static void ioport_write(int index, uint32_t address, uint32_t data)
{
static IOPortWriteFunc * const default_func[3] = {
default_ioport_writeb,
default_ioport_writew,
default_ioport_writel
};
IOPortWriteFunc *func = ioport_write_table[index][address];
if (!func)
func = default_func[index];
RR_DO_RECORD_OR_REPLAY(
/*action=*/func(ioport_opaque[address], address, data),
/*record=*/RR_NO_ACTION,
/*replay=*/RR_NO_ACTION,
/*location=*/RR_CALLSITE_IOPORT_WRITE);
}
static uint32_t ioport_read(int index, uint32_t address)
{
uint32_t result;
static IOPortReadFunc * const default_func[3] = {
default_ioport_readb,
default_ioport_readw,
default_ioport_readl
};
IOPortReadFunc *func = ioport_read_table[index][address];
if (!func)
func = default_func[index];
RR_DO_RECORD_OR_REPLAY(
/*action=*/result = func(ioport_opaque[address], address),
/*record=*/rr_input_4((uint32_t *)&result),
/*replay=*/rr_input_4((uint32_t *)&result),
/*location=*/RR_CALLSITE_IOPORT_READ);
return result;
}
void helper_rdtsc(CPUX86State *env)
{
uint64_t val;
if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
raise_exception_ra(env, EXCP0D_GPF, GETPC());
}
cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0, GETPC());
#ifdef CONFIG_SOFTMMU
RR_DO_RECORD_OR_REPLAY(
/*action=*/val = cpu_get_tsc(env) + env->tsc_offset,
/*record=*/rr_input_8(&val),
/*replay=*/rr_input_8(&val),
/*location=*/RR_CALLSITE_RDTSC);
#else
val = cpu_get_tsc(env) + env->tsc_offset;
#endif
env->regs[R_EAX] = (uint32_t)(val);
env->regs[R_EDX] = (uint32_t)(val >> 32);
}
