/**
* FchInitEnvSataIde2Ahci - Config SATA Ide2Ahci controller
* before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde2Ahci (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
//
// Device ID
//
if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
}
//
// SSID
//
if (LocalCfgPtr->Sata.SataAhciSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
}
}
/**
* FchInitLateSataIde2Ahci - Prepare SATA Ide2Ahci controller to
* boot to OS.
*
* - Set class ID to Ide2Ahci (if set to Ide2Ahci * Mode)
* - Enable Ide2Ahci interrupt
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSataIde2Ahci (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//program the AHCI class code
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01060100, StdHeader);
//
// Device ID
//
if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_AMDAHCI_DID, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_AHCI_DID, StdHeader);
}
SataBar5setting (LocalCfgPtr, &Bar5);
//
//Set interrupt enable bit
//
RwMem ((Bar5 + 0x04), AccessWidth8, (UINT32)~0, BIT1);
ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
}
/**
* FchProgramSataPhy - Program Sata PHY registers
*
* @param[in] StdHeader
*
*/
VOID
FchProgramSataPhy (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
SATA_PHY_SETTING *PhyTablePtr;
UINT16 Index;
UINT32 SquelchValue[2];
UINT8 PortNum;
PhyTablePtr = &SataPhyTable[0];
for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
++PhyTablePtr;
}
SquelchValue[0] = (0x07 << 9);
SquelchValue[1] = (0x07 << 9);
for (PortNum = 0; PortNum < 2; PortNum ++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader);
}
}
/**
* FchInitEnvPcib - Config Pcib controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvPcib (
IN VOID *FchDataPtr
)
{
UINT8 VerbPciClks;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Early post initialization of pci config space
//
ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);
//
//Disable or Enable PCI Clks based on input
//
VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, ~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
//
// PCIB MSI
//
if (LocalCfgPtr->Pcib.PcibMsiEnable) {
RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG40, AccessWidth8, ~BIT3, BIT3, StdHeader);
}
}
EFI_STATUS
EFIAPI
FchCsResumeCallBack (
IN RESUME_TYPE ResumeType,
IN VOID *Context
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) Context;
StdHeader = LocalCfgPtr->StdHeader;
if (ResumeType == ResumeFromConnectedStandby) {
RwAlink (FCH_ABCFG_REG80 | (UINT32) (ABCFG << 29), ~(UINT32) BIT0, BIT0, StdHeader);
RwAlink (FCH_ABCFG_REG80 | (UINT32) (ABCFG << 29), ~(UINT32) (0x3 << 17), (UINT32) (0x3 << 17), StdHeader);
RwAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), 0xFFE00000, BIT20 + 0x00FEE, StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), 0xFFFFF000, 0x7FF, StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~(UINT32) BIT21, BIT21, StdHeader);
RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~(UINT32) BIT16, BIT16, StdHeader);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~(UINT32) (BIT29 + BIT31), (UINT32) (BIT29 + BIT31), StdHeader);
RwAlink (FCH_ABCFG_REG10056 | (UINT32) (ABCFG << 29), 0xFFFFC00, 0x310, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), 0xFE00FFEA, 0x01100014, StdHeader);
//Add SATA PHY STAGGERING SEQUENCE to fix SSD disk detection issue
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth32, (UINT32) (~ (0x1 << 16)), (UINT32) (0x1 << 16), StdHeader);
FchStall (1, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth32, (UINT32) (~ (0x1 << 16)), (UINT32) (0x0 << 16), StdHeader);
return EFI_SUCCESS;
} else {
return EFI_UNSUPPORTED;
}
}
/**
* SoftwareDisableImc - Software disable IMC strap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareDisableImc (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG84), AccessWidth32, &ABStrapOverrideReg);
ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte |= BIT1; // Set GenImcClkEn to 1
WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}
/**
* FchGppSetAspm - Set GPP ASPM
*
*
* @param[in] PciAddress PCI Address.
* @param[in] LxState Lane State.
* @param[in] StdHeader
*
*/
VOID
FchGppSetAspm (
IN UINT32 PciAddress,
IN UINT8 LxState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapOffset;
UINT8 DeviceType;
PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader);
if (PcieCapOffset) {
//
// Read link capabilities register (0x0C[11:10] - ASPM support)
//
ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT2) {
DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
//
// Set ASPM state in link control register
//
RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader);
}
}
/**
* ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller
* before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchEnvHwAcpiPciReg (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Early post initialization of pci config space
//
ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]), sizeof (FchYangtzeInitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
}
if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2);
}
ProgramPcieNativeMode (FchDataPtr);
}
/**
* FchInitResetImc - Config Imc controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetImc (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 PortStatusByte;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) {
//
// EC is disabled by jumper setting or board config
//
RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader);
// Set PMIO_C4[5] to 1 for cold reset
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xDF, 0x20);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08);
FchInitResetEc (FchDataPtr);
}
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018A40, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
VOID
FchSataRestore (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, 0x11);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0, 0x04140006, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), 0, StdHeader);
FchStall (1000, StdHeader);
FchInitEnvSata (FchDataPtr);
FchInitLateSata (FchDataPtr);
}
/**
* FchSpiUnlock - Fch SPI Unlock
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchSpiUnlock (
IN VOID *FchDataPtr
)
{
UINT32 SpiRomBase;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress;
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader);
RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, ~(UINT32) (BIT22 + BIT23), (BIT22 + BIT23));
}
/**
* sataDisableWriteAccess - Disable Sata PCI configuration space
*
* @param[in] StdHeader
*
*/
VOID
SataDisableWriteAccess (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
//
// Disable write access to PCI header
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, ~(UINT32) BIT0, 0, StdHeader);
}
/**
* sataEnableWriteAccess - Enable Sata PCI configuration space
*
* @param[in] StdHeader
*
*/
VOID
SataEnableWriteAccess (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
//
// BIT0 Enable write access to PCI header
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT0, StdHeader);
}
VOID
FchRecoveryProgramSataPhy (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
SATA_PHY_SETTING *PhyTablePtr;
UINT16 Index;
PhyTablePtr = &SataPhyTable[0];
for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
++PhyTablePtr;
}
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x110, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x10, StdHeader);
}
/**
* FchInitEnvAzalia - Config Azalia controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAzalia (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~(UINT32) BIT0, 0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~(UINT32) BIT0, BIT0);
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG4C, AccessWidth8, ~(UINT32) BIT0, BIT0, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG44, AccessWidth32, ~(UINT32) BIT8, BIT8, StdHeader);
}
}
}
/**
* FchInitEnvLpc - Config LPC controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvLpc (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// LPC CFG programming
//
//
// Turn on and configure LPC clock (48MHz)
//
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 2 << 19);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT7, 0);
//
// Initialization of pci config space
//
FchInitEnvLpcProgram (FchDataPtr);
//
// SSID for LPC Controller
//
if (LocalCfgPtr->Spi.LpcSsid != 0 ) {
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader);
}
//
// LPC MSI
//
if ( LocalCfgPtr->Spi.LpcMsiEnable ) {
RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
}
}
/**
* FchCombineSigRomInfo - Combine SIG ROM information
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
UINT32
FchCombineSigRomInfo (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINTN RomSigStartingAddr;
UINT32 RomStore[NUM_OF_ROMSIG_FILED];
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 SelNum;
UINT32 RomSignatureTag;
UINT16 XhciFwTag;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
GetRomSigPtr (&RomSigStartingAddr, StdHeader);
RomSignatureTag = ACPIMMIO32 (RomSigStartingAddr);
if ( RomSignatureTag == ROMSIG_SIG ) {
for ( SelNum = 0; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) {
RomStore[SelNum] = ACPIMMIO32 (RomSigStartingAddr + (SelNum << 2));
}
} else {
RomStore[XHCI_FILED_NUM] = 0;
}
if ( LocalCfgPtr->Usb.UserDefineXhciRomAddr != NULL ) {
RomStore[XHCI_FILED_NUM] = LocalCfgPtr->Usb.UserDefineXhciRomAddr;
}
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
for ( SelNum = 1; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) {
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ~(UINT32) (BIT2 + BIT1 + BIT0), (BIT2 + SelNum), StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ROMSIG_CFG_MASK, RomStore[SelNum], StdHeader);
}
XhciFwTag = (UINT16) ACPIMMIO32 (RomStore[XHCI_FILED_NUM]);
if ( XhciFwTag != INSTRUCTION_RAM_SIG ) {
RomStore[XHCI_FILED_NUM] = 0;
}
return RomStore[XHCI_FILED_NUM];
}
/**
*
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAzalia (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, BIT0);
RwPci ((((0x14<<3)+2) << 16) + 0x4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
RwPci ((((0x14<<3)+2) << 16) + 0x44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader);
RwPci ((((0x14<<3)+2) << 16) + 0x60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader);
}
}
}
/**
* EhciSetDebugPort - Config Ehci Debug Port
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] DebugPortSel Debug port selector.
*/
VOID
EhciSetDebugPort (
IN UINT32 Value,
IN FCH_DATA_BLOCK *FchDataPtr,
IN UINT8 DebugPortSel
)
{
AMD_CONFIG_PARAMS *StdHeader;
UINT16 UsbLegacySupportControl;
UINT16 UsbLegacySupportStatus;
UINT16 UsbPciCommand;
StdHeader = FchDataPtr->StdHeader;
if (DebugPortSel == 0) {
return;
}
if (!FchDataPtr->Usb.EhciSimpleDebugPort) {
ReadPci ((UINT32) Value + FCH_EHCI_REGA4 + 2, AccessWidth16, &UsbLegacySupportStatus, StdHeader);
if ((UsbLegacySupportStatus & BIT14) == 0) {
return;
}
ReadPci ((UINT32) Value + FCH_EHCI_REGA4, AccessWidth16, &UsbLegacySupportControl, StdHeader);
if ((UsbLegacySupportControl & BIT14) == 0) {
return;
}
ReadPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth16, &UsbPciCommand, StdHeader);
if ((UsbPciCommand & BIT1) != 0) {
return;
}
}
DebugPortSel--;
DebugPortSel &= (BIT0 + BIT1);
RwPci ((UINT32) Value + FCH_EHCI_REG90 + 2, AccessWidth8, ~(UINT32) (BIT0 + BIT1), DebugPortSel, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG90, AccessWidth32, ~(UINT32) BIT18, BIT18, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REGA4, AccessWidth16, 0, BIT0 + BIT13, StdHeader);
}
/**
* ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchHwAcpiResetP (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader);
RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader);
RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
}
/**
* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvProgramSataPciRegs (
IN VOID *FchDataPtr
)
{
UINT8 *PortRegByte;
UINT16 *PortRegWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Caculate SataPortReg for SATA_ESP_PORT
//
PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
FchSataCombineControlDataWord (PortRegWord);
PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
// *
// Enables the SATA watchdog timer register prior to the SATA BIOS post
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader);
// *
// SATA PCI Watchdog timer setting
// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader);
//
// BIT4: Enable fast boot (SpeedupXPBoot)
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040), AccessWidth8, 0xef, 0, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
//
// Unused SATA Ports Disabled
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 Bar5;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SataBar5setting (LocalCfgPtr, &Bar5);
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018A00, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018F00, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x07, StdHeader);
// Clear AHCI Enable during POST time. DE is investigating when/how to restore this bit before goes to OS boot.
RwMem ((Bar5 + FCH_SATA_BAR5_REG04), AccessWidth32, ~(UINT32) (BIT31), 0);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x00, StdHeader);
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
/**
* FchInitMidUsbOhci1 - Config USB1 OHCI controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidUsbOhci1 (
IN VOID *FchDataPtr
)
{
UINT32 DeviceId;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
DeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
if (LocalCfgPtr->Usb.OhciSsid != 0 ) {
RwPci ((USB1_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
}
}
/**
* FchGppForceGen2R - Set GPP to Gen2
*
*
* @param[in] FchGpp Pointer to Fch GPP configuration structure
* @param[in] ActivePorts Activate Ports
* @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
*
*/
VOID
FchGppForceGen2R (
IN FCH_GPP_R *FchGpp,
IN CONST UINT8 ActivePorts,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PortId;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
if (ActivePorts & (1 << PortId)) {
RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader);
RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader);
RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, ~BIT13, 0, StdHeader);
RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader);
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader);
(&FchGpp->PortCfg[PortId])->PortIsGen2 = TRUE;
}
}
}
/**
* FchProgramSataPhy - Program Sata PHY registers
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchProgramSataPhy (
IN VOID *FchDataPtr
)
{
SATA_PHY_SETTING *PhyTablePtr;
UINT16 Index;
UINT8 eFuseSquelchValue;
UINT32 SquelchValue[2];
UINT8 PortNum;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
PhyTablePtr = &SataPhyTable[0];
for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
++PhyTablePtr;
}
SquelchValue[0] = (0x07 << 9);
SquelchValue[1] = (0x07 << 9);
eFuseSquelchValue = 0;
//
// SATA RX register settings need to be updated to pass Gen3 RX JTOL
//
for (PortNum = 0; PortNum < 2; PortNum ++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0xF << 24)), (UINT32) (0xF << 24), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x3 << 22)), (UINT32) (0x2 << 22), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1F << 17)), (UINT32) (0x07 << 17), StdHeader); //ENH454807
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1 << 16)), (UINT32) (0x1 << 16), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1 << 12)), 0, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0xF << 5)), (UINT32) (0x4 << 5), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1F)), (UINT32) ( 0x6), StdHeader);
}
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x1F << 2 ), StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8, AccessWidth8, 0xDF, 0x20);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 1);
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1, AccessWidth8, &eFuseSquelchValue);
if ( (eFuseSquelchValue & BIT4) == BIT4) {
SquelchValue[0] = ( UINT32 ) ( eFuseSquelchValue & 0xE0);
SquelchValue[0] = (SquelchValue[0] << 4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 2);
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1, AccessWidth8, &eFuseSquelchValue);
SquelchValue[1] = ( UINT32 ) ( eFuseSquelchValue & 0x07);
SquelchValue[1] = (SquelchValue[1] << 9);
} else {
SquelchValue[0] = (0x05 << 9);
SquelchValue[1] = (0x05 << 9);
}
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8, AccessWidth8, 0xDF, 0);
for (PortNum = 0; PortNum < 2; PortNum ++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x04 << 2 ), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x03 << 2 ), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x010, StdHeader);
}
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + 0), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, (UINT32) (~(0x7FF << 0)), (UINT32) ( (LocalCfgPtr->Sata.SataDbgTX_DRV_STR << 8) | LocalCfgPtr->Sata.SataDbgTX_DE_EMPH_STR ), StdHeader);
}
/**
* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvProgramSataPciRegs (
IN VOID *FchDataPtr
)
{
UINT8 *PortRegByte;
UINT16 *PortRegWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Caculate SataPortReg for SATA_ESP_PORT
//
PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
FchSataCombineControlDataWord (PortRegWord);
PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
//
// Reset DevSlp S5 Pin here
//
if (LocalCfgPtr->Sata.SataDevSlpPort0) {
if (LocalCfgPtr->FchRunTime.SataDevSlpPort0S5Pin) {
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (LocalCfgPtr->FchRunTime.SataDevSlpPort0S5Pin << 2)) |= BIT22 + BIT23;
}
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_10C_GPIO55_AGPI067) &= ~ BIT22;
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_10C_GPIO55_AGPI067) |= BIT23;
}
if (LocalCfgPtr->Sata.SataDevSlpPort1) {
if (LocalCfgPtr->FchRunTime.SataDevSlpPort1S5Pin) {
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (LocalCfgPtr->FchRunTime.SataDevSlpPort1S5Pin << 2)) |= BIT22 + BIT23;
}
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_118_GPIO59_AGPI070) &= ~ BIT22;
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_118_GPIO59_AGPI070) |= BIT23;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
// *
// Enables the SATA watchdog timer register prior to the SATA BIOS post
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44), AccessWidth8, 0xff, BIT0, StdHeader);
// *
// SATA PCI Watchdog timer setting
// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44 + 2), AccessWidth8, 0, 0x20, StdHeader);
//
// BIT4: Enable fast boot (SpeedupXPBoot)
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xef, 0, StdHeader);
//
// HBA Initialization setting
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
//
// Unused SATA Ports Disabled
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
//
// Disable Prefetch In Ahci Mode
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 1), AccessWidth8, 0xDF, BIT5, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth32, (UINT32) (~ (0x3 << 1)), (UINT32) (0x01 << 1), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x1 << 3)), (UINT32) (0x01 << 3), StdHeader);
}
/**
* FchOhciInitAfterPciInit - Config USB OHCI controller after
* PCI emulation
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] FchDataPtr Fch configuration structure pointer.
*/
VOID
FchOhciInitAfterPciInit (
IN UINT32 Value,
IN FCH_DATA_BLOCK *FchDataPtr
)
{
//
// Disable the MSI capability of USB host controllers
//
RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, 0xFF, BIT0, FchDataPtr->StdHeader);
RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~(BIT0 + BIT5 + BIT12), 0, FchDataPtr->StdHeader);
//
// USB SMI Handshake
//
RwPci ((UINT32) Value + 0x50 + 1, AccessWidth8, (UINT32)~BIT4, 0x00, FchDataPtr->StdHeader);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
if ( FchDataPtr->Usb.OhciSsid != 0 ) {
RwPci ((UINT32) Value + FCH_OHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.OhciSsid, FchDataPtr->StdHeader);
}
}
//
// recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
//OHCI 0_PCI_Config 0x50[30] = 1
//
RwPci ((UINT32) Value + 0x50 + 3, AccessWidth8, (UINT32)~BIT6, (UINT32)BIT6, FchDataPtr->StdHeader);
//
// L1 Early Exit
// Set OHCI Arbiter Mode.
// Set Enable Global Clock Gating.
//
RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth8, (UINT32)~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), (UINT32)(BIT0 + BIT4 + BIT7), FchDataPtr->StdHeader);
RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth16, (UINT32)~(BIT4 + BIT5 + BIT8), (UINT32)(BIT4 + BIT5 + BIT8), FchDataPtr->StdHeader);
//
// Enable OHCI SOF Synchronization.
// Enable OHCI Periodic List Advance.
//
RwPci ((UINT32) Value + 0x50 + 2, AccessWidth8, (UINT32)~(BIT3 + BIT4 + BIT6 + BIT7), (UINT32)(BIT3 + BIT4 + BIT6 + BIT7), FchDataPtr->StdHeader);
if ( FchDataPtr->Usb.UsbMsiEnable) {
RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, (UINT32)~BIT0, 0x00, FchDataPtr->StdHeader);
RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT5, (UINT32)BIT5, FchDataPtr->StdHeader);
}
// full-speed false crc errors detected. Issue - fix enable
RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth32, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10), FchDataPtr->StdHeader);
// SB02643
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4, AccessWidth8, (UINT32)~BIT7, (UINT32)BIT7);
// RPR 7.27 SB02686
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, (UINT32)~BIT2, (UINT32)BIT2);
// SB02698
RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT0, 0, FchDataPtr->StdHeader);
}
/**
* FchInitLateSata - Prepare SATA controller to boot to OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSata (
IN VOID *FchDataPtr
)
{
UINT8 SataPciCommandByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Return immediately is sata controller is not enabled
//
if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
return;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
//
// Set Sata Controller Memory & IO access enable
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
//
// Call Sub-function for each Sata mode
//
if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
FchInitLateSataAhci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
FchInitLateSataIde2Ahci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
FchInitLateSataIde ( LocalCfgPtr );
}
if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
FchInitLateSataRaid ( LocalCfgPtr );
}
FchInitLateProgramSataRegs ( LocalCfgPtr );
//
// Restore Sata Controller Memory & IO access status
//
WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
//
// Set Sata PCI Configuration Space Write disable
//
SataDisableWriteAccess (StdHeader);
}
/**
* FchInitMidAzalia - Config Azalia controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidAzalia (
IN VOID *FchDataPtr
)
{
UINT8 Index;
BOOLEAN EnableAzalia;
UINT32 PinRouting;
UINT8 ChannelNum;
UINT8 AzaliaTempVariableByte;
UINT16 AzaliaTempVariableWord;
UINT32 BAR0;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
EnableAzalia = FALSE;
ChannelNum = 0;
AzaliaTempVariableByte = 0;
AzaliaTempVariableWord = 0;
BAR0 = 0;
if ( LocalCfgPtr->Azalia.AzaliaEnable == 1 ) {
return;
} else {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth8, (UINT32)~BIT1, BIT1, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaSsid != 0 ) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader);
}
ReadPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG10, AccessWidth32, &BAR0, StdHeader);
if ( BAR0 != 0 ) {
if ( BAR0 != 0xFFFFFFFF ) {
BAR0 &= ~(0x03FFF);
EnableAzalia = TRUE;
}
}
}
if ( EnableAzalia ) {
//
// Get SDIN Configuration
//
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x01);
}
Index = 11;
do {
ReadMem ( BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
AzaliaTempVariableByte |= BIT0;
WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
FchStall (1000, StdHeader);
ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
Index--;
} while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) );
if ( Index == 0 ) {
return;
}
FchStall (1000, StdHeader);
ReadMem ( BAR0 + FCH_AZ_BAR_REG0E, AccessWidth16, &AzaliaTempVariableWord);
if ( AzaliaTempVariableWord & 0x0F ) {
//
//at least one azalia codec found
//
//PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin;
//new structure need make up PinRouting
//need adjust later!!!
//
PinRouting = 0;
PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0;
do {
if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) {
ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum);
}
PinRouting >>= 8;
ChannelNum++;
} while ( ChannelNum != 4 );
} else {
//
//No Azalia codec found
//
if ( LocalCfgPtr->Azalia.AzaliaEnable != 2 ) {
