static int s3c64xx_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai) { /* configure GPIO for i2s port */ switch (dai->id) { case 0: s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK); s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI); s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_DO); break; case 1: s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK); s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_DO); break; case 2: s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); break; } return 0; }
static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) { s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); return 0; }
static int s3c64xx_i2sv4_probe(struct platform_device *pdev, struct snd_soc_dai *dai) { /* configure GPIO for i2s port */ s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); return 0; }
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { unsigned int gpio; unsigned int end; end = S3C64XX_GPH(2 + width); /* Set all the necessary GPG pins to special-function 0 */ for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); }
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) { unsigned int base; switch (pdev->id) { case 0: base = S3C64XX_GPD(0); break; case 1: base = S3C64XX_GPE(0); break; case 2: s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5)); return 0; default: printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", pdev->id); return -EINVAL; } s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3)); return 0; }
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { /* Set all the necessary GPH pins to special-function 3 */ s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3)); /* Set all the necessary GPC pins to special-function 3 */ s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3)); }
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { unsigned int gpio; unsigned int end; end = S3C64XX_GPH(2 + width); /* Set all the necessary GPG pins to special-function 0 */ for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } #if 1 /* only ch0 will have card detection pin. by scsuh. */ s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); #endif }
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { unsigned int gpio; unsigned int end; end = S3C64XX_GPH(6 + width); /* Set all the necessary GPH pins to special-function 1 */ for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } /* Set all the necessary GPC pins to special-function 1 */ for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } }
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; end = S3C64XX_GPH(2 + width); /* Set all the necessary GPG pins to special-function 0 */ for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); } }
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPH pins to special-function 2 */ s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2)); if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); } }
static int __init smdk6410_init(void) { int ret; unsigned int *reg_GPHCON1; unsigned int *reg_GPCCON; reg_GPHCON1 = ioremap(0x7f0080e4,0x100); reg_GPCCON = ioremap(0x7f008040,0x100); s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); writel(0x50550000, reg_GPCCON); writel(0x00000055, reg_GPHCON1); s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); /* pull-up-enable, pull-down-disable*/ s3c_gpio_setpull(S3C64XX_GPH(6), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPH(7), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPH(8), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPH(9), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); s3c_gpio_setpull(S3C64XX_GPC(7), S3C_GPIO_PULL_UP); smdk6410_snd_device = platform_device_alloc("soc-audio", -1); if (!smdk6410_snd_device) return -ENOMEM; platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata); smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev; ret = platform_device_add(smdk6410_snd_device); if (ret) platform_device_put(smdk6410_snd_device); return ret; }
.to_irq = s3c64xx_gpio2int_gpm, }, }, }; int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) { return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; } static struct s3c_gpio_chip gpio_4bit2[] = { { .base = S3C64XX_GPH_BASE + 0x4, .config = &gpio_4bit_cfg_eint0111, .chip = { .base = S3C64XX_GPH(0), .ngpio = S3C64XX_GPIO_H_NR, .label = "GPH", }, }, { .base = S3C64XX_GPK_BASE + 0x4, .config = &gpio_4bit_cfg_noint, .chip = { .base = S3C64XX_GPK(0), .ngpio = S3C64XX_GPIO_K_NR, .label = "GPK", }, }, { .base = S3C64XX_GPL_BASE + 0x4, .config = &gpio_4bit_cfg_eint0011, .chip = {