Beispiel #1
0
Datei: pm.c Projekt: 08opt/linux
static void s3c2410_pm_prepare(void)
{
	/* ensure at least GSTATUS3 has the resume address */

	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);

	S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
	S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));

	if (machine_is_h1940()) {
		void *base = phys_to_virt(H1940_SUSPEND_CHECK);
		unsigned long ptr;
		unsigned long calc = 0;

		/* generate check for the bootloader to check on resume */

		for (ptr = 0; ptr < 0x40000; ptr += 0x400)
			calc += __raw_readl(base+ptr);

		__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
	}

	/* RX3715 and RX1950 use similar to H1940 code and the
	 * same offsets for resume and checksum pointers */

	if (machine_is_rx3715() || machine_is_rx1950()) {
		void *base = phys_to_virt(H1940_SUSPEND_CHECK);
		unsigned long ptr;
		unsigned long calc = 0;

		/* generate check for the bootloader to check on resume */

		for (ptr = 0; ptr < 0x40000; ptr += 0x4)
			calc += __raw_readl(base+ptr);

		__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
	}

	if ( machine_is_aml_m5900() )
		s3c2410_gpio_setpin(S3C2410_GPF(2), 1);

	if (machine_is_rx1950()) {
		/* According to S3C2442 user's manual, page 7-17,
		 * when the system is operating in NAND boot mode,
		 * the hardware pin configuration - EINT[23:21] –
		 * must be set as input for starting up after
		 * wakeup from sleep mode
		 */
		s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
		s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
		s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
	}
}
Beispiel #2
0
/**
 * s3c_pm_runcheck() - helper to check a resource on restore.
 * @res: The resource to check
 * @vak: Pointer to list of CRC32 values to check.
 *
 * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
 * function runs the given memory resource checking it against the stored
 * CRC to ensure that memory is restored. The function tries to skip as
 * many of the areas used during the suspend process.
 */
static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
{
	void *save_at = phys_to_virt(s3c_sleep_save_phys);
	unsigned long addr;
	unsigned long left;
	void *stkpage;
	void *ptr;
	u32 calc;

	stkpage = (void *)((u32)&calc & ~PAGE_MASK);

	for (addr = res->start; addr < res->end;
	     addr += CHECK_CHUNKSIZE) {
		left = res->end - addr;

		if (left > CHECK_CHUNKSIZE)
			left = CHECK_CHUNKSIZE;

		ptr = phys_to_virt(addr);

		if (in_region(ptr, left, stkpage, 4096)) {
			S3C_PMDBG("skipping %08lx, has stack in\n", addr);
			goto skip_check;
		}

		if (in_region(ptr, left, crcs, crc_size)) {
			S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
			goto skip_check;
		}

		if (in_region(ptr, left, save_at, 32*4 )) {
			S3C_PMDBG("skipping %08lx, has save block in\n", addr);
			goto skip_check;
		}

		/* calculate and check the checksum */

		calc = crc32_le(~0, ptr, left);
		if (calc != *val) {
			printk(KERN_ERR "Restore CRC error at "
			       "%08lx (%08x vs %08x)\n", addr, calc, *val);

			S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
			    addr, calc, *val);
		}

	skip_check:
		val++;
	}

	return val;
}
Beispiel #3
0
static void s3c2410_pm_prepare(void)
{
	/* ensure at least GSTATUS3 has the resume address */
	
	
	{
		volatile unsigned long *ptr = phys_to_virt(0x30000900);
		*ptr = 0x55;
	}

	__raw_writel(0x7, S3C2410_GSTATUS2);
	S3C_PMDBG("GSTATUS2 0x%08x\n", __raw_readl(S3C2410_GSTATUS2));

	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
	S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
	
	S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
	

	if (machine_is_h1940()) {
		void *base = phys_to_virt(H1940_SUSPEND_CHECK);
		unsigned long ptr;
		unsigned long calc = 0;

		/* generate check for the bootloader to check on resume */

		for (ptr = 0; ptr < 0x40000; ptr += 0x400)
			calc += __raw_readl(base+ptr);

		__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
	}

	/* the RX3715 uses similar code and the same H1940 and the
	 * same offsets for resume and checksum pointers */

	if (machine_is_rx3715()) {
		void *base = phys_to_virt(H1940_SUSPEND_CHECK);
		unsigned long ptr;
		unsigned long calc = 0;

		/* generate check for the bootloader to check on resume */

		for (ptr = 0; ptr < 0x40000; ptr += 0x4)
			calc += __raw_readl(base+ptr);

		__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
	}

	if ( machine_is_aml_m5900() )
		s3c2410_gpio_setpin(S3C2410_GPF(2), 1);

}
Beispiel #4
0
void s3c_pm_do_restore(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
#if defined(CONFIG_CPU_EXYNOS4210)
		S3C_PMDBG("restore %p (restore %08lx, was %08x)\n",
			  ptr->reg, ptr->val, __raw_readl(ptr->reg));
#else
		S3C_PMDBG("restore %p (restore %08lx, was %08x)\n",
		       ptr->reg, ptr->val, __raw_readl(ptr->reg));
#endif

		__raw_writel(ptr->val, ptr->reg);
	}
}
Beispiel #5
0
/**
 * s3c_pm_do_save() - save a set of registers for restoration on resume.
 * @ptr: Pointer to an array of registers.
 * @count: Size of the ptr array.
 *
 * Run through the list of registers given, saving their contents in the
 * array for later restoration when we wakeup.
 */
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		ptr->val = __raw_readl(ptr->reg);
		S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
	}
}
Beispiel #6
0
void s3c_pm_do_restore(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		S3C_PMDBG("restore %p (restore %08lx, was %08x)\n",
		       ptr->reg, ptr->val, __raw_readl(ptr->reg));

		__raw_writel(ptr->val, ptr->reg);
	}
}
Beispiel #7
0
static int exynos_suspend_enter(suspend_state_t state)
{
	int ret;

	s3c_pm_debug_init();

	S3C_PMDBG("%s: suspending the system...\n", __func__);

	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
			exynos_irqwake_intmask, exynos_get_eint_wake_mask());

	if (exynos_irqwake_intmask == -1U
	    && exynos_get_eint_wake_mask() == -1U) {
		pr_err("%s: No wake-up sources!\n", __func__);
		pr_err("%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	s3c_pm_save_uarts();
	if (pm_data->pm_prepare)
		pm_data->pm_prepare();
	flush_cache_all();
	s3c_pm_check_store();

	ret = call_firmware_op(suspend);
	if (ret == -ENOSYS)
		ret = cpu_suspend(0, pm_data->cpu_suspend);
	if (ret)
		return ret;

	if (pm_data->pm_resume_prepare)
		pm_data->pm_resume_prepare();
	s3c_pm_restore_uarts();

	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
			pmu_raw_readl(S5P_WAKEUP_STAT));

	s3c_pm_check_restore();

	S3C_PMDBG("%s: resuming the system...\n", __func__);

	return 0;
}
Beispiel #8
0
static void s3c64xx_irq_pm_resume(void)
{
	struct irq_grp_save *grp = eint_grp_save;
	int i;

	S3C_PMDBG("%s: resuming IRQs\n", __func__);

	s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));

	for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
		__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);

	for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
		__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
		__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
		__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
	}

	S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
}
Beispiel #9
0
void s3c_pm_check_prepare(void)
{
	crc_size = 0;

	s3c_pm_run_sysram(s3c_pm_countram, &crc_size);

	S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);

	crcs = kmalloc(crc_size+4, GFP_KERNEL);
	if (crcs == NULL)
		printk(KERN_ERR "Cannot allocated CRC save area\n");
}
Beispiel #10
0
static u32 *s3c_pm_countram(struct resource *res, u32 *val)
{
	u32 size = (u32)resource_size(res);

	size += CHECK_CHUNKSIZE-1;
	size /= CHECK_CHUNKSIZE;

	S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
		  (unsigned long)res->start, (unsigned long)res->end, size);

	*val += size * sizeof(u32);
	return val;
}
Beispiel #11
0
/* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
*/
static void __maybe_unused s3c_pm_show_resume_irqs(int start,
						   unsigned long which,
						   unsigned long mask)
{
	int i;

	which &= ~mask;

	for (i = 0; i <= 31; i++) {
		if (which & (1L<<i))
			S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
	}
}
Beispiel #12
0
static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
	unsigned long irqstate;
	unsigned long pinstate;
	int irq = gpio_to_irq(pin);

	if (irqoffs < 4)
		irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
	else
		irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);

	pinstate = s3c_gpio_getcfg(pin);

	if (!irqstate) {
		if (pinstate == S3C2410_GPIO_IRQ)
			S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
	} else {
		if (pinstate == S3C2410_GPIO_IRQ) {
			S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
			s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
		}
	}
}
Beispiel #13
0
static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
{
	void __iomem *regs = S3C_VA_UARTx(uart);

	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
	save->ucon = __raw_readl(regs + S3C2410_UCON);
	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
	save->umcon = __raw_readl(regs + S3C2410_UMCON);
	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);

	if (pm_uart_udivslot)
		save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);

	S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
		  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
}
Beispiel #14
0
void s3c_pm_save_uarts(void)
{
	void __iomem *regs = s3c_pm_uart_base();
	struct pm_uart_save *save = &uart_save;

	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
	save->ucon = __raw_readl(regs + S3C2410_UCON);
	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
	save->umcon = __raw_readl(regs + S3C2410_UMCON);
	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);

	if (!soc_is_s3c2410())
		save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);

	S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
		  regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
}
Beispiel #15
0
static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
{
	while (ptr != NULL) {
		if (ptr->child != NULL)
			s3c_pm_run_res(ptr->child, fn, arg);

		if ((ptr->flags & IORESOURCE_MEM) &&
		    strcmp(ptr->name, "System RAM") == 0) {
			S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
				  (unsigned long)ptr->start,
				  (unsigned long)ptr->end);
			arg = (fn)(ptr, arg);
		}

		ptr = ptr->sibling;
	}
}
Beispiel #16
0
static int s3c64xx_irq_pm_suspend(void)
{
	struct irq_grp_save *grp = eint_grp_save;
	int i;

	S3C_PMDBG("%s: suspending IRQs\n", __func__);

	s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));

	for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
		irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);

	for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
		grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
		grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
		grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
	}

	return 0;
}
Beispiel #17
0
static int s3c_pm_enter(suspend_state_t state)
{
	static unsigned long regs_save[16];

	

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	

	s3c_sleep_save_phys = virt_to_phys(regs_save);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	

	pm_cpu_prep();

	

	flush_cache_all();

	s3c_pm_check_store();

	

	s3c_pm_arch_stop_clocks();

	

	s3c_cpu_save(regs_save);

	

	cpu_init();

	

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();

	s3c_pm_debug_init();

	

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
Beispiel #18
0
static int s3c_pm_enter(suspend_state_t state)
{
	/*                                              */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/*                                                             
                                                              
                               
 */

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/*                                                              */

	samsung_pm_save_gpios();
	samsung_pm_saved_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/*                                    */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/*                               */

	pm_cpu_prep();

	/*                         */

	flush_cache_all();

	s3c_pm_check_store();

	/*                          */

	s3c_pm_arch_stop_clocks();

	/*                                                 
                                                                
                        */

	cpu_suspend(0, pm_cpu_sleep);

	/*                          */

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	samsung_pm_restore_gpios();
	s3c_pm_restored_gpios();

	s3c_pm_debug_init();

	/*                                             */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/*                         */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/*                             */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
Beispiel #19
0
static int s3c_pm_enter(suspend_state_t state)
{
	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_saved_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	printk(KERN_ALERT "PM: SLEEP\n");

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();
	s3c_pm_restored_gpios();

	s3c_pm_debug_init();

	/* restore the system state */

	if (pm_cpu_restore)
		pm_cpu_restore();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
static int s3c_pm_enter(suspend_state_t state)
{
	static unsigned long regs_save[16];

	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

	s3c_sleep_save_phys = virt_to_phys(regs_save);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();


	s3c_config_sleep_gpio();
		
	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */


#if defined(CONFIG_WIMAX) || defined(CONFIG_WIMAX_MODULE)	//cky 20101116 WiMAX ext-interrupt
/* FIXME
	if (gpio_get_value(GPIO_WIMAX_EN))
	{
		DBG("WIMAX POWER ON!! Set WIMAX_INT as Ext-Int.\n");
		s3c_pm_set_eint(6, 0x0);	// WIMAX_INT: GPH0(6); LOW LEVEL DETECT
	}
*/
#endif

#ifdef FEATURE_FTM_SLEEP
	s3c_pm_check_auto_wakeup();
#endif

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* clear wakeup_stat register for next wakeup reason */
	__raw_writel(__raw_readl(S5P_WAKEUP_STAT), S5P_WAKEUP_STAT);

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	pmstats->sleep_count++;
	pmstats->sleep_freq = __raw_readl(S5P_CLK_DIV0);
	s3c_cpu_save(regs_save);
	pmstats->wake_count++;
	pmstats->wake_freq = __raw_readl(S5P_CLK_DIV0);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();

	fiq_glue_resume();
	local_fiq_enable();

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();
	s5pv210_restore_eint_group();

	s3c_pm_debug_init();

        /* restore the system state */

	if (pm_cpu_restore)
		pm_cpu_restore();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

#if defined(CONFIG_WIMAX) || defined(CONFIG_WIMAX_MODULE)	//cky 20101116 ext-int for wimax
/* FIXME
	if (gpio_get_value(GPIO_WIMAX_EN))
	{
		DBG("WIMAX POWER ON!! Set WIMAX_INT: INPUT.\n");
		s3c_pm_clear_eint(6);

		s3c_gpio_cfgpin(GPIO_WIMAX_INT, S3C_GPIO_INPUT);
		s3c_gpio_setpull(GPIO_WIMAX_INT, S3C_GPIO_PULL_UP);
	}
*/
#endif

#ifdef FEATURE_FTM_SLEEP
	if (ftm_sleep == 1)
	{
		ftm_sleep = 0;
		pm_disable_rtctic();
		wake_lock_timeout(&ftm_wake_lock, 11 * HZ);
		printk(KERN_DEBUG "pm_disable_rtctic...\n");
	}
#endif
	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
static int s3c_pm_enter(suspend_state_t state)
{
#ifndef USE_DMA_ALLOC
	static unsigned long regs_save[16];
#endif /* !USE_DMA_ALLOC */
	unsigned int tmp;


	//janged
	start_sleep_state = 1;
	/* ensure the debug is initialised (if enabled) */


	s3c_pm_debug_init();

#ifdef PROCESS_WKUP_SRC
   set_request_screenon(0);
#endif

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		start_sleep_state = 0;
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/
#ifdef DISABLE_WAKEUP_RTC
	s3c_irqwake_intmask = 0xFFFF; // none
#else
	s3c_irqwake_intmask = 0xFFFD; // rtc_alarm(1)
#endif

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		start_sleep_state = 0;
		return -EINVAL;
	}

	/* ktj, If pmic INT occured while entering sleep mode, then return. */
	if( __raw_readl(S5PV210_EINT2PEND) & 0x1 ) 
	{
		set_request_poweroff();
		printk(KERN_ERR "%s: Aborting sleep because pmic INT\n", __func__);
		start_sleep_state = 0;
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

#ifndef USE_DMA_ALLOC
	s3c_sleep_save_phys = virt_to_phys(regs_save);
#else
	__raw_writel(phy_regs_save, S5P_INFORM2);
#endif /* !USE_DMA_ALLOC */

	/* set flag for sleep mode idle2 flag is also reserved */
	__raw_writel(SLEEP_MODE, S5P_INFORM1);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

///	s3c_config_sleep_gpio(); /* ktj */

	/* set the irq configuration for wake */
#ifdef DISABLE_WAKEUP_WIFI_BT
//  s3c_irqwake_eintmask	= 0xfffcfffd;   // disable wifi, bt, 3g
    s3c_irqwake_eintmask	= 0xffdcfffd;   // disable wifi, bt
#else
    s3c_irqwake_eintmask	= 0xfbdcfbfd;
#endif
	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
		s3c_irqwake_intmask, s3c_irqwake_eintmask);

	/* Set wake up sources */
#if defined(CONFIG_MX100)   /* ktj */
    #ifdef DISABLE_WAKEUP_WIFI_BT
	s3c_pm_set_eint( 1, 0x02);  // power-key    : falling     
	s3c_pm_set_eint(16, 0x02);  // pmic-lowbat  : falling  
	s3c_pm_set_eint(17, 0x02);  // usb-adaptor  : falling 
	s3c_pm_set_eint(21, 0x01);  // cdma-host    : high
    #else
	s3c_pm_set_eint( 1, 0x02);  // power-key    : falling     
	s3c_pm_set_eint(10, 0x02);  // bt-host      : falling            
	s3c_pm_set_eint(16, 0x02);  // pmic-lowbat  : falling  
	s3c_pm_set_eint(17, 0x02);  // usb-adaptor  : falling
	s3c_pm_set_eint(21, 0x03);  // cdma-host    : rising  
	s3c_pm_set_eint(26, 0x03);  // wifi-host    : rising
    #endif
#endif

///	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */
	pm_cpu_prep();

	/* flush cache back to ram */
	flush_cache_all();

	s3c_pm_check_store();

	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	__raw_writel(tmp, S5P_WAKEUP_STAT);

s3c_config_sleep_gpio(); // move here

	/* Enable PS_HOLD pin to avoid reset failure */
    __raw_writel((0x5 << 12 | 0x1<<9 | 0x1<<8 | 0x1<<0),S5P_PSHOLD_CONTROL);

	/* send the cpu to sleep... */
	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */
	s3c_cpu_save(regs_save);

	/* restore the cpu state using the kernel's cpu init code. */
	cpu_init();

	/* restore the system state */

	s3c_pm_restore_core();
	
#if 0
	/*Reset the uart registers*/
	__raw_writel(0x0, S3C24XX_VA_UART3+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART2+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART1+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART0+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTP);
#endif
	
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();


#ifdef PROCESS_WKUP_SRC
	printk("\n\n\n\n\n");
    s3c_process_wakeup_source();    /* ktj proc_wkup_drc */	//janged move here
#endif

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	__raw_writel(tmp, S5P_WAKEUP_STAT);


#if 0 // ktj disable
    //Shanghai ewada
	tmp = __raw_readl(S5P_CLKGATE_IP3);
	__raw_writel(tmp | CP3_UNUSED_CLK_MASK, S5P_CLKGATE_IP3);
#endif
	
	s3c_pm_debug_init();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
	
	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	
	return 0;
}
Beispiel #22
0
// 2011-03-?? SV: Added
static void s3c_pm_safe_gpios(void)
{
	S3C_PMDBG("s3c_pm_safe_gpios()\n");

// Port A
//Ports  : GPA22 GPA21   GPA20 GPA19 GPA18 GPA17 GPA16     GPA15         GPA14      GPA13   GPA12  GPA11  GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1   GPA0
//Signal : nFCE  nRSTOUT nFRE  nFWE  ALE   CLE   AUDIO_ENn KP_MATRIX_CSn VIBMTR_ENn CHG_ENn L3MODE ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
//Binary : 1     1       1     1     1     1     0         1             0          0       0      1      1      1      1      1      1      1      1      1      1      1      1
	__raw_writel(__raw_readl(S3C2410_GPADAT) | ((1<<16) | (1<<14)), S3C2410_GPADAT);
	__raw_writel(0x7E8FFF, S3C2410_GPACON);

// Port B
// Ports  : GPB10       GPB9       GPB8         GPB7       GPB6      GPB5          GPB4    GPB3   GPB2             GPB1          GPB0
// Signal : CHG_PWR_GDn CHG_STAT2n 5V0_SMPS_ENn CHG_STAT1n PSU_PWRDN WLESS_5V0_ENn L3CLOCK L3DATA MZIO_SPI_DRN_PWM BUZZER_PWM_EN BL_EN_PWM
// Setting: IN          IN         OUT          IN         OUT       x           	 OUT     OUT    x              	 OUT           OUT 
// Binary : 00          00         01           00         01        xx            01      01     xx               01            01  
// PU_OFF : 0           0          1            0          1         1             1       1      1                1             1
// DATA   : 0           0          0            0          0         1             0       0      0                0             0 
	__raw_writel(0x020, 	S3C2410_GPBDAT);
	__raw_writel(0x11555, S3C2410_GPBCON);
	__raw_writel(0x17F, 	S3C2410_GPBUP);

// Port C
// Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9      GPC8      GPC7      GPC6        GPC5    GPC4    GPC3      GPC2      GPC1     GPC0
// Signal : VD7   VD6   VD5   VD4   VD3   VD2   5V_CR_ENn 5V_MZ_ENn BT_RESETn WIFI_RESETn WIFI_CS WIFI_EN LCD_VSYNC LCD_HYSNC LCD_PCLK Wless_BT_EN
// Setting: OUT   OUT   OUT   OUT   OUT   OUT   OUT       OUT       IN        IN          OUT     OUT     OUT       OUT       OUT      OUT
// Binary : 01    01    01    01    01    01    01        01        00        00          01      01      01        01        01       01
// PU_OFF : 1     1     1     1     1     1     1         1         1         1           1       1       1         1         1        1
// DATA   : 0     0     0     0     0     0     1         1         0         0           0       0       0         0         0        0
	__raw_writel(0x0300, 			S3C2410_GPCDAT);
	__raw_writel(0x55550555, 	S3C2410_GPCCON);
	__raw_writel(0xFFFF, 			S3C2410_GPCUP);

// Port D
// Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9     GPD8         GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1         GPD0
// Signal : VD23  VD22  VD21  VD20  VD19  VD18  RS232_EN MZIO_IrDAENn VD15 VD14 VD13 VD12 VD11 VD10 MZIO_MOD_PWR MZIO_RESET
// Setting: OUT   OUT   OUT   OUT   OUT   OUT   OUT      OUT          OUT  OUT  OUT  OUT  OUT  OUT  OUT          OUT
// Binary : 01    01    01    01    01    01    01       01           01   01   01   01   01   01   01           01
// PU_OFF : 1     1     1     1     1     1     1        1            1    1    1    1    1    1    1            1
// DATA   : 0     0     0     0     0     0     0        1            0    0    0    0    0    0    0            0
	__raw_writel(0x0100, 			S3C2410_GPDDAT);
	__raw_writel(0x55555555, 	S3C2410_GPDCON);
	__raw_writel(0xFFFF, 			S3C2410_GPDUP);

// Port E
// Ports  : GPE15  GPE14  GPE13      GPE12       GPE11       GPE10   GPE9    GPE8    GPE7    GPE6  GPE5  GPE4   GPE3   GPE2  GPE1    GPE0    
// Signal : IICSDA IICSCL MZ_SPI_CLK MZ_SPI_MOSI MZ_SPI_MISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO I2SSDI CDCLK I2SSCLK I2SLRCK
// Setting: IN     IN     OUT        OUT         IN          OUT     OUT     OUT     OUT     OUT   OUT   OUT    IN     OUT   OUT     OUT
// Binary : 00     00     01         01          00          01      01      01      01      01    01    01     00     01    01      01
// PU_OFF : 1      1      1          1           1           1       1       1       1       1     1     1      1      1     1       1 
// DATA   : 1      1      0          0           0           0       0       0       0       0     0     0      0      0     0       0
	__raw_writel(0xC000, 			S3C2410_GPEDAT);
	__raw_writel(0x5000115, 	S3C2410_GPECON);	// SV: Setting SD lines as input because we are keeping the card powered!
//	__raw_writel(0x05155515, 	S3C2410_GPECON);
	__raw_writel(0xFFFF, 			S3C2410_GPEUP);

// Port F
// Ports  : GPF7          GPF6            GPF5       GPF4     GPF3           GPF2           GPF1         GPF0
// Signal : MZ_RDY_IREQ_N KP_IREQN_WAKEUP WIFI_IREQn BT_IREQn KP_SideButtonR KP_SideButtonL KP_BLIGHTKEY KP_POWERKEY
// Setting: x         		IN              x      	 	 x				IN             IN             IN           EINT0
// Binary : xx            00              xx         xx       00             00             00           10
// PU_OFF : 1             1               x          x        1              1              1            1
// DATA   : 0             0               0          0        0              0              0            0
	__raw_writel(0xC000, 	S3C2410_GPFDAT);
	__raw_writel(0x0002,	S3C2410_GPFCON);
	__raw_writel(0xFF, 		S3C2410_GPFUP);

// Port G
// ** WARNING ** GPG[15:13] must be inputs for NAND mode
// Ports  : GPG15 GPG14 GPG13 GPG12   GPG11          GPG10   GPG9    GPG8   GPG7     GPG6      GPG5      GPG4   GPG3          GPG2      GPG1   GPG0    
// Signal : x     x     x     BATT_SW MZ_SPI_DRN_PWM BT_CTSn BT_RTSn SD_CDn WIFI_CLK WIFI_MOSI WIFI_MISO LCD_ON CRADLE_WAKEUP MZ_SPI_SS SD_ENn CRADLE_HOTSYNCINT
// Setting: IN    IN    IN    IN	    IN             IN      OUT     IN     OUT      OUT       OUT       OUT    EINT11        OUT       OUT	   EINT8   
// Binary : 00    00    00    00      00             00      01      00     01       01        01        01     10            01        01     10
// PU_OFF : 1     1     1     1       1              1       1       1      1        1         1         1      1             1         1      1
// DATA   : 0     0     0     0       0              0       0       0      0        0         0         0      0             0         1      0
__raw_writel(0x0000, 			S3C2410_GPGDAT);	// SV: Keep SD card powered!
//	__raw_writel(0x0002, 			S3C2410_GPGDAT);
	__raw_writel(0x00045596, 	S3C2410_GPGCON);
	__raw_writel(0xFFFF, 			S3C2410_GPGUP);

// Port H
// Ports  : GPH10       GPH9       GPH8  GPH7 GPH6 GPH5    GPH4    GPH3 GPH2 GPH1 GPH0 
// Signal : USB_HOST_EN 3V3EXT_ENn SD_WP RXD2 TXD2 BT_RXD1 BT_TXD1 RXD0 TXD0 RTS0 CTS0
// Setting: OUT         OUT        IN    IN   OUT  IN      OUT     IN   OUT  OUT  IN
// Binary : 01          01         00    00   01   00      01      00   01   01   00
// PU_OFF : 1           1          1     1    1    1       1       1    1    1    1
// DATA   : 1           1          0     0    0    0       0       0    0    0    0
// Note: USB_HOST_EN is high as a USB electrical disconnect
	__raw_writel(0x0600, 		S3C2410_GPHDAT);
	__raw_writel(0x14A114, 	S3C2410_GPHCON);	// SV: Keep the debug UART alive!
//	__raw_writel(0x141114, 	S3C2410_GPHCON);
	__raw_writel(0x7FF,			S3C2410_GPHUP);
	
// Port J
// Ports  : GPJ12   GPJ11       GPJ10	   GPJ9      GPJ8     GPJ7      GPJ6      GPJ5      GPJ4      GPJ3      GPJ2      GPJ1      GPJ0
// Signal : CAM_RST CAM_CLK_OUT CAM_HREF CAM_VSYNC CAM_PCLK CAM_DATA7 CAM_DATA6 CAM_DATA5 CAM_DATA4 CAM_DATA3 CAM_DATA2 CAM_DATA1 CAM_DATA0
// Setting: OUT     OUT         OUT      OUT       OUT      OUT       OUT       OUT       OUT       OUT       OUT       OUT       OUT
// Binary : 01      01          01       01        01       01        01        01        01        01        01        01        01
// PU_OFF : 1       1           1        1         1        1         1         1         1         1         1         1         1
// DATA   : 0       0           0        0         0        0         0         0         0         0         0         0         0
	__raw_writel(0x0000, 		S3C2440_GPJDAT);
	__raw_writel(0x1555555, S3C2440_GPJCON);
	__raw_writel(0x1FFF,		S3C2440_GPJUP);
}
Beispiel #23
0
static int s3c_pm_enter(suspend_state_t state)
{
#ifndef USE_DMA_ALLOC
	static unsigned long regs_save[16];
#endif /* !USE_DMA_ALLOC */
	unsigned int tmp,audiodomain_On;

	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/
		s3c_irqwake_intmask = 0xFFFD; // rtc_alarm

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

#ifndef USE_DMA_ALLOC
	s3c_sleep_save_phys = virt_to_phys(regs_save);
#else
	__raw_writel(phy_regs_save, S5P_INFORM2);
#endif /* !USE_DMA_ALLOC */

	/* set flag for sleep mode idle2 flag is also reserved */
	__raw_writel(SLEEP_MODE, S5P_INFORM1);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	s3c_config_sleep_gpio();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
			s3c_irqwake_intmask, s3c_irqwake_eintmask);

	/*Set EINT as wake up source*/
#if defined(CONFIG_OPTICAL_GP2A)
	if(gp2a_get_proximity_enable())
	{
		s3c_pm_set_eint(2, 0x4); // Proximity
	}
#endif
	s3c_pm_set_eint( 6, 0x4); // det_3.5
	s3c_pm_set_eint( 7, 0x2); // pmic
	s3c_pm_set_eint(11, 0x2); // onedram
	s3c_pm_set_eint(20, 0x3); // wifi
	s3c_pm_set_eint(21, 0x4); // bt
	s3c_pm_set_eint(22, 0x2); // power key
	s3c_pm_set_eint(23, 0x2);   // microusb
	s3c_pm_set_eint(25, 0x4); // volume down
	s3c_pm_set_eint(26, 0x4); // volume up
	s3c_pm_set_eint(28, 0x4);   // T_FLASH_DETECT
	s3c_pm_set_eint(29, 0x4);   // ok key
   	if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
	{
		s3c_pm_set_eint(30, 0x4); //sendend
	}
	else
	{
		s3c_pm_clear_eint(30);
	}

	//s3c_pm_arch_prepare_irqs();
	

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); //0xFFDD:key, RTC_ALARM	
	

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	__raw_writel(tmp, S5P_WAKEUP_STAT);

	//s3c_config_sleep_gpio();

	// Enable PS_HOLD pin to avoid reset failure */
	__raw_writel((0x5 << 12 | 0x1<<9 | 0x1<<8 | 0x1<<0),S5P_PSHOLD_CONTROL);


	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	s3c_cpu_save(regs_save);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();
	

	/* restore the system state */

	s3c_pm_restore_core();

	/*Reset the uart registers*/
	__raw_writel(0x0, S3C24XX_VA_UART3+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART2+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART1+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART0+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTP);

	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();

	tmp = readl(S5P_NORMAL_CFG);
	if(!(tmp & S5PC110_POWER_DOMAIN_AUDIO)) {
		tmp = tmp | S5PC110_POWER_DOMAIN_AUDIO;
		writel(tmp , S5P_NORMAL_CFG);
		audiodomain_On = 1;
	} else {
		audiodomain_On = 0;
	}

	/* enable gpio, uart, mmc */
	tmp = __raw_readl(S5P_OTHERS);
	tmp |= (1<<31) | (1<<30) | (1<<28) | (1<<29);
	__raw_writel(tmp, S5P_OTHERS);

	tmp = readl(S5P_NORMAL_CFG);
	if (audiodomain_On) {
		tmp = tmp & ~S5PC110_POWER_DOMAIN_AUDIO;
		writel(tmp , S5P_NORMAL_CFG);
	}

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	//printk("\nS5P_WAKEUP_STAT=%x\n",tmp);
	__raw_writel(tmp, S5P_WAKEUP_STAT);

	printk("wakeup source is 0x%x  \n", tmp);
	printk(" EXT_INT_0_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(0)));
	printk(" EXT_INT_1_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(1)));
	printk(" EXT_INT_2_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(2)));
	printk(" EXT_INT_3_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(3)));

	s3c_pm_clear_eint(21);
//	s3c_pm_clear_eint(22); // to be cleared later

	/* check what irq (if any) restored the system */
	s3c_pm_debug_init();

	s3c_pm_arch_show_resume_irqs();



#if defined(CONFIG_MACH_S5PC110_P1)
	// Set wakeup stat
	s3c_pm_set_wakeup_stat();
#endif // CONFIG_MACH_S5PC110_P1

	//printk("Int pending register before =%d\n",readl(S5PV210_EINTPEND(eint_pend_reg(22))));

	//printk("Int pending register after =%d\n",readl(S5PV210_EINTPEND(eint_pend_reg(22))));

	//S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
	//printk("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	//s3c_pm_debug_smdkled(1 << 1, 0);


	s3c_pm_check_restore();

	//mdelay(500);

	/* ok, let's return from sleep */
	printk(KERN_ERR "\n%s:%d\n", __func__, __LINE__);

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
Beispiel #24
0
static int s3c_pm_enter(suspend_state_t state)
{
	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	if (pm_check_eint_pend) {
		u32 pending_eint = pm_check_eint_pend();
		if (pending_eint) {
			pr_warn("%s: Aborting sleep, EINT PENDING(0x%08x)\n",
					__func__, pending_eint);
			return -EBUSY;
		}
	}

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_saved_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

#ifdef CONFIG_FAST_BOOT
	if (fake_shut_down) {
		/* Masking external wake up source
		 * only enable  power key, FUEL ALERT, AP/IF PMIC IRQ */
		__raw_writel(0xff77df7f, S5P_EINT_WAKEUP_MASK);
		/* disable all system int */
		__raw_writel(0xffffffff, S5P_WAKEUP_MASK);
	}
#endif

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	printk(KERN_ALERT "PM: SLEEP\n");

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	printk(KERN_ALERT "ARM_COREx_STATUS CORE1[0x%08x], CORE2[0x%08x], CORE3[0x%08x]\n",
			__raw_readl(S5P_VA_PMU + 0x2084),
			__raw_readl(S5P_VA_PMU + 0x2104),
			__raw_readl(S5P_VA_PMU + 0x2184));

	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();

#ifdef CONFIG_FAST_BOOT
	fake_shut_down = false;
#endif

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();
	s3c_pm_restored_gpios();

	s3c_pm_debug_init();

	/* restore the system state */

	if (pm_cpu_restore)
		pm_cpu_restore();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
#ifdef CONFIG_SLP_WAKEUP_COUNT
	wakeup_state = 1;
	wakeup_counter = wakeup_counter + 1;
#endif
	return 0;
}
Beispiel #25
0
*/

static int s3c_pm_enter(suspend_state_t state)
{
	int tmp;
	static unsigned long regs_save[16];

	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

//Apollo +
  s5p_pad_pdn_control();
  s3c_irqwake_intmask = 0xFFDF; // key 
//Apollo -

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/
//printk("s3c_irqwake_intmask  = 0x%08x, s3c_irqwake_intallow  = 0x%08x+++++++\n", s3c_irqwake_intmask, s3c_irqwake_intallow);
//printk("s3c_irqwake_eintmask = 0x%08x, s3c_irqwake_eintallow = 0x%08x+++++++\n", s3c_irqwake_eintmask, s3c_irqwake_eintallow);
	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

	s3c_sleep_save_phys = virt_to_phys(regs_save);

//Apollo +
	/* set flag for sleep mode idle2 flag is also reserved */
  #define SLEEP_MODE 0
  #define IDLE2_MODE 1
	__raw_writel(SLEEP_MODE, S5P_INFORM1);
//Apollo -

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

//Apollo +
  s3c_config_sleep_gpio();  //ÅäÖÃÐÝÃßʱ¸÷io״̬
//Apollo -

	/* set the irq configuration for wake */
	s3c_pm_configure_extint(); 
  
	//printk(KERN_INFO"sleep: irq wakeup masks: %08lx,%08lx\n", s3c_irqwake_intmask, s3c_irqwake_eintmask);
  s3c_irqwake_intmask = 0xFFDF;
	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* clear wakeup_stat register for next wakeup reason */
	__raw_writel(__raw_readl(S5P_WAKEUP_STAT), S5P_WAKEUP_STAT);

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	pmstats->sleep_count++;
	pmstats->sleep_freq = __raw_readl(S5P_CLK_DIV0);
	s3c_cpu_save(regs_save);
	pmstats->wake_count++;
	pmstats->wake_freq = __raw_readl(S5P_CLK_DIV0);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();
	tmp = readl(S5P_WAKEUP_STAT);
	fiq_glue_resume();
	local_fiq_enable();

	s3c_pm_restore_core();


	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();
	s5pv210_restore_eint_group();

	s3c_pm_debug_init();

        /* restore the system state */

	if (pm_cpu_restore)
		pm_cpu_restore();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
//	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
Beispiel #26
0
static int s3c_pm_enter(suspend_state_t state)
{
	static unsigned long regs_save[16];
	unsigned int gpio;
	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

	s3c_sleep_save_phys = virt_to_phys(regs_save);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */


#if 0
	/* control power of moviNAND at PM and add 700ms delay for stabilization of moviNAND. */
    gpio = readl(S5PV210_GPJ2DAT);
    writel(gpio & (~0x80), S5PV210_GPJ2DAT);
    mdelay(700);
#endif 

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	config_sleep_gpio();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* clear wakeup_stat register for next wakeup reason */
	__raw_writel(__raw_readl(S5P_WAKEUP_STAT), S5P_WAKEUP_STAT);

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	pmstats->sleep_count++;
	pmstats->sleep_freq = __raw_readl(S5P_CLK_DIV0);
	s3c_cpu_save(regs_save);
	pmstats->wake_count++;
	pmstats->wake_freq = __raw_readl(S5P_CLK_DIV0);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();

	fiq_glue_resume();
	local_fiq_enable();

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();
	s5pv210_restore_eint_group();

	s3c_pm_debug_init();

        /* restore the system state */

	if (pm_cpu_restore)
		pm_cpu_restore();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
Beispiel #27
0
static int s3c_pm_enter(suspend_state_t state)
{
	int ret;
	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	printk("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!of_have_populated_dt() &&
	    !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* save all necessary core registers not covered by the drivers */

	if (!of_have_populated_dt()) {
		samsung_pm_save_gpios();
		samsung_pm_saved_gpios();
	}

	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();
	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

#ifdef CONFIG_RTC_TICK_SLEEP_AGING_TEST
	if (rtc_tick_wakeup_enable)
		s3c_rtc_tick_control(1);
#endif

	/* this will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	ret = cpu_suspend(0, pm_cpu_sleep);

#ifdef CONFIG_RTC_TICK_SLEEP_AGING_TEST
	if (rtc_tick_wakeup_enable)
		s3c_rtc_tick_control(0);
#endif

	if (ret)
		return ret;

	/* restore the system state */

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();

	if (!of_have_populated_dt()) {
		samsung_pm_restore_gpios();
		s3c_pm_restored_gpios();
	}

	s3c_pm_debug_init();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
// intr_mode 0x2=>falling edge, 0x3=>rising dege, 0x4=>Both edge
static void s3c_pm_set_eint(unsigned int irq, unsigned int intr_mode)
{
	int offs = (irq);
	int shift;
	u32 ctrl, mask, tmp;

	shift = (offs & 0x7) * 4;
	if((0 <= offs) && (offs < 8)){
		tmp = readl(S5PV210_GPH0CON);
		tmp |= (0xf << shift);
		writel(tmp , S5PV210_GPH0CON);
		/*pull up disable*/
	}
	else if((8 <= offs) && (offs < 16)){
		tmp = readl(S5PV210_GPH1CON);
		tmp |= (0xf << shift);
		writel(tmp , S5PV210_GPH1CON);
	}
	else if((16 <= offs) && (offs < 24)){
		tmp = readl(S5PV210_GPH2CON);
		tmp |= (0xf << shift);
		writel(tmp , S5PV210_GPH2CON);
	}
	else if((24 <= offs) && (offs < 32)){
		tmp = readl(S5PV210_GPH3CON);
		tmp |= (0xf << shift);
		writel(tmp , S5PV210_GPH3CON);
	}
	else{
		printk(KERN_ERR "No such irq number %d", offs);
		return;
	}

#if 0 /* ktj disable */
	/*special handling for keypad eint*/
	if( (24 <= irq) && (irq <= 27))
	{// disable the pull up
		tmp = readl(S5PV210_GPH3PUD);
		tmp &= ~(0x3 << ((offs & 0x7) * 2));	
		writel(tmp, S5PV210_GPH3PUD);
		S3C_PMDBG("S5PV210_GPH3PUD = %x\n",readl(S5PV210_GPH3PUD));
	}
#endif
	
	/*Set irq type*/
	mask = 0x7 << shift;
	ctrl = readl(S5PV210_EINTCON(eint_conf_reg_x(irq)));
	ctrl &= ~mask;
	ctrl |= intr_mode << shift;

	writel(ctrl, S5PV210_EINTCON(eint_conf_reg_x(irq)));
	/*clear mask*/
	mask = readl(S5PV210_EINTMASK(eint_mask_reg_x(irq)));
	mask &= ~(eint_irq_to_bit_x(irq));
	writel(mask, S5PV210_EINTMASK(eint_mask_reg_x(irq)));

	/*clear pending*/
	mask = readl(S5PV210_EINTPEND(eint_pend_reg_x(irq)));
	mask &= (eint_irq_to_bit_x(irq));
	writel(mask, S5PV210_EINTPEND(eint_pend_reg_x(irq)));
	
	/*Enable wake up mask*/
	tmp = readl(S5P_EINT_WAKEUP_MASK);
	tmp &= ~(1 << (irq));
	writel(tmp , S5P_EINT_WAKEUP_MASK);

	S3C_PMDBG("S5PV210_EINTCON = %x\n",readl(S5PV210_EINTCON(eint_conf_reg_x(irq))));
	S3C_PMDBG("S5PV210_EINTMASK = %x\n",readl(S5PV210_EINTMASK(eint_mask_reg_x(irq))));
	S3C_PMDBG("S5PV210_EINTPEND = %x\n",readl(S5PV210_EINTPEND(eint_pend_reg_x(irq))));
	
	return;
}
Beispiel #29
0
static int s3c_pm_enter(suspend_state_t state)
{
#ifndef USE_DMA_ALLOC
	static unsigned long regs_save[16];
#endif /* !USE_DMA_ALLOC */
	unsigned int tmp;

	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

#ifndef USE_DMA_ALLOC
	s3c_sleep_save_phys = virt_to_phys(regs_save);
#else
	__raw_writel(phy_regs_save, S5P_INFORM2);
#endif /* !USE_DMA_ALLOC */

	/* set flag for sleep mode idle2 flag is also reserved */
	__raw_writel(SLEEP_MODE, S5P_INFORM1);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
		s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	s3c_cpu_save(regs_save);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();

	/* restore the system state */

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();

	s3c_pm_debug_init();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}
Beispiel #30
0
static int s3c_pm_enter(suspend_state_t state)
{
#ifndef USE_DMA_ALLOC
	static unsigned long regs_save[16];
#endif /* !USE_DMA_ALLOC */
	unsigned int tmp,audiodomain_On;

	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/
		s3c_irqwake_intmask = 0xFFFD; // rtc_alarm

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* store the physical address of the register recovery block */

#ifndef USE_DMA_ALLOC
	s3c_sleep_save_phys = virt_to_phys(regs_save);
#else
	__raw_writel(phy_regs_save, S5P_INFORM2);
#endif /* !USE_DMA_ALLOC */

	/* set flag for sleep mode idle2 flag is also reserved */
	__raw_writel(SLEEP_MODE, S5P_INFORM1);

	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c_pm_save_gpios();
	s3c_pm_save_uarts();
	s3c_pm_save_core();

	s3c_config_sleep_gpio();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
			s3c_irqwake_intmask, s3c_irqwake_eintmask);

	/*Set EINT as wake up source*/
#if defined(CONFIG_OPTICAL_GP2A) || defined(CONFIG_S5PC110_DEMPSEY_BOARD)
	if(gp2a_get_proximity_enable())
	{
		s3c_pm_set_eint(2, 0x4); // Proximity
	}
#endif

#if defined(CONFIG_S5PC110_DEMPSEY_BOARD)
	s3c_pm_set_eint( 6, 0x4); // det_3.5
	s3c_pm_set_eint( 7, 0x2); // pmic
	s3c_pm_set_eint(11, 0x2); // onedram
	#if defined (CONFIG_CP_CHIPSET_STE) 
	s3c_pm_set_eint(12, 0x2);		//INT_RESOUT
	s3c_pm_set_eint(9, 0x2);		//INT_CP_PWR_RST
	#else
	s3c_pm_set_eint(15, 0x4);		//PHONE_ACTIVE
	#endif	
//	s3c_pm_set_eint(20, 0x3); // wifi
	s3c_pm_set_eint(21, 0x4); // bt
	s3c_pm_set_eint(22, 0x2); // power key
	s3c_pm_set_eint(23, 0x2);   // microusb

//	s3c_pm_set_eint(28, 0x4);   // T_FLASH_DETECT: NC
//	s3c_pm_set_eint(29, 0x4);   // GYRO_INT
   	if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
	{
	    s3c_pm_set_eint(30, 0x4); //sendend
	}
    else
    {
        s3c_pm_clear_eint(30);
    }
#elif defined (CONFIG_S5PC110_HAWK_BOARD)	
	/*Set EINT 22 as wake up source*/
	s3c_pm_set_eint(11, 0x2); // nINT_ONEDRAM_AP
#if defined(CONFIG_HAWK_VER_B1_REAL_ADDED_FEATURE) //NAGSM_Android_HQ_KERNEL_CLEE_20100908 : Setup Hawk Real Board Rev 0.1
	s3c_pm_set_eint(31, 0x2); // nPower
	s3c_pm_set_eint(24, 0x2); // Home key
#else
	s3c_pm_set_eint(22, 0x2); // nPower
#endif
#if defined (CONFIG_CP_CHIPSET_STE) 
	s3c_pm_set_eint(12, 0x2);		//INT_RESOUT
	s3c_pm_set_eint(9, 0x2);		//INT_CP_PWR_RST
#else
	s3c_pm_set_eint(15, 0x4);		//PHONE_ACTIVE
#endif
	s3c_pm_set_eint(21, 0x4);		// BT_HOST_WAKE
	s3c_pm_set_eint(7,	0x02);		//PMIC	
	s3c_pm_set_eint(6, 0x4);		//det_3.5

	s3c_pm_set_eint(28, 0x4);	// T_FLASH_DETECT
#elif defined (CONFIG_S5PC110_VIBRANTPLUS_BOARD)
	s3c_pm_set_eint( 6, 0x4); // det_3.5
	s3c_pm_set_eint( 7, 0x2); // pmic
	s3c_pm_set_eint(11, 0x2); // onedram
	#if defined (CONFIG_CP_CHIPSET_STE) 
	s3c_pm_set_eint(12, 0x2);		//INT_RESOUT
	s3c_pm_set_eint(9, 0x2);		//INT_CP_PWR_RST
	#else
	s3c_pm_set_eint(15, 0x4);		//PHONE_ACTIVE
	#endif
	s3c_pm_set_eint(20, 0x3); // wifi
	s3c_pm_set_eint(21, 0x4); // bt
	s3c_pm_set_eint(22, 0x2); // power key
	s3c_pm_set_eint(23, 0x2);   // microusb

	if((is_calling_or_playing & IS_VOICE_CALL_2G) || (is_calling_or_playing & IS_VOICE_CALL_3G) || (is_calling_or_playing & IS_DATA_CALL)){
		s3c_pm_set_eint(25, 0x4); //volume up
		s3c_pm_set_eint(26, 0x4); //volume down
	}
	
	s3c_pm_set_eint(28, 0x4);   // T_FLASH_DETECT
#else
	s3c_pm_set_eint( 6, 0x4); // det_3.5
	s3c_pm_set_eint( 7, 0x2); // pmic
	s3c_pm_set_eint(11, 0x2); // onedram
	#if defined (CONFIG_CP_CHIPSET_STE) 
	s3c_pm_set_eint(12, 0x2);		//INT_RESOUT
	s3c_pm_set_eint(9, 0x2);		//INT_CP_PWR_RST
	#else
	s3c_pm_set_eint(15, 0x4);		//PHONE_ACTIVE
	#endif
	s3c_pm_set_eint(20, 0x3); // wifi
	s3c_pm_set_eint(21, 0x4); // bt
	s3c_pm_set_eint(22, 0x2); // power key
	s3c_pm_set_eint(23, 0x2);   // microusb
	s3c_pm_set_eint(25, 0x4); // volume down
	s3c_pm_set_eint(26, 0x4); // volume up
	s3c_pm_set_eint(28, 0x4);   // T_FLASH_DETECT
/*
	s3c_pm_set_eint(29, 0x4);   // ok key

   	if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
	{
	    s3c_pm_set_eint(30, 0x4); //sendend
	}
    else
    {
        s3c_pm_clear_eint(30);
    }
*/

#endif

#if defined CONFIG_T959_VER_B0
	s3c_pm_set_eint(29, 0x4);
// [[junghyunseok edit for fuel_int interrupt control of fuel_gauge 20100504
#elif defined CONFIG_KEPLER_VER_B0
#elif defined(CONFIG_KEPLER_VER_B2) || defined(CONFIG_T959_VER_B5) || defined (CONFIG_S5PC110_VIBRANTPLUS_BOARD) || defined(CONFIG_S5PC110_DEMPSEY_BOARD)
	s3c_pm_set_eint(27, 0x2);
// ]]junghyunseok edit for fuel_int interrupt control of fuel_gauge 20100504
#else	
	//gpio key
	if(HWREV >= 0xB)
	{
		s3c_pm_set_eint(27, 0x4);
		s3c_pm_set_eint(29, 0x4);
	}
#endif


//[hdlnc_bp_ytkwon : 20100326
//	#ifdef CONFIG_KEPLER_AUDIO_A1026
#if defined(CONFIG_S5PC110_KEPLER_BOARD)
		if(HWREV!=0x08)
		{
    			if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
			{
				s3c_pm_set_eint(30, 0x4); //sendend
				s3c_pm_set_eint(18, 0x4); //sendend 2.5
			}
   			else
   			{
       			s3c_pm_clear_eint(30);
	   			s3c_pm_clear_eint(18);
   			}
		}

#elif defined(CONFIG_S5PC110_T959_BOARD)
		if(HWREV==0x0a ||HWREV==0x0c)
		{
   			if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
			{
				s3c_pm_set_eint(30, 0x4); //sendend
			}
			else
   			{
     			s3c_pm_clear_eint(30);
       		}
			
		}
		else
		{
   			if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
			{
				s3c_pm_set_eint(30, 0x4); //sendend
				s3c_pm_set_eint(18, 0x4); //sendend 2.5
			}
   			else
   			{
	   			s3c_pm_clear_eint(30);
       			s3c_pm_clear_eint(18);
  			}
		}
#else	//sidekick, hawk, vibrantplus

   			if(get_headset_status() & SEC_HEADSET_4_POLE_DEVICE)
			{
				s3c_pm_set_eint(30, 0x4); //sendend
				s3c_pm_set_eint(18, 0x4); //sendend 2.5
			}
   			else
   			{
	   			s3c_pm_clear_eint(30);
       				s3c_pm_clear_eint(18);
  			}

#endif
	
//]hdlnc_bp_ytkwon : 20100326
#if defined (CONFIG_S5PC110_HAWK_BOARD)
		
	if(gp2a_get_proximity_enable())
	{
#if defined(CONFIG_HAWK_VER_B1_REAL_ADDED_FEATURE) //NAGSM_Android_HQ_KERNEL_CLEE_20100928 : Setup Hawk Real Board Rev 0.1 Proximity sensor
	    s3c_pm_set_eint(10, 0x2);//proximity
#else
	    s3c_pm_set_eint(2, 0x4);//proximity
#endif
	}
	s3c_pm_set_eint(20, 0x3);//WiFi
	s3c_pm_set_eint(23, 0x2);//microusb

#endif



	//s3c_pm_arch_prepare_irqs();
	

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

//	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); //0xFFDD:key, RTC_ALARM	
	if((is_calling_or_playing & IS_VOICE_CALL_2G) || (is_calling_or_playing & IS_VOICE_CALL_3G) || (is_calling_or_playing & IS_DATA_CALL)){
			__raw_writel(0xFFDD, S5P_WAKEUP_MASK); //0xFFDD:key, RTC_ALARM	
	}else{
		__raw_writel(0xFFFD, S5P_WAKEUP_MASK); //0xFFDD:key, RTC_ALARM	
	}
	

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	__raw_writel(tmp, S5P_WAKEUP_STAT);

	//s3c_config_sleep_gpio();

	// Enable PS_HOLD pin to avoid reset failure */
        __raw_writel((0x5 << 12 | 0x1<<9 | 0x1<<8 | 0x1<<0),S5P_PSHOLD_CONTROL);


	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* s3c_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	s3c_cpu_save(regs_save);

	/* restore the cpu state using the kernel's cpu init code. */

	cpu_init();
	

	/* restore the system state */

	s3c_pm_restore_core();

	/*Reset the uart registers*/
	__raw_writel(0x0, S3C24XX_VA_UART3+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART3+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART2+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART2+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART1+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART1+S5P_UINTP);
	__raw_writel(0x0, S3C24XX_VA_UART0+S3C2410_UCON);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTM);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTSP);
	__raw_writel(0xf, S3C24XX_VA_UART0+S5P_UINTP);

	s3c_pm_restore_uarts();
	s3c_pm_restore_gpios();

	/* enable gpio, uart, mmc */
	tmp = __raw_readl(S5P_OTHERS);
	tmp |= (1<<31) | (1<<30) | (1<<28) | (1<<29);
	__raw_writel(tmp, S5P_OTHERS);

	/*clear for next wakeup*/
	tmp = __raw_readl(S5P_WAKEUP_STAT);
	//printk("\nS5P_WAKEUP_STAT=%x\n",tmp);
	__raw_writel(tmp, S5P_WAKEUP_STAT);

	printk("wakeup source is 0x%x  \n", tmp);
	printk(" EXT_INT_0_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(0)));
	printk(" EXT_INT_1_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(1)));
	printk(" EXT_INT_2_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(2)));
	printk(" EXT_INT_3_PEND       %x \n", __raw_readl(S5PV210_EINTPEND(3)));

#if defined(CONFIG_S5PC110_HAWK_BOARD)
	//	s3c_pm_clear_eint(21);
#else
	s3c_pm_clear_eint(21);
#endif

//	s3c_pm_clear_eint(22); // to be cleared later

	/* check what irq (if any) restored the system */
	s3c_pm_debug_init();

	s3c_pm_arch_show_resume_irqs();



#if defined(CONFIG_MACH_S5PC110_P1)
	// Set wakeup stat
	s3c_pm_set_wakeup_stat();
#endif // CONFIG_MACH_S5PC110_P1

	//printk("Int pending register before =%d\n",readl(S5PV210_EINTPEND(eint_pend_reg(22))));

	//printk("Int pending register after =%d\n",readl(S5PV210_EINTPEND(eint_pend_reg(22))));

	//S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
	//printk("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	//s3c_pm_debug_smdkled(1 << 1, 0);


	s3c_pm_check_restore();

	//mdelay(500);

	/* ok, let's return from sleep */
	printk(KERN_ERR "\n%s:%d\n", __func__, __LINE__);

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}