void uart3_wakeup(void)
{
unsigned int gpa0_tx_dat = 0;
//AP uart3 TX Set to Low
s3c_gpio_cfgpin(S5PV210_GPA1(3), S3C_GPIO_OUTPUT);
gpa0_tx_dat = __raw_readl(S5PV210_GPA1DAT);
gpa0_tx_dat &= ~(1 << 3);
__raw_writel(gpa0_tx_dat, S5PV210_GPA1DAT);
s3c_gpio_cfgpin(S5PV210_GPA1(3), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPA1(3), S3C_GPIO_PULL_NONE);
}
};
static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
{
.base = S5PV210_GPA0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PV210_GPA0(0),
.ngpio = S5PV210_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.base = S5PV210_GPA1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PV210_GPA1(0),
.ngpio = S5PV210_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.base = S5PV210_GPB_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PV210_GPB(0),
.ngpio = S5PV210_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S5PV210_GPC0_BASE,
.config = &gpio_cfg,
.chip = {
#if defined(CONFIG_SPI_CNTRLR_0)
static struct s3c_spi_pdata s3c_slv_pdata_0[] __initdata = {
[0] = { /* Slave-0 */
.cs_level = CS_FLOAT,
.cs_pin = S5PV210_GPB(1),
.cs_mode = S5PV210_GPB_OUTPUT(1),
.cs_set = s3c_cs_set,
.cs_config = s3c_cs_config,
.cs_suspend = s3c_cs_suspend,
.cs_resume = s3c_cs_resume,
},
#if 0
[1] = { /* Slave-1 */
.cs_level = CS_FLOAT,
.cs_pin = S5PV210_GPA1(1),
.cs_mode = S5PV210_GPA1_OUTPUT(1),
.cs_set = s3c_cs_set,
.cs_config = s3c_cs_config,
.cs_suspend = s3c_cs_suspend,
.cs_resume = s3c_cs_resume,
},
#endif
};
#endif
#if defined(CONFIG_SPI_CNTRLR_1)
static struct s3c_spi_pdata s3c_slv_pdata_1[] __initdata = {
[0] = { /* Slave-0 */
.cs_level = CS_FLOAT,
.cs_pin = S5PV210_GPB(5),
static void s5pv210_uart_init(struct uart_t * uart)
{
struct resource_t * res = (struct resource_t *)uart->priv;
struct s5pv210_uart_data_t * dat = (struct s5pv210_uart_data_t *)res->data;
switch(res->id)
{
case 0:
clk_enable("psys-pclk");
/* Configure GPA01, GPA00 for TXD0, RXD0 and pull up */
gpio_set_cfg(S5PV210_GPA0(1), 0x2);
gpio_set_cfg(S5PV210_GPA0(0), 0x2);
gpio_set_pull(S5PV210_GPA0(1), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA0(0), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
write32(dat->regbase + S5PV210_UMON, 0x00000000);
break;
case 1:
clk_enable("psys-pclk");
/* Configure GPA05, GPA04 for TXD1, RXD1 */
gpio_set_cfg(S5PV210_GPA0(5), 0x2);
gpio_set_cfg(S5PV210_GPA0(4), 0x2);
gpio_set_pull(S5PV210_GPA0(5), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA0(4), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
write32(dat->regbase + S5PV210_UMON, 0x00000000);
break;
case 2:
clk_enable("psys-pclk");
/* Configure GPA11, GPA10 for TXD2, RXD2 */
gpio_set_cfg(S5PV210_GPA1(1), 0x2);
gpio_set_cfg(S5PV210_GPA1(0), 0x2);
gpio_set_pull(S5PV210_GPA1(1), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA1(0), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
break;
case 3:
clk_enable("psys-pclk");
/* Configure GPA13, GPA12 for TXD3, RXD3 */
gpio_set_cfg(S5PV210_GPA1(3), 0x2);
gpio_set_cfg(S5PV210_GPA1(2), 0x2);
gpio_set_pull(S5PV210_GPA1(3), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA1(2), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
break;
default:
return;
}
s5pv210_uart_setup(uart, dat->baud, dat->data, dat->parity, dat->stop);
}
