static int sh_sci_spi_probe(struct platform_device *dev) { struct resource *r; struct spi_master *master; struct sh_sci_spi *sp; int ret; master = spi_alloc_master(&dev->dev, sizeof(struct sh_sci_spi)); if (master == NULL) { dev_err(&dev->dev, "failed to allocate spi master\n"); ret = -ENOMEM; goto err0; } sp = spi_master_get_devdata(master); platform_set_drvdata(dev, sp); sp->info = dev->dev.platform_data; sp->bitbang.master = spi_master_get(master); sp->bitbang.master->bus_num = sp->info->bus_num; sp->bitbang.master->num_chipselect = sp->info->num_chipselect; sp->bitbang.chipselect = sh_sci_spi_chipselect; sp->bitbang.txrx_word[SPI_MODE_0] = sh_sci_spi_txrx_mode0; sp->bitbang.txrx_word[SPI_MODE_1] = sh_sci_spi_txrx_mode1; sp->bitbang.txrx_word[SPI_MODE_2] = sh_sci_spi_txrx_mode2; sp->bitbang.txrx_word[SPI_MODE_3] = sh_sci_spi_txrx_mode3; r = platform_get_resource(dev, IORESOURCE_MEM, 0); if (r == NULL) { ret = -ENOENT; goto err1; } sp->membase = ioremap(r->start, r->end - r->start + 1); if (!sp->membase) { ret = -ENXIO; goto err1; } sp->val = ioread8(SCSPTR(sp)); setbits(sp, PIN_INIT, 1); ret = spi_bitbang_start(&sp->bitbang); if (!ret) return 0; setbits(sp, PIN_INIT, 0); iounmap(sp->membase); err1: spi_master_put(sp->bitbang.master); err0: return ret; }
static inline void setbits(struct sh_sci_spi *sp, int bits, int on) { if (on) sp->val |= bits; else sp->val &= ~bits; iowrite8(sp->val, SCSPTR(sp)); }
static inline void setbits(struct sh_sci_spi *sp, int bits, int on) { /* * We are the only user of SCSPTR so no locking is required. * Reading bit 2 and 0 in SCSPTR gives pin state as input. * Writing the same bits sets the output value. * This makes regular read-modify-write difficult so we * use sp->val to keep track of the latest register value. */ if (on) sp->val |= bits; else sp->val &= ~bits; iowrite8(sp->val, SCSPTR(sp)); }
static inline u32 getmiso(struct spi_device *dev) { struct sh_sci_spi *sp = spi_master_get_devdata(dev->master); return (ioread8(SCSPTR(sp)) & PIN_RXD) ? 1 : 0; }