/*
* @fn extern void OUTPUT_Initialize(buffer, len)
*
* @param buffer - seed name of the output file
* @param len - length of the seed name
* @returns None
* @brief Allocate, initialize, and return all output data structure
*
* <I>Special Notes:</I>
* Initialize the output structures.
* For each CPU in the system, allocate the output buffers.
* Initialize a module buffer and temp file to hold module information
* Initialize the read queues for each sample buffer
*
*/
extern OS_STATUS
OUTPUT_Initialize (
char *buffer,
unsigned long len
)
{
BUFFER_DESC unused;
int i;
OS_STATUS status = OS_SUCCESS;
flush = 0;
for (i = 0; i < GLOBAL_STATE_num_cpus(driver_state); i++) {
unused = output_Initialized_Buffers(&cpu_buf[i], 1);
if (!unused) {
SEP_PRINT_ERROR("OUTPUT_Initialize: Failed to allocate cpu output buffers\n");
OUTPUT_Destroy();
return OS_NO_MEM;
}
}
/*
* Just need one module buffer
*/
module_buf = output_Initialized_Buffers(module_buf, MODULE_BUFF_SIZE);
if (!module_buf) {
SEP_PRINT_ERROR("OUTPUT_Initialize: Failed to create module output buffers\n");
OUTPUT_Destroy();
return OS_NO_MEM;
}
return status;
}
/*!
* @fn VOID UTILITY_Configure_Chipset
*
* @brief Configures the chipset information
*
* @param none
*
* @return none
*
* <I>Special Notes:</I>
* <NONE>
*/
extern CS_DISPATCH
UTILITY_Configure_Chipset (
void
)
{
if (CHIPSET_CONFIG_gmch_chipset(pma)) {
cs_dispatch = &gmch_dispatch;
SEP_PRINT_DEBUG("UTLITY_Configure_Chipset: using GMCH dispatch table!\n");
}
else if (CHIPSET_CONFIG_mch_chipset(pma) || CHIPSET_CONFIG_ich_chipset(pma)) {
cs_dispatch = &chap_dispatch;
SEP_PRINT_DEBUG("UTLITY_Configure_Chipset: using CHAP dispatch table!\n");
}
else {
SEP_PRINT_ERROR("UTLITY_Configure_Chipset: unable to map chipset dispatch table!\n");
}
SEP_PRINT_DEBUG("UTLITY_Configure_Chipset: exiting with cs_dispatch=0x%p\n", cs_dispatch);
return cs_dispatch;
}
/*!
* @fn VOID UTILITY_Configure_CPU
*
* @brief Reads the CPU information from the hardware
*
* @param param dispatch_id - The id of the dispatch table.
*
* @return Pointer to the correct dispatch table for the CPU architecture
*
* <I>Special Notes:</I>
* <NONE>
*/
extern DISPATCH
UTILITY_Configure_CPU (
U32 dispatch_id
)
{
DISPATCH dispatch = NULL;
switch (dispatch_id) {
#if defined(DRV_IA32) || defined(DRV_EM64T)
case 1:
SEP_PRINT_DEBUG("Set up the Core(TM)2 processor dispatch table\n");
dispatch = &core2_dispatch;
break;
case 6:
SEP_PRINT_DEBUG("Set up the Silvermont dispatch table\n");
dispatch = &silvermont_dispatch;
break;
case 7:
SEP_PRINT_DEBUG("Set up the perfver4 HTON dispatch table such as Skylake\n");
dispatch = &perfver4_dispatch;
break;
case 8:
SEP_PRINT_DEBUG("Set up the perfver4 HTOFF dispatch table such as Skylake\n");
dispatch = &perfver4_dispatch_htoff_mode;
break;
case 700:
SEP_PRINT_DEBUG("Set up the Valleyview SA dispatch table\n");
dispatch = &valleyview_visa_dispatch;
break;
case 710:
case 800:
SEP_PRINT_DEBUG("Set up the Silvermont/Haswell Server Power dispatch table\n");
dispatch = &avoton_power_dispatch;
break;
case 2:
dispatch = &corei7_dispatch;
SEP_PRINT_DEBUG("Set up the Core i7(TM) processor dispatch table\n");
break;
case 3:
SEP_PRINT_DEBUG("Set up the Core i7(TM) dispatch table\n");
dispatch = &corei7_dispatch_htoff_mode;
break;
case 4:
dispatch = &corei7_dispatch_2;
SEP_PRINT_DEBUG("Set up the Sandybridge processor dispatch table\n");
break;
case 5:
SEP_PRINT_DEBUG("Set up the Sandybridge dispatch table\n");
dispatch = &corei7_dispatch_htoff_mode_2;
break;
case 9:
dispatch = &corei7_dispatch_nehalem;
SEP_PRINT_DEBUG("Set up the Nehalem, Westemere dispatch table\n");
break;
case 200:
SEP_PRINT_DEBUG("Set up the SNB iMC dispatch table\n");
dispatch = &snbunc_imc_dispatch;
break;
case 201:
SEP_PRINT_DEBUG("Set up the SNB Cbo dispatch table\n");
dispatch = &snbunc_cbo_dispatch;
break;
#if !defined (DRV_ANDROID)
case 100:
SEP_PRINT_DEBUG("Set up the Core i7 uncore dispatch table\n");
dispatch = &corei7_unc_dispatch;
break;
case 210:
SEP_PRINT_DEBUG("Set up the WSM-EX iMC dispatch table\n");
dispatch = &wsmexunc_imc_dispatch;
break;
case 211:
SEP_PRINT_DEBUG("Set up the WSM-EX QPI dispatch table\n");
dispatch = &wsmexunc_qpi_dispatch;
break;
case 212:
SEP_PRINT_DEBUG("Set up the WSM-EX WBOX dispatch table\n");
dispatch = &wsmexunc_wbox_dispatch;
break;
case 220:
SEP_PRINT_DEBUG("Set up the JKT IMC dispatch table\n");
dispatch = &jktunc_imc_dispatch;
break;
case 221:
SEP_PRINT_DEBUG("Set up the JKT QPILL dispatch table\n");
dispatch = &jktunc_qpill_dispatch;
break;
case 222:
SEP_PRINT_DEBUG("Set up the Jaketown UBOX dispatch table\n");
dispatch = &jaketown_ubox_dispatch;
break;
#endif
case 300:
SEP_PRINT_DEBUG("Set up the SNB Power dispatch table\n");
dispatch = &snb_power_dispatch;
break;
case 400:
SEP_PRINT_DEBUG("Set up the SNB Power dispatch table\n");
dispatch = &snbunc_gt_dispatch;
break;
case 500:
SEP_PRINT_DEBUG("Set up the Haswell UNC NCU dispatch table\n");
dispatch = &haswellunc_ncu_dispatch;
break;
#if !defined (DRV_ANDROID)
case 600:
SEP_PRINT_DEBUG("Set up the IVT UNC CBO dispatch table\n");
dispatch = &ivtunc_cbo_dispatch;
break;
case 610:
SEP_PRINT_DEBUG("Set up the IVT UNC IMC dispatch table\n");
dispatch = &ivtunc_imc_dispatch;
break;
case 620:
SEP_PRINT_DEBUG("Set up the Ivytown UNC PCU dispatch table\n");
dispatch = &ivytown_pcu_dispatch;
break;
case 630:
SEP_PRINT_DEBUG("Set up the Ivytown UNC PCU dispatch table\n");
dispatch = &ivytown_ha_dispatch;
break;
case 640:
SEP_PRINT_DEBUG("Set up the Ivytown QPI dispatch table\n");
dispatch = &ivytown_qpill_dispatch;
break;
case 650:
SEP_PRINT_DEBUG("Set up the Ivytown R3QPI dispatch table\n");
dispatch = &ivytown_r3qpi_dispatch;
break;
case 660:
SEP_PRINT_DEBUG("Set up the Ivytown UNC UBOX dispatch table\n");
dispatch = &ivytown_ubox_dispatch;
break;
case 670:
SEP_PRINT_DEBUG("Set up the Ivytown UNC R2PCIe dispatch table\n");
dispatch = &ivytown_r2pcie_dispatch;
break;
case 680:
SEP_PRINT_DEBUG("Set up the Ivytown UNC IRP dispatch table\n");
dispatch = &ivytown_irp_dispatch;
break;
#endif
case 720:
SEP_PRINT_DEBUG("Set up the Haswell Power dispatch table\n");
dispatch = &haswell_power_dispatch;
break;
#if !defined (DRV_ANDROID)
case 790:
SEP_PRINT_DEBUG("Set up the Haswell Server CBO dispatch table\n");
dispatch = &haswell_server_cbo_dispatch;
break;
case 791:
SEP_PRINT_DEBUG("Set up the Haswell Server PCU dispatch table\n");
dispatch = &haswell_server_pcu_dispatch;
break;
case 792:
SEP_PRINT_DEBUG("Set up the Haswell Server UBOX dispatch table\n");
dispatch = &haswell_server_ubox_dispatch;
break;
case 793:
SEP_PRINT_DEBUG("Set up the Haswell Server QPILL dispatch table\n");
dispatch = &haswell_server_qpill_dispatch;
break;
case 794:
SEP_PRINT_DEBUG("Set up the Haswell Server iMC dispatch table\n");
dispatch = &haswell_server_imc_dispatch;
break;
case 795:
SEP_PRINT_DEBUG("Set up the Haswell Server HA dispatch table\n");
dispatch = &haswell_server_ha_dispatch;
break;
case 796:
SEP_PRINT_DEBUG("Set up the Haswell Server R2PCIe dispatch table\n");
dispatch = &haswell_server_r2pcie_dispatch;
break;
case 797:
SEP_PRINT_DEBUG("Set up the Haswell Server R3QPI dispatch table\n");
dispatch = &haswell_server_r3qpi_dispatch;
break;
case 798:
SEP_PRINT_DEBUG("Set up the Haswell Server SBOX dispatch table\n");
dispatch = &haswell_server_sbox_dispatch;
break;
case 799:
SEP_PRINT_DEBUG("Set up the Haswell Server IRP dispatch table\n");
dispatch = &haswell_server_irp_dispatch;
break;
#endif
#endif
default:
dispatch = NULL;
SEP_PRINT_ERROR("Architecture not supported (dispatch_id=%d)\n", dispatch_id);
break;
}
return dispatch;
}
/*!
* @fn VOID UTILITY_Configure_CPU
*
* @brief Reads the CPU information from the hardware
*
* @param param dispatch_id - The id of the dispatch table.
*
* @return Pointer to the correct dispatch table for the CPU architecture
*
* <I>Special Notes:</I>
* <NONE>
*/
extern DISPATCH
UTILITY_Configure_CPU (
U32 dispatch_id
)
{
DISPATCH dispatch = NULL;
switch (dispatch_id) {
#if defined(DRV_IA32) && !defined(DRV_ATOM_ONLY)
case 0:
SEP_PRINT_DEBUG("Set up the Core(TM) processor dispatch table\n");
dispatch = &core_dispatch;
break;
#endif
#if defined(DRV_IA32) || defined(DRV_EM64T)
case 1:
SEP_PRINT_DEBUG("Set up the Core(TM)2 processor dispatch table\n");
dispatch = &core2_dispatch;
break;
case 6:
SEP_PRINT_DEBUG("Set up the Silvermont dispatch table\n");
dispatch = &silvermont_dispatch;
break;
#if !defined(DRV_ATOM_ONLY)
case 2:
dispatch = &corei7_dispatch;
SEP_PRINT_DEBUG("Set up the Core i7(TM) processor dispatch table\n");
break;
case 3:
SEP_PRINT_DEBUG("Set up the Core i7(TM) dispatch table\n");
dispatch = &corei7_dispatch_htoff_mode;
break;
case 4:
dispatch = &corei7_dispatch_2;
SEP_PRINT_DEBUG("Set up the Sandybridge processor dispatch table\n");
break;
case 5:
SEP_PRINT_DEBUG("Set up the Sandybridge dispatch table\n");
dispatch = &corei7_dispatch_htoff_mode_2;
break;
case 100:
SEP_PRINT_DEBUG("Set up the Core i7 uncore dispatch table\n");
dispatch = &corei7_unc_dispatch;
break;
case 200:
SEP_PRINT_DEBUG("Set up the SNB iMC dispatch table\n");
dispatch = &snbunc_imc_dispatch;
break;
case 201:
SEP_PRINT_DEBUG("Set up the SNB Cbo dispatch table\n");
dispatch = &snbunc_cbo_dispatch;
break;
case 210:
SEP_PRINT_DEBUG("Set up the WSM-EX iMC dispatch table\n");
dispatch = &wsmexunc_imc_dispatch;
break;
case 211:
SEP_PRINT_DEBUG("Set up the WSM-EX QPI dispatch table\n");
dispatch = &wsmexunc_qpi_dispatch;
break;
case 212:
SEP_PRINT_DEBUG("Set up the WSM-EX WBOX dispatch table\n");
dispatch = &wsmexunc_wbox_dispatch;
break;
case 220:
SEP_PRINT_DEBUG("Set up the JKT IMC dispatch table\n");
dispatch = &jktunc_imc_dispatch;
break;
case 221:
SEP_PRINT_DEBUG("Set up the JKT QPILL dispatch table\n");
dispatch = &jktunc_qpill_dispatch;
break;
case 222:
SEP_PRINT_DEBUG("Set up the Jaketown UBOX dispatch table\n");
dispatch = &jaketown_ubox_dispatch;
break;
case 500:
SEP_PRINT_DEBUG("Set up the Haswell UNC NCU dispatch table\n");
dispatch = &haswellunc_ncu_dispatch;
break;
case 600:
SEP_PRINT_DEBUG("Set up the IVT UNC CBO dispatch table\n");
dispatch = &ivtunc_cbo_dispatch;
break;
case 610:
SEP_PRINT_DEBUG("Set up the IVT UNC IMC dispatch table\n");
dispatch = &ivtunc_imc_dispatch;
break;
case 620:
SEP_PRINT("Set up the Ivytown UNC PCU dispatch table\n");
dispatch = &ivytown_pcu_dispatch;
break;
case 630:
SEP_PRINT("Set up the Ivytown UNC PCU dispatch table\n");
dispatch = &ivytown_ha_dispatch;
break;
case 640:
SEP_PRINT_DEBUG("Set up the Ivytown QPI dispatch table\n");
dispatch = &ivytown_qpill_dispatch;
break;
case 650:
SEP_PRINT_DEBUG("Set up the Ivytown R3QPI dispatch table\n");
dispatch = &ivytown_r3qpi_dispatch;
break;
case 660:
SEP_PRINT("Set up the Ivytown UNC UBOX dispatch table\n");
dispatch = &ivytown_ubox_dispatch;
break;
case 670:
SEP_PRINT("Set up the Ivytown UNC R2PCIe dispatch table\n");
dispatch = &ivytown_r2pcie_dispatch;
break;
#endif
#endif
#if defined(DRV_IA64)
case 4:
dispatch = &montecito_dispatch;
SEP_PRINT_DEBUG("Set up the Itanium(TM) Processor dispatch table\n");
break;
case 5:
dispatch = &poulson_dispatch;
SEP_PRINT_DEBUG("Set up the Itanium(TM) Processor dispatch table\n");
break;
#endif
default:
dispatch = NULL;
SEP_PRINT_ERROR("Architecture not supported (dispatch_id=%d)\n", dispatch_id);
break;
}
return dispatch;
}
/*!
* @fn int CPUMON_Install_Cpuhooks(VOID)
* @brief Assign the PMU interrupt to the driver
*
* @return zero if successful, non-zero error value if something failed
*
* Install the driver ebs handler onto the PMU interrupt. If perfmon is
* compiled in then we ask perfmon for the interrupt, otherwise we ask the
* kernel...
*
* <I>Special Notes:</I>
*
* @Note This routine is for Itanium(R)-based systems only!
*
* For IA32, the LBRs are not frozen when a PMU interrupt is taken.
* Since the LBRs capture information on every branch, for the LBR
* registers to be useful, we need to freeze them as quickly as
* possible after the interrupt. This means hooking the IDT directly
* to call a driver specific interrupt handler. That happens in the
* vtxsys.S file via samp_get_set_idt_entry. The real routine being
* called first upon PMU interrupt is t_ebs (in vtxsys.S) and that
* routine calls PMI_Interrupt_Handler()...
*
*/
extern void
CPUMON_Install_Cpuhooks (
void
)
{
int status = -1;
SEP_PRINT_DEBUG("CPUMON_Install_Cpuhooks: entered... pmv 0x%p \n", SYS_Read_PMV());
#if defined(PERFMON_V1) || defined(PERFMON_V2_ALT)
/*
* if Perfmon1 or Perfmon2_alt is set, we can use the perfmon.c
* interface to steal perfmon.c's interrupt handler for our use
* perfmon.c has already done register_percpu_irq()
*/
ebs_irq = SEP_PERFMON_IRQ;
desc.handler = &PMI_Interrupt_Handler;
status = CPUMON_INSTALL_INTERRUPT(&desc);
if (status) {
SEP_PRINT_ERROR("CPUMON_Install_Cpuhooks: CPUMON_INSTALL_INTERRUPT returned %d\n",status);
}
#elif !defined(PERFMON_V2)
if (pebs_irqaction) {
return status;
}
#ifdef SA_PERCPU_IRQ_SUPPORTED
ebs_irq = SEP_PERFMON_IRQ;
pebs_irqaction = (struct irqaction *) 1;
status = request_irq(SEP_PERFMON_IRQ,
PMI_Interrupt_Handler,
SA_INTERRUPT | SA_PERCPU_IRQ,
"SEP Sampling",
NULL);
#else
{
pebs_irqaction = kmalloc(sizeof (struct irqaction), GFP_ATOMIC);
if (pebs_irqaction) {
memset(pebs_irqaction, 0, sizeof (struct irqaction));
ebs_irq = SEP_PERFMON_IRQ;
pebs_irqaction->handler = (void *)PMI_Interrupt_Handler;
pebs_irqaction->flags = SA_INTERRUPT;
pebs_irqaction->name = SEP_DRIVER_NAME;
pebs_irqaction->dev_id = NULL;
register_percpu_irq(ebs_irq, pebs_irqaction);
status = 0;
}
else {
SEP_PRINT_WARNING("couldn't kmalloc pebs_irqaction (%d bytes)\n",
(int)sizeof(struct irqaction));
}
}
#endif
#endif
SEP_PRINT("IRQ vector 0x%x will be used for handling PMU interrupts\n", SEP_PERFMON_IRQ);
SEP_PRINT_DEBUG("CPUMON_Install_Cpuhooks: exit...... rc=0x%x pmv=0x%p \n",
status, SYS_Read_PMV());
return;
}
