//------------------------------------------------------------------------------
void
PrcmVoltEnableVp(
VoltageProcessor_e vp,
BOOL bEnable
)
{
switch (vp)
{
case kVoltageProcessor1:
if (bEnable != FALSE)
{
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_VPENABLE);
}
else
{
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_VPENABLE);
}
break;
case kVoltageProcessor2:
if (bEnable != FALSE)
{
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_VPENABLE);
}
else
{
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_VPENABLE);
}
break;
}
}
void
OMAP2420DMAContext::HWStartOutputDMA()
{
OMAP2420_DMA_REGS *pDMAReg;
DEBUGMSG(ZONE_FUNCTION, (L"+OMAP2420DMAContext::HWStartOutputDMA()\r\n"));
#ifdef PROFILE_MIXER
GetOutputDeviceContext(0)->StartMixerProfiler();
#endif
pDMAReg = m_pOutDMAReg;
// enable the channel
SETREG32(&pDMAReg->DMA4_CLNK_CTRL, DMA_CLNK_CTRL_ENABLE_LINK);
SETREG32(&pDMAReg->DMA4_CCR, DMA_CCR_ENABLE);
#if defined(DEBUG)
DumpDMA_LC(L"Start Output", pDMAReg);
CheckDMAStatus(pDMAReg, TRUE);
#endif
HWEnableOutputChannel(TRUE);
DEBUGMSG(ZONE_FUNCTION, (L"-OMAP2420DMAContext::HWStartOutputDMA()\r\n"));
}
void jz4755fb_change_clock(void )
{
unsigned int val = 0;
unsigned int reg;
/* Timing setting */
SETREG32(A_CPM_CLKGR, CLKGR_STOP_LCD);
SETREG32(A_CPM_CLKGR, CLKGR_STOP_TVE);
OUTREG32(A_CPM_CPPCR, CPPCR_CFG_FOR_TVE);
CLRREG32(A_CPM_LPCDR, LPCDR_LSCS);
SETREG32(A_CPM_LPCDR, LPCDR_LTCS);
// val = GetCurrentPLLClock(1) / GetCommonClock(CPM_HDIV);
// reg = (INREG32(A_CPM_CPCCR) & ~CPCCR_LDIV_MASK);
// OUTREG32(A_CPM_CPCCR, reg | ((val - 1) << (CPCCR_LDIV_BIT)));
/********* In TVE mode PCLK = 27MHz ***********/
val = CFG_CPU_SPEED_FOR_TVE / TV_SPEED_CLCK; // PLLCLK = 324
OUTREG32(A_CPM_LPCDR, val - 1);
SETREG32(A_CPM_LPCDR, LPCDR_LTCS); // REG_CPM_LPCDR |= CPM_LPCDR_LTCS;
SETREG32(A_CPM_CPCCR, CPCCR_CHANGE_EN); // REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_LCD);
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TVE); //Ò»¶¨Òª¿ªÆô°¡
udelay(1000);
}
////////////////////////////////////////////////////
// 功能: 延迟N个豪秒
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void dma_init(unsigned int channel, char mode)
{
unsigned int group, data;
#ifdef KPRINTF_DEF
kprintf("dma init channle = %d\n",channel);
#endif
group = channel / HALF_DMA_NUM;
SETREG32(A_DMA_DMAC(group), (DMAC_DMA_EN | DMAC_FAST_AIC) );
SETREG32(A_DMA_DCKE(group), (1 << (channel - group * HALF_DMA_NUM)) );
OUTREG32(A_DMA_DCS(channel), DCS_NDES );
if (mode)
{
data = DCM_SAI | DCM_SP_32BIT | DCM_DP_16BIT | DCM_TSZ_16BYTE | DCM_RDIL_IGN | DCM_TRANS_INTR_EN;
OUTREG32(A_DMA_DCM(channel), data);
OUTREG32(A_DMA_DRT(channel), DRT_AIC_TX);
}
else
{
data = DCM_DAI | DCM_SP_16BIT | DCM_DP_32BIT | DCM_TSZ_16BYTE | DCM_RDIL_IGN;
OUTREG32(A_DMA_DCM(channel), data);
OUTREG32(A_DMA_DRT(channel), DRT_AIC_RX);
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//Note:
// frequence=[(OSC_CLOCK / 4) / 0xffff+1,((OSC_CLOCK / 4) / 100)]
// IF OSC_CLOCK=12,000,000 THEN frequence=[190,120000]
// mode: bit0---InitLevel 0--LowLevel 1--HightLevel
// bit1---ShutDown 0--Gracefull 1--Abrutp
void pwm_init(unsigned int chn, unsigned int frequence, unsigned int mode)
{
unsigned int full_counter;
if ((frequence < ((OSC_CLOCK) / 0xffff) + 1) || (frequence > (OSC_CLOCK/100)))
{
printf("The frequence of pwm shoud be in [%d,%d]\n",
(((OSC_CLOCK) / 0xffff)+1), ((OSC_CLOCK/100)) );
return;
}
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
OUTREG16(A_TCU_TCSR(chn), TCU_CLK_EXTAL);
full_counter = (OSC_CLOCK) / frequence;
OUTREG16(A_TCU_TDFR(chn), full_counter);
OUTREG16(A_TCU_TDHR(chn), 0x0000);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
SETREG32((A_TCU_TCSR(chn)), (mode & 0x3) << 8);
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
}
BOOL InitClockController()
{
OALMSG(OAL_ETHER&&OAL_FUNC, (L"+USBFN:: Initialize USB Clock Mgr\r\n"));
{
OMAP2420_PRCM_REGS * pPRCMRegs = OALPAtoUA(OMAP2420_PRCM_REGS_PA);
#if 0
// Disable the USB Interface clock
CLRREG32(&pPRCMRegs->ulCM_ICLKEN2_CORE, 0x00000001); // Clear EN_USB
#endif
// Configure the USB Interface Clock Speed
CLRREG32(&pPRCMRegs->ulCM_CLKSEL1_CORE, 0x0E000000); // Clear clk = L3_CLK/1 (boot mode only)
SETREG32(&pPRCMRegs->ulCM_CLKSEL1_CORE, 0x08000000); // Set clk = L3_CLK/3
#if 0
// Ensure that the USB Interface clock remains active when the MPU enters Idle Mode.
CLRREG32(&pPRCMRegs->ulCM_AUTOIDLE2_CORE, 0x00000001); // Clear AUTO_USB
// Enable the USB Interface clock
SETREG32(&pPRCMRegs->ulCM_ICLKEN2_CORE, 0x00000001); // Set EN_USB
// Enable the USB Functional clock
SETREG32(&pPRCMRegs->ulCM_FCLKEN2_CORE, 0x00000001); // Set EN_USB
// Enable USB Wake-Up
SETREG32(&pPRCMRegs->ulPM_WKEN2_CORE, 0x00000001); // Set EN_USB
#endif
}
OALMSG(OAL_ETHER&&OAL_FUNC, (L"-USBFN:: Initialize USB Clock Mgr\r\n"));
return TRUE;
}
int efuseWrite(UINT32 group, UINT32* pBuf, UINT32 num)
{
int i;
SETREG32(EFUSEC_CFG, EFUSEC_APB);
SETBITVALUE32(EFUSEC_COUNT, EFUSE_COUNT_MASK, EFUSE_COUNT_CFG);
SETBITVALUE32(EFUSEC_PGM_COUNT, EFUSE_PGM_COUNT_MASK, PGM_COUNT_CFG);
SETREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PRE_PG_FIN, EFUSEC_PRE_PG_FIN))
{
return ERROR;
}
for (i = 0; i < num; i++)
{
SETBITVALUE32(EFUSE_GROUP, EFUSE_GP_MASK, group + i);
OUTREG32(EFUSE_PG_VALUE, *(pBuf + i));
SETREG32(EFUSEC_CFG, EFUSEC_PG_EN);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PG_STATUS, EFUSEC_PG_STATUS))
{
return ERROR;
}
}
CLRREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
return OK;
}
// Function: configure_dss
// This function configures the display sub-system
void configure_dss( unsigned int framebuffer ){
// Configure the clock source
OUTREG32(0x48045040, 1<<8 | 0<<9 | 0<<10 | 0<<12 | 0<<17);//DSI_CTRL
udelay(10000);
// Configure interconnect parameters
// OUTREG32(0x48041010, 1<<0 | 1<<3 | 1<<12 );
OUTREG32(0x48041010, 0x00002015);
udelay(10000);
// Disable any interrupts
OUTREG32(0x4804501c,0);//DSI_IRQENABLE
udelay(10000);
// Over-ride default LCD config
//OUTREG32(DISPC_CONFIG,BSP_LCD_CONFIG);
//OUTREG32(0x48041620, );//DISPC_CONFIG2 in omap4
// Configure graphic window
OUTREG32(0x48041080,framebuffer);//DISPC_GFX_BA_0
// Configure the position of graphic window
OUTREG32(0x48041088,BSP_GFX_POS(g_LogoX,g_LogoY));//DISPC_GFX_POSITION
// Configure the size of graphic window
OUTREG32(0x4804108c,BSP_GFX_SIZE(g_LogoW,g_LogoH));//DISPC_GFX_SIZE
// GW Enabled, RGB24 packed, little Endian
//OUTREG32(0x480410a0,LOGO_GFX_ATTRIBUTES);//DISPC_GFX_ATTRIBUTES
// OUTREG32(0x480410a0,1<<0 | 9<<1);//DISPC_GFX_ATTRIBUTES no crash
// OUTREG32(0x480410a0,1<<30 | 0x3<<26 | 1<<25 | 1<<14 | 1<<0 | 9<<1);//DISPC_GFX_ATTRIBUTES
// OUTREG32(0x480410a0,1<<30 | 0x3<<26 | 1<<25 | 1<<7 | 1<<0 | 9<<1);//DISPC_GFX_ATTRIBUTES
OUTREG32(0x480410a0,1<<30);
udelay(10000);
SETREG32(0x480410a0,0x3<<26);
udelay(10000);
SETREG32(0x480410a0,1<<25);
udelay(10000);
SETREG32(0x480410a0,1<<14);
udelay(10000);
SETREG32(0x480410a0,1<<7);
udelay(10000);
SETREG32(0x480410a0,1<<0 | 6<<1);//DISPC_GFX_ATTRIBUTES
udelay(10000);
//0000 0000 0000 0000 0000 0000 0001 0011
//OUTREG32(0x480410a0,0x42000099);//DISPC_GFX_ATTRIBUTES
OUTREG32(0x480410a4,DISPC_GFX_FIFO_THRESHOLD_R(192,252));//DISPC_GFX_FIFO_THRESHOLD
// OUTREG32(0x480410a4,0x04ff0480);//DISPC_GFX_FIFO_THRESHOLD
//!!! should be modify??
OUTREG32(0x480410ac,1);//DISPC_GFX_ROW_INC
OUTREG32(0x480410b0,1);//DISPC_GFX_PIXEL_INC
OUTREG32(0x480410b4,0);//DISPC_GFX_WINDOW_SKIP
// Configure the LCD
LcdPdd_LCD_Initialize();
}
// turn off TVE, turn off DACn...
int jz4755tve_close(void)
{
CLRREG32(A_TV_TVECR, TV_TVECR_DAPD);
#if (TV_VIDEO_OUT_MODE == TV_OUT_MODE_3DIV)
SETREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2| TV_TVECR_DAPD3);
#else
SETREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2);
#endif
SETREG32(A_TV_TVECR, TV_TVECR_SWRST);
}
void dma_nowait_cpyinit()
{
CLRREG32(A_CPM_CLKGR, ( 1 << 12 ));
SETREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6),DMAC_DMA_EN);
OUTREG32(A_DMA_DCKE(DMA_CPY_CHANNEL / 6),(1 << (DMA_CPY_CHANNEL % 6)));//Open channel clock
CLRREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), 0);//DTCn = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_NDES);
}
void LcdPdd_SetPowerLevel(void){
unsigned char val;
// LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001
OUTREG32(0x48041238, DISPC_CONTROL_TFTDATALINES_24 | DISPC_CONTROL_STNTFT | 1<<0);//DISPC_CONTROL2
// Apply display configuration
SETREG32(0x48041238, DISPC_CONTROL_GOLCD);//DISPC_CONTROL2
// Start scanning
SETREG32(0x48041238, DISPC_CONTROL_LCDENABLE );//DISPC_CONTROL2
// Add delay to prevent blinking screen.
udelay(10000);
}
//------------------------------------------------------------------------------
//
// Function: enable_lcd_power
//
// This function enables the power for the LCD controller
//
UINT32 enable_lcd_power( void )
{
OMAP_PRCM_DSS_CM_REGS *pPrcmRegs = OALPAtoUA(OMAP_PRCM_DSS_CM_REGS_PA);
//OALMSG(OAL_INFO, (L"enable_lcd_power+\r\n"));
SETREG32(&pPrcmRegs->CM_FCLKEN_DSS, (CM_CLKEN_DSS1 | CM_CLKEN_DSS2));
SETREG32(&pPrcmRegs->CM_ICLKEN_DSS, (CM_CLKEN_DSS));
//OALMSG(OAL_INFO, (L"enable_lcd_power-\r\n"));
return ERROR_SUCCESS;
}
void pwm_set_duty(unsigned int chn, unsigned int percent)
{
unsigned int full_cycles;
static unsigned int old_percent=1;
if (percent == 108)
{
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
return;
}
if (percent > 100)
{
printf("The percent of PWM should be within 100\n");
return;
}
if (percent == 0)
{
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
if(old_percent!=0)
{
__gpio_as_output(4*32+20+chn);
__gpio_clear_pin(4*32+20+chn);
}
old_percent=0;
}
else
{
if(old_percent==0)
{
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
}
full_cycles = INREG16(A_TCU_TDFR(chn));
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG16(A_TCU_TDHR(chn), full_cycles - (full_cycles * percent) / 110);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
old_percent=percent;
}
}
void LcdPdd_LCD_Initialize(void){
unsigned int val = 0;
val = INREG32(0x4a009120);//CM_DSS_DSS_CLKCTRL
val = val & ~(0x0502);
// Setup the DSS1 clock divider - disable DSS1 clock, change divider, enable DSS clock
OUTREG32(0x4a009120, val);//CM_DSS_DSS_CLKCTRL
udelay(10000);
SETREG32(0x4a00815c, 8<<0);//CM_DIV_M5_DPLL_PER
udelay(10000);
//printf("CM_CLKSEL_DSS= %x\n",INREG32(CM_CLKSEL_DSS));
val = INREG32(0x4a009120) ;//CM_DSS_DSS_CLKCTRL
val = val | 0x0502;
OUTREG32(0x4a009120, 0x00000502);
udelay(10000);
// LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001
OUTREG32(0x48041238, DISPC_CONTROL_TFTDATALINES_24 | DISPC_CONTROL_STNTFT);//DISPC_CONTROL2
// Default Color
OUTREG32(0x480413ac, 0x00000000);//DISPC_DEFAULT_COLOR2
// LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001
SETREG32(0x48041238, 0<<12);//DISPC_CONTROL2 OVERLAYOPTIMIZATION
// Default Transparency Color
OUTREG32(0x480413b0, 0);//DISPC_TRANS_COLOR2
SETREG32(0x48041044, 0x4<<0);//DISPC_CONFIG1 LOAD_MODE: Frame data only loaded every frame
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Signal configuration
// OUTREG32(0x48041408,DISPC_POL_FREQ_ONOFF);//DISPC_POL_FREQ2
OUTREG32(0x48041408,0x00003000);//DISPC_POL_FREQ2
udelay(10000);
// Configure the divisor
OUTREG32(0x4804140c,DISPC_DIVISOR_R(LCD_PIXCLKDIV,LCD_LOGCLKDIV));//DISPC_DIVISOR2 (PCD 4,LCD 1)
// Configure the panel size
OUTREG32(0x480413cc,DISPC_SIZE_LCD_R(LCD_HEIGHT,LCD_WIDTH));//DISPC_SIZE_LCD2 (1024,600)
// Timing logic for HSYNC signal
OUTREG32(0x48041400,DISPC_TIMING(LCD_HSW-1,LCD_HFP-1,LCD_HBP-1));//DISPC_TIMING_H2
// Timing logic for VSYNC signal
OUTREG32(0x48041404,DISPC_TIMING(LCD_VSW-1,LCD_VFP,LCD_VBP));//DISPC_TIMING_V2
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
}
static void enable_tv_detect(bool tv_enable)
{
// disable ACCDET unit before switch the detect way
OUTREG32(ACCDET_CTRL, ACCDET_DISABLE);
OUTREG32(ACCDET_STATE_SWCTRL, 0);
if(tv_enable)
{
}
else
{
// switch analog switch from tv out to mic
OUTREG32(ACCDET_STATE_SWCTRL, ACCDET_SWCTRL_EN);
// init the accdet MIC detect unit
SETREG32(ACCDET_RSTB, MIC_INIT_BIT);
CLRREG32(ACCDET_RSTB, MIC_INIT_BIT);
}
ACCFIX_DEBUG("[accfix]enable_tv_detect:ACCDET_STATE_SWCTRL =%x\n",
INREG32(ACCDET_STATE_SWCTRL));
// enable ACCDET unit
OUTREG32(ACCDET_CTRL, ACCDET_ENABLE);
}
//-----------------------------------------------------------------------------
BOOL
NAND_LockBlocks(
HANDLE hNand,
UINT blockStart,
UINT blockEnd,
BOOL bLock
)
{
BOOL rc = FALSE;
NandDevice_t *pDevice = (NandDevice_t*)hNand;
UNREFERENCED_PARAMETER(blockEnd);
UNREFERENCED_PARAMETER(blockStart);
if (pDevice == NULL) goto cleanUp;
if (bLock)
{
CLRREG32(&pDevice->pGpmcRegs->GPMC_CONFIG, GPMC_CONFIG_WRITEPROTECT);
}
else
{
SETREG32(&pDevice->pGpmcRegs->GPMC_CONFIG, GPMC_CONFIG_WRITEPROTECT);
}
rc = TRUE;
cleanUp:
return rc;
}
//////////
// Function Name : OTGDevice_DeInit
// Function Desctiption : This function de-initializes OTG PHY and LINK.
// Input : NONE
// Output : NONE
// Version :
void OTGDevice_DeInit()
{
DWORD epNum;
// Clear USB Interrupt enable registers
OUTREG32(GINTMSK, 0);
// Disable all RX, TX EPs
if (INREG32(DIEPCTL0) & DEPCTL_EPENA)
OUTREG32(DIEPCTL0, DEPCTL_EPDIS);
if (INREG32(DOEPCTL0) & DEPCTL_EPENA)
OUTREG32(DOEPCTL0, DEPCTL_EPDIS);
for (epNum = 1; epNum < MAX_ENDPTS; epNum++)
{
if (INREG32(DIEPCTL[epNum]) & DEPCTL_EPENA)
OUTREG32(DIEPCTL[epNum], DEPCTL_EPDIS);
if (INREG32(DOEPCTL[epNum]) & DEPCTL_EPENA)
OUTREG32(DOEPCTL[epNum], DEPCTL_EPDIS);
}
SETREG32(PCGCCTL, (1<<0)); //stop pclk
}
////////////////////////////////////////////////////
// 功能: 音频初始化
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void jz_audio_reset(void)
{
CLRREG32(AIC_CR, AIC_CR_ERPL | AIC_CR_EREC);
SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
OUTREG32(AIC_SR, 0x00000000);
}
////////////////////////////////////////////////////
// 功能: 关闭声音设备
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void CloseMediaDevice(char channel)
{
int arg;
int time;
arg = ((channel == 0) ? RECORD_CHANNEL : PLAYBACK_CHANNEL );
//等待DMA结束
time = 0;
while( INREG32(A_DMA_DTC(arg)) )
{
#ifdef KPRINTF_DEF
kprintf("close media device : count = %x\n",INREG32(A_DMA_DTC(arg)));
#endif
sTimerSleep(10, NULL);
//加入延迟处理，防止死锁
time++;
if( time > 10 )
{
kdebug(mod_media, PRINT_WARNING, "close media device timer out\n");
break;
}
}
//stop dma
CLRREG32(A_DMA_DCS(arg), DCS_AR | DCS_HLT | DCS_CTE | DCS_CT);
//close aic
CLRREG32(AIC_CR, AIC_CR_ERPL);
SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
OUTREG32(AIC_SR, 0x00000000);
#ifndef CODEC_ALWAYS_OPEN
CloseMediaCodecDevice();
#endif
}
//------------------------------------------------------------------------------
//
// Function: ClockSetup
//
// Initializes clocks and power. Stack based initialization only - no
// global variables allowed.
//
void ClockSetup(pCPU_OPP_Settings opp_setting)
{
OMAP_PRCM_CLOCK_CONTROL_PRM_REGS* pPrcmClkPRM = OALPAtoUA(OMAP_PRCM_CLOCK_CONTROL_PRM_REGS_PA);
OMAP_PRCM_WKUP_CM_REGS* pPrcmWkupCM = OALPAtoUA(OMAP_PRCM_WKUP_CM_REGS_PA);
OMAP_PRCM_PER_CM_REGS* pPrcmPerCM = OALPAtoUA(OMAP_PRCM_PER_CM_REGS_PA);
OMAP_PRCM_CORE_CM_REGS* pPrcmCoreCM = OALPAtoUA(OMAP_PRCM_CORE_CM_REGS_PA);
// setup input system clock
OUTREG32(&pPrcmClkPRM->PRM_CLKSEL, BSP_PRM_CLKSEL);
if(gCPU_family == CPU_FAMILY_DM37XX)
{
Omap37xx_core_dpll_init();
Omap37xx_dpll4_init();
Mpu_dpll_init(opp_setting);
Iva_dpll_init(opp_setting);
Omap37xx_per_dpll_init();
}
else
{
/*Core_dpll_init();
Dpll4_init();
Mpu_dpll_init(opp_setting);
Iva_dpll_init(opp_setting);
Per_dpll_init();*/
}
//--------------------------
// Enable GPTIMER1, GPIO bank 1 (debug led)
SETREG32(&pPrcmWkupCM->CM_FCLKEN_WKUP, (CM_CLKEN_GPT1|CM_CLKEN_GPIO1));
SETREG32(&pPrcmWkupCM->CM_ICLKEN_WKUP, (CM_CLKEN_GPT1|CM_CLKEN_GPIO1));
// Enable UART3 (debug port) and GPIO banks that are accessed in the bootloader
SETREG32(&pPrcmPerCM->CM_FCLKEN_PER, (CM_CLKEN_UART3|CM_CLKEN_GPIO6|CM_CLKEN_GPIO5|CM_CLKEN_GPIO3));
SETREG32(&pPrcmPerCM->CM_ICLKEN_PER, (CM_CLKEN_UART3|CM_CLKEN_GPIO6|CM_CLKEN_GPIO5|CM_CLKEN_GPIO3));
// Disable HS USB OTG interface clock
CLRREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_HSOTGUSB);
// Disable D2D interface clock
CLRREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_D2D);
}
//------------------------------------------------------------------------------
//
// Function: WatchdogSetup
//
// Initializes watchdog timer settings.
//
static VOID WatchdogSetup()
{
/* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
either taken care of by ROM (HS/EMU) or not accessible (GP).
We need to take care of WD2-MPU or take a PRCM reset. WD3
should not be running and does not generate a PRCM reset. */
OMAP_PRCM_WKUP_CM_REGS *pPrcmWkupCM = OALPAtoUA(OMAP_PRCM_WKUP_CM_REGS_PA);
OMAP_WDOG_REGS *pWdogTimer = OALPAtoUA(OMAP_WDOG2_REGS_PA);
SETREG32(&pPrcmWkupCM->CM_FCLKEN_WKUP, CM_CLKEN_WDT2);
SETREG32(&pPrcmWkupCM->CM_ICLKEN_WKUP, CM_CLKEN_WDT2);
WaitOnValue(CM_IDLEST_ST_WDT2, CM_IDLEST_ST_WDT2, &pPrcmWkupCM->CM_IDLEST_WKUP, 5); // Some issue here
OUTREG32(&pWdogTimer->WSPR, WDOG_DISABLE_SEQ1);
while (INREG32(&pWdogTimer->WWPS));
OUTREG32(&pWdogTimer->WSPR, WDOG_DISABLE_SEQ2);
}
int jz4755tve_open(void)
{
// enable tve controller, enable DACn
CLRREG32(A_TV_TVECR, TV_TVECR_SWRST);
SETREG32(A_TV_TVECR, TV_TVECR_DAPD);
#if (TV_VIDEO_OUT_MODE == TV_OUT_MODE_3DIV)
CLRREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2 | TV_TVECR_DAPD3);
#else
CLRREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2);
#endif
}
void
OMAP2420DMAContext::HWInitOutputDMA()
{
OMAP2420_DMA_REGS *pDMAReg;
DWORD dwAddr, dwVal;
DEBUGMSG(ZONE_FUNCTION, (L"+OMAP2420DMAContext::HWInitOutputDMA()\r\n"));
pDMAReg = m_pOutDMAReg;
// disable the channel, clear the configuration
SETREG32(&pDMAReg->DMA4_CCR, 0);
// link this channel to itself to get continuous operation
OUTREG32(&pDMAReg->DMA4_CLNK_CTRL, AUDIO_OUTPUT_DMA_CHANNEL);
// 16 bits scalar, no pack, no burst
OUTREG32(&pDMAReg->DMA4_CSDP, DMA_CSDP_DATATYPE_16BIT);
// request number, post incremented source address, high priority
dwVal = DMA_CCR_SYNC(AUDIO_OUTPUT_DMA_REQ) | DMA_CCR_SRC_AMODE_POST_INC | DMA_CCR_PRIO;
OUTREG32(&pDMAReg->DMA4_CCR, dwVal);
// source address
dwAddr = m_paAudioDMA.LowPart;
OUTREG32(&pDMAReg->DMA4_CSSA, dwAddr);
// destination address
OUTREG32(&pDMAReg->DMA4_CDSA, AUDIO_OUTPUT_DMA_DEST);
// interrupt conditions
dwVal = DMA_CICR_FRAME_IE | DMA_CICR_HALF_IE | DMA_CICR_DROP_IE;
OUTREG32(&pDMAReg->DMA4_CICR, dwVal);
// number of samples per frame
OUTREG32(&pDMAReg->DMA4_CEN, AUDIO_DMA_PAGE_SIZE);
// number of frames per block
OUTREG32(&pDMAReg->DMA4_CFN, 1);
// source frame index and element index
OUTREG32(&pDMAReg->DMA4_CSFI, 0);
OUTREG32(&pDMAReg->DMA4_CSEI, 0);
// destination frame index and element index
OUTREG32(&pDMAReg->DMA4_CDFI, 0);
OUTREG32(&pDMAReg->DMA4_CDEI, 0);
#if defined(DEBUG)
DumpDMA_LC(L"Init Output", pDMAReg);
#endif
DEBUGMSG(ZONE_FUNCTION, (L"-OMAP2420DMAContext::WInitOutputDMA()\r\n"));
}
/*****************************************************************************
* 函 数 名 : efuseRead
*
* 功能描述 : 按组读取EFUSE中的数据
*
* 输入参数 : group 起始group
* num 数组长度(word数,不超过512/4=128)
* 输出参数 : pBuf ：EFUSE中的数据
*
* 返 回 值 :
*
* 其它说明 :
*
*****************************************************************************/
int efuseRead(UINT32 group, UINT32* pBuf, UINT32 num)
{
UINT32* pSh;
UINT32 cnt;
if((group+num > EFUSE_MAX_SIZE/WORD_SIZE)||(NULL == pBuf))
{
return ERROR;
}
pSh = pBuf;
/* 设置EFUSE信号为APB信号 */
SETREG32(EFUSEC_CFG, EFUSEC_APB);
/* 循环读取Efuse值 */
for(cnt=group; cnt<num; cnt++)
{
/* 设置读取地址 */
OUTREG32(EFUSE_GROUP, group+cnt);
/* 使能读 */
SETREG32(EFUSEC_CFG, EFUSEC_RD_EN);
/* 等待读使能设置成功，读使能超时返回错误 */
if(!TestBitValue(EFUSEC_CFG, EFUSEC_RD_EN, EFUSEC_RD_EN))
{
return ERROR;
}
/* 等待读完成 */
if(!TestBitValue(EFUSEC_STATUS, EFUSEC_RD_STATUS, EFUSEC_RD_STATUS))
{
return ERROR;
}
/* 读取数据 */
*pSh = INREG32(EFUSEC_DATA);
pSh++;
}
return OK;
}
//------------------------------------------------------------------------------
void
PrcmVoltFlushVoltageLevels(
VoltageProcessor_e vp
)
{
switch (vp)
{
case kVoltageProcessor1:
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
break;
case kVoltageProcessor2:
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
break;
default:
return;
}
}
int Init_PerformanceCounter(void)
{
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
OUTREG32(A_OST_CSR, TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
OUTREG32(A_OST_DR, 0xFFFFFFFF);
OUTREG32(A_OST_CNT, 0);
SETREG32(A_TCU_TESR, TCU_OSTEN);
return ((OSC_CLOCK / 4 ) / 1000000);
}
void switch_asw_to_tv(bool tv_enable)
{
ACCFIX_DEBUG("[accfix]switch analog switch to tv is %d\n",tv_enable);
if(tv_enable)
{
SETREG32(ACCDET_STATE_SWCTRL,TV_DET_BIT);
//hwSPKClassABAnalogSwitchSelect(ACCDET_TV_CHA);
}
else
{
CLRREG32(ACCDET_STATE_SWCTRL,TV_DET_BIT);
//hwSPKClassABAnalogSwitchSelect(ACCDET_MIC_CHA);
}
}
int cmd_mw(int argc, CmdArg* argv) {
cmd_start();
if(argc != 3) {
puts("usage: mw <address> <value>\n");
return 0;
}
unsigned int address = argv[1].uinteger;
unsigned int value = argv[2].uinteger;
SETREG32(address, value);
//clear_cpu_caches();
return 0;
}
void dma_copy_nowait(void *tar,void *src,int size)
{
int timeout = 0x1000000;
while ((!(INREG32(A_DMA_DCS(DMA_CPY_CHANNEL)) & DCS_TT)) && (timeout--));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
OUTREG32(A_DMA_DSA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)src));
OUTREG32(A_DMA_DTA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)tar));
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), size / 32);
OUTREG32(A_DMA_DRT(DMA_CPY_CHANNEL), DRT_AUTO);
OUTREG32(A_DMA_DCM(DMA_CPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL),(DCS_TT));
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE | DCS_NDES);
}
////////////////////////////////////////////////////
// 功能: 触发DMA中断，传送数据
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void DmaDataToAic(int arg,unsigned int sour_addr, unsigned int len,unsigned char mode)
{
if( !arg )
{ //放音DMA
dma_cache_wback_inv(sour_addr, len);
CLRREG32(AIC_SR, AIC_SR_TUR);
SETREG32(AIC_CR, AIC_CR_ERPL);
dma_start(PLAYBACK_CHANNEL, PHYADDR(sour_addr), PHYADDR(AIC_DR),len,mode);
if (INREG32(AIC_SR) & AIC_SR_TUR)
CLRREG32(AIC_SR, AIC_SR_TUR);
}
else
{ //录音DMA
__dcache_inv((unsigned long)sour_addr, len);
SETREG32(AIC_CR, AIC_CR_EREC);
dma_start(RECORD_CHANNEL, PHYADDR(AIC_DR), PHYADDR(sour_addr),len,mode);
if (INREG32(A_AIC_AICSR) & AICSR_ROR)
CLRREG32(A_AIC_AICSR, AICSR_ROR);
}
}
