void SPIClass::begin()
{
/* Protect from a scheduler and prevent transactionBegin*/
uint32_t flags = interrupt_lock();
if (!initialized) {
interruptMode = 0;
interruptMask[0] = 0;
interruptMask[1] = 0;
interruptMask[2] = 0;
#ifdef SPI_TRANSACTION_MISMATCH_LED
inTransactionFlag = 0;
#endif
lsbFirst = false;
frameSize = SPI_8_BIT;
/* Set SS to high so a connected chip will be "deselected" by default.
* TODO - confirm that data register is updated even if pin is set as
* input. */
digitalWrite(ss_gpio, HIGH);
/* When the SS pin is set as OUTPUT, it can be used as
* a general purpose output port (it doesn't influence
* SPI operations). */
pinMode(ss_gpio, OUTPUT);
/* disable controller */
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;
/* Enable clock to peripheral */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= enable_val;
/* Configure defaults for clock divider, frame size and data mode */
SPI_M_REG_VAL(spi_addr, BAUDR) = SPI_CLOCK_DIV4;
SPI_M_REG_VAL(spi_addr, CTRL0) =
(frameSize << SPI_FSIZE_SHIFT) | (SPI_MODE0 << SPI_MODE_SHIFT);
/* Disable interrupts */
SPI_M_REG_VAL(spi_addr, IMR) = SPI_DISABLE_INT;
/* Enable at least one slave device (mandatory, though
* SS signals are unused) */
SPI_M_REG_VAL(spi_addr, SER) = 0x1;
/* Enable controller */
SPI_M_REG_VAL(spi_addr, SPIEN) |= SPI_ENABLE;
/* Set SoC pin mux configuration */
SET_PIN_MODE(g_APinDescription[MOSI].ulSocPin, SPI_MUX_MODE);
SET_PIN_MODE(g_APinDescription[MISO].ulSocPin, SPI_MUX_MODE);
SET_PIN_MODE(g_APinDescription[SCK].ulSocPin, SPI_MUX_MODE);
}
initialized++; /* reference count */
interrupt_unlock(flags);
}
void Curie_I2S::muxTX(bool enable)
{
int mux_mode = GPIO_MUX_MODE;
if(enable)
{
mux_mode = I2S_MUX_MODE;
}
/* Set SoC pin mux configuration */
SET_PIN_MODE(g_APinDescription[I2S_TXD].ulSocPin, mux_mode);
SET_PIN_MODE(g_APinDescription[I2S_TWS].ulSocPin, mux_mode);
SET_PIN_MODE(g_APinDescription[I2S_TSCK].ulSocPin, mux_mode);
}
void Curie_I2S::muxRX(bool enable)
{
int mux_mode = GPIO_MUX_MODE;
if(enable)
{
mux_mode = I2S_MUX_MODE;
}
/* Set SoC pin mux configuration */
SET_PIN_MODE(49, mux_mode); //I2S_RXD
SET_PIN_MODE(51, mux_mode); //I2S_RWS
SET_PIN_MODE(50, mux_mode); //I2S_RSCK
}
void ss_gpio_srv_test(void)
{
uint8_t init_tst_input_pin_mode = GET_PIN_MODE(MUX_SS_INPUT_PIN);
uint8_t init_tst_output_pin_mode = GET_PIN_MODE(MUX_SS_OUTPUT_PIN);
SET_PIN_MODE(MUX_SS_INPUT_PIN, QRK_PMUX_SEL_MODEA);
SET_PIN_MODE(MUX_SS_OUTPUT_PIN, QRK_PMUX_SEL_MODEA);
generic_gpio_srv_test(SS_GPIO_SERVICE_ID, TST_SS_INPUT_PIN, TST_SS_OUTPUT_PIN, "SS");
/* Restore default configuration for SS pins */
SET_PIN_MODE(MUX_SS_INPUT_PIN, init_tst_input_pin_mode);
SET_PIN_MODE(MUX_SS_OUTPUT_PIN, init_tst_output_pin_mode);
}
void vnh2sp30_reset(void) {
SET_PIN_MODE(VNH2SP30_DIAGA_PORT, VNH2SP30_DIAGA_PIN, OUTPUT);
SET_PIN_MODE(VNH2SP30_DIAGB_PORT, VNH2SP30_DIAGB_PIN, OUTPUT);
vnh2sp30_clear_INA();
vnh2sp30_clear_INB();
vnh2sp30_set_PWM_dutycycle(0);
IO_SET_LOW(VNH2SP30_DIAGA_PORT, VNH2SP30_DIAGA_PIN);
IO_SET_LOW(VNH2SP30_DIAGB_PORT, VNH2SP30_DIAGB_PIN);
vnh2sp30_init_DIAGA();
vnh2sp30_init_DIAGB();
}
void pinMode( uint8_t pin, uint8_t mode )
{
if (pin >= NUM_DIGITAL_PINS) return;
PinDescription *p = &g_APinDescription[pin];
if (mode == OUTPUT) {
p->ulInputMode = OUTPUT_MODE;
if (p->ulGPIOType == SS_GPIO) {
uint32_t reg = p->ulGPIOBase + SS_GPIO_SWPORTA_DDR;
SET_ARC_BIT(reg, p->ulGPIOId);
}
else if (p->ulGPIOType == SOC_GPIO) {
uint32_t reg = p->ulGPIOBase + SOC_GPIO_SWPORTA_DDR;
SET_MMIO_BIT(reg, p->ulGPIOId);
}
} else {
p->ulInputMode = INPUT_MODE;
if (p->ulGPIOType == SS_GPIO) {
uint32_t reg = p->ulGPIOBase + SS_GPIO_SWPORTA_DDR;
CLEAR_ARC_BIT(reg, p->ulGPIOId);
}
else if (p->ulGPIOType == SOC_GPIO) {
uint32_t reg = p->ulGPIOBase + SOC_GPIO_SWPORTA_DDR;
CLEAR_MMIO_BIT(reg, p->ulGPIOId);
}
}
/* Set SoC pin mux configuration */
SET_PIN_PULLUP(p->ulSocPin, (mode == INPUT_PULLUP) ? 1 : 0);
if (p->ulPinMode != GPIO_MUX_MODE) {
SET_PIN_MODE(p->ulSocPin, GPIO_MUX_MODE);
p->ulPinMode = GPIO_MUX_MODE;
}
}
uint32_t analogRead(uint32_t pin)
{
uint32_t val = 0;
/* allow for channel or pin numbers */
if (pin < 6) pin += A0;
PinDescription *p = &g_APinDescription[pin];
/* Disable pull-up and set pin mux for ADC output */
SET_PIN_MODE(p->ulSocPin, ADC_MUX_MODE);
SET_PIN_PULLUP(p->ulSocPin,0);
/* Reset sequence pointer */
SET_ARC_MASK(ADC_CTRL, ADC_SEQ_PTR_RST);
/* Update sequence table */
WRITE_ARC_REG(p->ulAdcChan, ADC_SEQ);
/* Reset sequence pointer & start sequencer */
SET_ARC_MASK(ADC_CTRL, ADC_SEQ_PTR_RST | ADC_SEQ_START | ADC_ENABLE);
/* Poll for ADC data ready status (DATA_A) */
while((READ_ARC_REG(ADC_INTSTAT) & ADC_INT_DATA_A) == 0);
/* Pop the data sample from FIFO to sample register */
SET_ARC_MASK(ADC_SET, ADC_POP_SAMPLE);
/* Read sample from sample register */
val = READ_ARC_REG( ADC_SAMPLE);
/* Clear the DATA_A status bit */
SET_ARC_MASK( ADC_CTRL, ADC_CLR_DATA_A);
return mapResolution(val, ADC_RESOLUTION, _readResolution);
}
void digitalWrite( uint8_t pin, uint8_t val )
{
if (pin >= NUM_DIGITAL_PINS) return;
PinDescription *p = &g_APinDescription[pin];
if(pinmuxMode[pin] != GPIO_MUX_MODE)
{
pinmuxMode[pin] = GPIO_MUX_MODE;
SET_PIN_MODE(p->ulSocPin, GPIO_MUX_MODE);
}
if (p->ulGPIOType == SS_GPIO) {
uint32_t reg = p->ulGPIOBase + SS_GPIO_SWPORTA_DR;
if (val)
SET_ARC_BIT(reg, p->ulGPIOId);
else
CLEAR_ARC_BIT(reg, p->ulGPIOId);
}
else if (p->ulGPIOType == SOC_GPIO) {
uint32_t reg = p->ulGPIOBase + SOC_GPIO_SWPORTA_DR;
if (val)
SET_MMIO_BIT(reg, p->ulGPIOId);
else
CLEAR_MMIO_BIT(reg, p->ulGPIOId);
}
if (val)
SET_PIN_PULLUP(p->ulSocPin,1);
else
SET_PIN_PULLUP(p->ulSocPin,0);
}
void UARTClass::end( void )
{
int ret=0;
uint8_t uc_data;
// Wait for any outstanding data to be sent
flush();
uart_irq_rx_disable(CONFIG_UART_CONSOLE_INDEX);
uart_irq_tx_disable(CONFIG_UART_CONSOLE_INDEX);
while ( ret != -1 ) {
ret = uart_poll_in(CONFIG_UART_CONSOLE_INDEX, &uc_data);
}
opened = false;
// Clear any received data
_rx_buffer->_iHead = _rx_buffer->_iTail;
SET_PIN_MODE(17, GPIO_MUX_MODE); // Rdx SOC PIN (Arduino header pin 0)
SET_PIN_MODE(16, GPIO_MUX_MODE); // Txd SOC PIN (Arduino header pin 1)
}
void dfu_spi_init(void){
/* pinmuxing */
SET_PIN_MODE(55, QRK_PMUX_SEL_MODEB); /* SPI0_M_SCK */
SET_PIN_MODE(56, QRK_PMUX_SEL_MODEB); /* SPI0_M_MISO */
SET_PIN_MODE(57, QRK_PMUX_SEL_MODEB); /* SPI0_M_MOSI */
/* SPI0_M CS is controlled as a gpio */
SET_PIN_MODE(58, QRK_PMUX_SEL_MODEA); /* GPIO[24]/SPI0_M_CS_0 */
/* spi0 clock gating */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= SPI0_CLK_GATE_MASK;
spi_cfg_data_t spi_cfg;
spi_cfg.speed = 4000; /*!< SPI bus speed in KHz */
spi_cfg.txfr_mode = SPI_TX_RX; /*!< Transfer mode */
spi_cfg.data_frame_size = SPI_8_BIT; /*!< Data Frame Size ( 4 - 16 bits ) */
spi_cfg.bus_mode = SPI_BUSMODE_0; /*!< SPI bus mode is 0 by default */
soc_spi_set_config(&spi_cfg);
}
void shift_init()
{
SET_PIN_MODE(55, QRK_PMUX_SEL_MODEA);
SET_PIN_MODE(57, QRK_PMUX_SEL_MODEA);
SET_PIN_MODE(58, QRK_PMUX_SEL_MODEA);
gpio_cfg_data_t config;
config.gpio_type = GPIO_OUTPUT;
config.int_type = EDGE;
config.int_polarity = ACTIVE_LOW;
config.int_debounce = DEBOUNCE_OFF;
config.int_ls_sync = LS_SYNC_OFF;
config.gpio_cb = NULL;
config.gpio_cb_arg = NULL;
gpio_set_config(gpio_dev, CLOCK_BIT, &config);
gpio_set_config(gpio_dev, DATA_BIT, &config);
gpio_set_config(gpio_dev, LATCH_BIT, &config);
}
void button_init(void) {
// Set up for right wheel
SET_PIN_MODE(BUTTON_A_PORT, BUTTON_A_PIN, INPUT_PULLUP);
// Generate synchronous interrupt on rising edge
EICRB |= ((1 << BUTTON_A_ISC1) | (0 << BUTTON_A_ISC0));
BIT_SET(EIMSK, BUTTON_A_INT); // Interrupt enable
// Set up for left wheel
SET_PIN_MODE(BUTTON_B_PORT, BUTTON_B_PIN, INPUT_PULLUP);
// Generate synchronous interrupt on rising edge
EICRB |= ((1 << BUTTON_B_ISC1) | (0 << BUTTON_B_ISC0));
BIT_SET(EIMSK, BUTTON_B_INT); // Interrupt enable
// Setup neutral button
//SET_PIN_MODE(NEUTRAL_PORT, NEUTRAL_PIN, INPUT);
SET_PIN_MODE(PORTF, PIN5, INPUT_PULLUP);
SET_PIN_MODE(PORTF, PIN7, INPUT_PULLUP);
}
static void init(void) {
usart1_init(115200, buf_in, ARR_LEN(buf_in), buf_out, ARR_LEN(buf_out));
sysclock_init();
adc_init(1, AVCC, 4);
can_init();
vnh2sp30_init();
vnh2sp30_active_break_to_Vcc();
SET_PIN_MODE(NEUT_PORT, NEUT_PIN, INPUT_PULLUP);
SET_PIN_MODE(IGN_PORT, IGN_PIN, OUTPUT);
IGNITION_UNCUT();
can_subscribe(PADDLE_STATUS);
can_subscribe(NEUTRAL_ENABLED);
can_subscribe(GEAR_STOP_BUTTON);
can_subscribe(RESET_GEAR_ESTIMATE);
sei();
puts_P(PSTR("Init complete\n\n"));
}
void analogWrite(uint8_t pin, uint32_t val)
{
if (! digitalPinHasPWM(pin))
{
if(val > 127)
{
digitalWrite(pin, HIGH);
}
else
{
digitalWrite(pin, LOW);
}
return;
}
if (val <= 0) {
/* Use GPIO for 0% duty cycle (always off) */
pinMode(pin, OUTPUT);
digitalWrite(pin, LOW);
} else if (val >= ((1 << _writeResolution) - 1)) {
/* Use GPIO for 100% duty cycle (always on) */
pinMode(pin, OUTPUT);
digitalWrite(pin, HIGH);
} else {
/* PWM for everything in between */
PinDescription *p = &g_APinDescription[pin];
uint32_t offset;
uint32_t hcnt = (val/(float)maxResolutionValue) * pwmPeriod[p->ulPwmChan];
uint32_t lcnt = pwmPeriod[p->ulPwmChan] - hcnt;
/* Set the high count period (duty cycle) */
offset = ((p->ulPwmChan * QRK_PWM_N_LCNT2_LEN) + QRK_PWM_N_LOAD_COUNT2);
MMIO_REG_VAL(QRK_PWM_BASE_ADDR + offset) = hcnt;
/* Set the low count period (duty cycle) */
offset = ((p->ulPwmChan * QRK_PWM_N_REGS_LEN) + QRK_PWM_N_LOAD_COUNT1);
MMIO_REG_VAL(QRK_PWM_BASE_ADDR + offset) = lcnt;
/* start the PWM output */
offset = ((p->ulPwmChan * QRK_PWM_N_REGS_LEN) + QRK_PWM_N_CONTROL);
SET_MMIO_MASK(QRK_PWM_BASE_ADDR + offset, QRK_PWM_CONTROL_ENABLE);
if(pinmuxMode[pin] != PWM_MUX_MODE)
{
/* Disable pull-up and set pin mux for PWM output */
SET_PIN_PULLUP(p->ulSocPin, 0);
SET_PIN_MODE(p->ulSocPin, PWM_MUX_MODE);
pinmuxMode[pin] = PWM_MUX_MODE;
}
}
}
uint8_t swd_init(void)
{
btfu_dap_error_t error_code = SWD_ERROR_OK;
SET_PIN_MODE(NRF_SWCLK_PIN, QRK_PMUX_SEL_MODEA);
SET_PIN_MODE(NRF_SWDIO_PIN, QRK_PMUX_SEL_MODEA);
hw_BtfuDapInit();
hw_BtfuDapHardReset();
//Connect to the target in debug mode
if ((error_code = swd_connect_to_target()) != SWD_ERROR_OK){
return error_code;
}
//Unlock the MPU
if ((error_code = swd_unlock_target()) != SWD_ERROR_OK){
return error_code;
}
return error_code;
}
void gpio_aon_test(void)
{
uint8_t init_tst_input_pin_mode = GET_PIN_MODE(TST_SOC_AON_INPUT_PIN);
uint8_t init_tst_output_pin_mode = GET_PIN_MODE(TST_SOC_AON_OUTPUT_PIN);
cu_print("##################################################\n");
cu_print("# #\n");
cu_print("# !!! Pins %d and %d must be connected !!! #\n", TST_SOC_AON_INPUT_PIN, TST_SOC_AON_OUTPUT_PIN);
cu_print("# #\n");
cu_print("# Purpose of aon GPIOs tests on port %d: #\n", TST_SOC_AON_PORT);
cu_print("# Validate input/output ports #\n");
cu_print("# Validate interrupts (edge low) #\n");
cu_print("# Validate interrupts (edge high) #\n");
cu_print("# Validate interrupts (double edge) #\n");
cu_print("##################################################\n");
DRIVER_API_RC ret;
struct device *aon_dev = &pf_device_soc_gpio_aon;
/* Change Pin Mode of pin 5 and 6 to be as GPIO */
SET_PIN_MODE(TST_SOC_AON_INPUT_PIN, QRK_PMUX_SEL_MODEA);
SET_PIN_MODE(TST_SOC_AON_OUTPUT_PIN, QRK_PMUX_SEL_MODEA);
ret = soc_gpio_test_pin(aon_dev, TST_SOC_AON_INPUT_PIN, TST_SOC_AON_OUTPUT_PIN);
CU_ASSERT("Test for gpio pin failed", ret == DRV_RC_OK);
ret = soc_gpio_test_port(aon_dev, TST_SOC_AON_INPUT_PIN, TST_SOC_AON_OUTPUT_PIN);
CU_ASSERT("Test for gpio port failed", ret == DRV_RC_OK);
ret = soc_gpio_test_pin_int(aon_dev, TST_SOC_AON_INPUT_PIN, TST_SOC_AON_OUTPUT_PIN);
CU_ASSERT("Test for gpio pin interrupt failed", ret == DRV_RC_OK);
ret = soc_gpio_test_port_int(aon_dev, TST_SOC_AON_INPUT_PIN, TST_SOC_AON_OUTPUT_PIN);
CU_ASSERT("Test for gpio port interrupt failed", ret == DRV_RC_OK);
/* Restore default configuration for AON pins */
SET_PIN_MODE(TST_SOC_AON_INPUT_PIN, init_tst_input_pin_mode);
SET_PIN_MODE(TST_SOC_AON_OUTPUT_PIN, init_tst_output_pin_mode);
}
/** Power on and prepare for general usage.
* This will prepare the SPI communication interface for accessing the BMI160
* on the Curie module, before calling BMI160::initialize() to activate the
* BMI160 accelerometer and gyroscpoe with default settings.
*/
bool CurieIMUClass::begin()
{
/* Configure pin-mux settings on the Intel Curie module to
* enable SPI mode usage */
SET_PIN_MODE(35, QRK_PMUX_SEL_MODEA); // SPI1_SS_MISO
SET_PIN_MODE(36, QRK_PMUX_SEL_MODEA); // SPI1_SS_MOSI
SET_PIN_MODE(37, QRK_PMUX_SEL_MODEA); // SPI1_SS_SCK
SET_PIN_MODE(38, QRK_PMUX_SEL_MODEA); // SPI1_SS_CS_B[0]
ss_spi_init();
/* Perform a dummy read from 0x7f to switch to spi interface */
uint8_t dummy_reg = 0x7F;
serial_buffer_transfer(&dummy_reg, 1, 1);
/* The SPI interface is ready - now invoke the base class initialization */
BMI160Class::initialize();
/** Verify the SPI connection.
* MakgetGyroRatee sure the device is connected and responds as expected.
* @return True if connection is valid, false otherwise
*/
return (CURIE_IMU_CHIP_ID == getDeviceID());
}
void UARTClass::init(const uint32_t dwBaudRate, const uint8_t modeReg)
{
uint8_t c;
// Make sure both ring buffers are initialized back to empty.
_rx_buffer->_iHead = _rx_buffer->_iTail = 0;
_tx_buffer->_iHead = _tx_buffer->_iTail = 0;
SET_PIN_MODE(17, UART_MUX_MODE); // Rdx SOC PIN (Arduino header pin 0)
SET_PIN_MODE(16, UART_MUX_MODE); // Txd SOC PIN (Arduino header pin 1)
info->options = 0;
info->sys_clk_freq = SYSCLK_DEFAULT_IOSC_HZ;
info->baud_rate = dwBaudRate;
info->regs = CONFIG_UART_CONSOLE_REGS;
info->irq = CONFIG_UART_CONSOLE_IRQ;
info->int_pri = CONFIG_UART_CONSOLE_INT_PRI;
info->async_format = modeReg;
uart_init(CONFIG_UART_CONSOLE_INDEX, info);
uart_irq_rx_disable(CONFIG_UART_CONSOLE_INDEX);
uart_irq_tx_disable(CONFIG_UART_CONSOLE_INDEX);
uart_int_connect(CONFIG_UART_CONSOLE_INDEX, /* UART to which to connect */
UART_Handler, /* interrupt handler */
NULL, /* argument to pass to handler */
NULL /* ptr to interrupt stub code */
);
while (uart_irq_rx_ready(CONFIG_UART_CONSOLE_INDEX))
uart_fifo_read(CONFIG_UART_CONSOLE_INDEX, &c, 1);
uart_irq_rx_enable(CONFIG_UART_CONSOLE_INDEX);
}
void variantGpioInit(void)
{
#define GPIO_CLKENA_POS (31)
#define GPIO_LS_SYNC_POS (0)
/* Enable SoC GPIO peripheral clock */
SET_MMIO_BIT((SOC_GPIO_BASE_ADDR+SOC_GPIO_LS_SYNC), GPIO_CLKENA_POS);
SET_MMIO_BIT((SOC_GPIO_BASE_ADDR+SOC_GPIO_LS_SYNC), GPIO_LS_SYNC_POS);
/* Enable SS_GPIO port 0 peripheral clock */
SET_ARC_BIT((SS_GPIO_8B0_BASE_ADDR+SS_GPIO_LS_SYNC), GPIO_CLKENA_POS);
SET_ARC_BIT((SS_GPIO_8B0_BASE_ADDR+SS_GPIO_LS_SYNC), GPIO_LS_SYNC_POS);
/* Enable SS_GPIO port 1 peripheral clock */
SET_ARC_BIT((SS_GPIO_8B1_BASE_ADDR+SS_GPIO_LS_SYNC), GPIO_CLKENA_POS);
SET_ARC_BIT((SS_GPIO_8B1_BASE_ADDR+SS_GPIO_LS_SYNC), GPIO_LS_SYNC_POS);
for (uint8_t pin = 0; pin < NUM_DIGITAL_PINS; pin++) {
PinDescription *p = &g_APinDescription[pin];
SET_PIN_MODE(p->ulSocPin, p->ulPinMode);
}
}
void shiftlight_init(void) {
SET_PIN_MODE(SHIFT_LIGHT_PORT, SHIFT_LIGHT_B, OUTPUT);
SET_PIN_MODE(SHIFT_LIGHT_PORT, SHIFT_LIGHT_R, OUTPUT);
shiftlight_off();
}
