static void
bfin_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu)
{
memset (&cpu->state, 0, sizeof (cpu->state));
PROFILE_TOTAL_INSN_COUNT (CPU_PROFILE_DATA (cpu)) = 0;
bfin_model_cpu_init (sd, cpu);
/* Set default stack to top of scratch pad. */
SET_SPREG (BFIN_DEFAULT_MEM_SIZE);
SET_KSPREG (BFIN_DEFAULT_MEM_SIZE);
SET_USPREG (BFIN_DEFAULT_MEM_SIZE);
/* This is what the hardware likes. */
SET_SYSCFGREG (0x30);
}
static void
bfin_user_init (SIM_DESC sd, SIM_CPU *cpu, struct bfd *abfd,
const char * const *argv, const char * const *env)
{
/* XXX: Missing host -> target endian ... */
/* Linux starts the user app with the stack:
argc
argv[0] -- pointers to the actual strings
argv[1..N]
NULL
env[0]
env[1..N]
NULL
auxvt[0].type -- ELF Auxiliary Vector Table
auxvt[0].value
auxvt[1..N]
AT_NULL
0
argv[0..N][0..M] -- actual argv/env strings
env[0..N][0..M]
FDPIC loadmaps -- for FDPIC apps
So set things up the same way. */
int i, argc, envc;
bu32 argv_flat, env_flat;
bu32 sp, sp_flat;
/* start, at_phdr, at_phnum, at_base, at_entry, pt_dynamic */
bu32 elf_addrs[6];
bu32 auxvt;
bu32 exec_loadmap, ldso_loadmap;
char *ldso_path;
unsigned char null[4] = { 0, 0, 0, 0 };
host_callback *cb = STATE_CALLBACK (sd);
elf_addrs[0] = elf_addrs[4] = bfd_get_start_address (abfd);
elf_addrs[1] = elf_addrs[2] = elf_addrs[3] = elf_addrs[5] = 0;
/* Keep the load addresses consistent between runs. Also make sure we make
space for the fixed code region (part of the Blackfin Linux ABI). */
fdpic_load_offset = 0x1000;
/* First try to load this as an FDPIC executable. */
sp = SPREG;
if (!bfin_fdpic_load (sd, cpu, STATE_PROG_BFD (sd), &sp, elf_addrs, &ldso_path))
goto skip_fdpic_init;
exec_loadmap = sp;
/* If that worked, then load the fixed code region. We only do this for
FDPIC ELFs atm because they are PIEs and let us relocate them without
manual fixups. FLAT files however require location processing which
we do not do ourselves, and they link with a VMA of 0. */
sim_write (sd, 0x400, bfin_linux_fixed_code, sizeof (bfin_linux_fixed_code));
/* If the FDPIC needs an interpreter, then load it up too. */
if (ldso_path)
{
const char *ldso_full_path = concat (simulator_sysroot, ldso_path, NULL);
struct bfd *ldso_bfd;
ldso_bfd = bfd_openr (ldso_full_path, STATE_TARGET (sd));
if (!ldso_bfd)
{
sim_io_eprintf (sd, "bfin-sim: bfd open failed: %s\n", ldso_full_path);
goto static_fdpic;
}
if (!bfd_check_format (ldso_bfd, bfd_object))
sim_io_eprintf (sd, "bfin-sim: bfd format not valid: %s\n", ldso_full_path);
bfd_set_arch_info (ldso_bfd, STATE_ARCHITECTURE (sd));
if (!bfin_fdpic_load (sd, cpu, ldso_bfd, &sp, elf_addrs, &ldso_path))
sim_io_eprintf (sd, "bfin-sim: FDPIC ldso failed to load: %s\n", ldso_full_path);
if (ldso_path)
sim_io_eprintf (sd, "bfin-sim: FDPIC ldso (%s) needs an interpreter (%s) !?\n",
ldso_full_path, ldso_path);
ldso_loadmap = sp;
}
else
static_fdpic:
ldso_loadmap = 0;
/* Finally setup the registers required by the FDPIC ABI. */
SET_DREG (7, 0); /* Zero out FINI funcptr -- ldso will set this up. */
SET_PREG (0, exec_loadmap); /* Exec loadmap addr. */
SET_PREG (1, ldso_loadmap); /* Interp loadmap addr. */
SET_PREG (2, elf_addrs[5]); /* PT_DYNAMIC map addr. */
auxvt = 1;
SET_SPREG (sp);
skip_fdpic_init:
sim_pc_set (cpu, elf_addrs[0]);
/* Figure out how much storage the argv/env strings need. */
argc = count_argc (argv);
if (argc == -1)
argc = 0;
argv_flat = argc; /* NUL bytes */
for (i = 0; i < argc; ++i)
argv_flat += strlen (argv[i]);
if (!env)
env = simple_env;
envc = count_argc (env);
env_flat = envc; /* NUL bytes */
for (i = 0; i < envc; ++i)
env_flat += strlen (env[i]);
/* Push the Auxiliary Vector Table between argv/env and actual strings. */
sp_flat = sp = ALIGN (SPREG - argv_flat - env_flat - 4, 4);
if (auxvt)
{
# define AT_PUSH(at, val) \
auxvt_size += 8; \
sp -= 4; \
auxvt = (val); \
sim_write (sd, sp, (void *)&auxvt, 4); \
sp -= 4; \
auxvt = (at); \
sim_write (sd, sp, (void *)&auxvt, 4)
unsigned int egid = getegid (), gid = getgid ();
unsigned int euid = geteuid (), uid = getuid ();
bu32 auxvt_size = 0;
AT_PUSH (AT_NULL, 0);
AT_PUSH (AT_SECURE, egid != gid || euid != uid);
AT_PUSH (AT_EGID, egid);
AT_PUSH (AT_GID, gid);
AT_PUSH (AT_EUID, euid);
AT_PUSH (AT_UID, uid);
AT_PUSH (AT_ENTRY, elf_addrs[4]);
AT_PUSH (AT_FLAGS, 0);
AT_PUSH (AT_BASE, elf_addrs[3]);
AT_PUSH (AT_PHNUM, elf_addrs[2]);
AT_PUSH (AT_PHENT, sizeof (Elf32_External_Phdr));
AT_PUSH (AT_PHDR, elf_addrs[1]);
AT_PUSH (AT_CLKTCK, 100); /* XXX: This ever not 100 ? */
AT_PUSH (AT_PAGESZ, 4096);
AT_PUSH (AT_HWCAP, 0);
#undef AT_PUSH
}
SET_SPREG (sp);
/* Push the argc/argv/env after the auxvt. */
sp -= ((1 + argc + 1 + envc + 1) * 4);
SET_SPREG (sp);
/* First push the argc value. */
sim_write (sd, sp, (void *)&argc, 4);
sp += 4;
/* Then the actual argv strings so we know where to point argv[]. */
for (i = 0; i < argc; ++i)
{
unsigned len = strlen (argv[i]) + 1;
sim_write (sd, sp_flat, (void *)argv[i], len);
sim_write (sd, sp, (void *)&sp_flat, 4);
sp_flat += len;
sp += 4;
}
sim_write (sd, sp, null, 4);
sp += 4;
/* Then the actual env strings so we know where to point env[]. */
for (i = 0; i < envc; ++i)
{
unsigned len = strlen (env[i]) + 1;
sim_write (sd, sp_flat, (void *)env[i], len);
sim_write (sd, sp, (void *)&sp_flat, 4);
sp_flat += len;
sp += 4;
}
/* Set some callbacks. */
cb->syscall_map = cb_linux_syscall_map;
cb->errno_map = cb_linux_errno_map;
cb->open_map = cb_linux_open_map;
cb->signal_map = cb_linux_signal_map;
cb->stat_map = stat_map_32 = cb_linux_stat_map_32;
stat_map_64 = cb_linux_stat_map_64;
}
void
cec_return (SIM_CPU *cpu, int ivg)
{
SIM_DESC sd = CPU_STATE (cpu);
struct bfin_cec *cec;
bool snen;
int curr_ivg;
bu32 oldpc, newpc;
oldpc = PCREG;
BFIN_CPU_STATE.did_jump = true;
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
{
SET_PCREG (cec_read_ret_reg (cpu, ivg));
TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
return;
}
cec = CEC_STATE (cpu);
/* XXX: This isn't entirely correct ... */
cec->ipend &= ~IVG_EMU_B;
curr_ivg = _cec_get_ivg (cec);
if (curr_ivg == -1)
curr_ivg = IVG_USER;
if (ivg == -1)
ivg = curr_ivg;
TRACE_EVENTS (cpu, "returning from EVT%i (should be EVT%i)", curr_ivg, ivg);
/* Not allowed to return from usermode. */
if (curr_ivg == IVG_USER)
cec_exception (cpu, VEC_ILL_RES);
if (ivg > IVG15 || ivg < 0)
sim_io_error (sd, "%s: ivg %i out of range !", __func__, ivg);
_cec_require_supervisor (cpu, cec);
switch (ivg)
{
case IVG_EMU:
/* RTE -- only valid in emulation mode. */
/* XXX: What does the hardware do ? */
if (curr_ivg != IVG_EMU)
cec_exception (cpu, VEC_ILL_RES);
break;
case IVG_NMI:
/* RTN -- only valid in NMI. */
/* XXX: What does the hardware do ? */
if (curr_ivg != IVG_NMI)
cec_exception (cpu, VEC_ILL_RES);
break;
case IVG_EVX:
/* RTX -- only valid in exception. */
/* XXX: What does the hardware do ? */
if (curr_ivg != IVG_EVX)
cec_exception (cpu, VEC_ILL_RES);
break;
default:
/* RTI -- not valid in emulation, nmi, exception, or user. */
/* XXX: What does the hardware do ? */
if (curr_ivg == IVG_EMU || curr_ivg == IVG_NMI
|| curr_ivg == IVG_EVX || curr_ivg == IVG_USER)
cec_exception (cpu, VEC_ILL_RES);
break;
case IVG_IRPTEN:
/* XXX: Is this even possible ? */
excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
break;
}
newpc = cec_read_ret_reg (cpu, ivg);
/* XXX: Does this nested trick work on EMU/NMI/EVX ? */
snen = (newpc & 1);
/* XXX: Delayed clear shows bad PCREG register trace above ? */
SET_PCREG (newpc & ~1);
TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (from EVT%i)", ivg);
/* Update ipend after the TRACE_BRANCH so dv-bfin_trace
knows current CEC state wrt overflow. */
if (!snen)
cec->ipend &= ~(1 << ivg);
/* Disable global interrupt mask to let any interrupt take over, but
only when we were already in a RTI level. Only way we could have
raised at that point is if it was cleared in the first place. */
if (ivg >= IVG_IVHW || ivg == IVG_RST)
cec_irpten_disable (cpu, cec);
/* When going from super to user, we clear LSB in LB regs in case
it was set on the transition up.
Also need to load SP alias with USP. */
if (_cec_get_ivg (cec) == -1)
{
int i;
for (i = 0; i < 2; ++i)
if (LBREG (i) & 1)
SET_LBREG (i, LBREG (i) & ~1);
SET_KSPREG (SPREG);
SET_SPREG (USPREG);
}
/* Check for pending interrupts before we return to usermode. */
_cec_check_pending (cpu, cec);
}
static void
_cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
{
SIM_DESC sd = CPU_STATE (cpu);
int curr_ivg = _cec_get_ivg (cec);
bool snen;
bool irpten;
TRACE_EVENTS (cpu, "processing request for EVT%i while at EVT%i",
ivg, curr_ivg);
irpten = (cec->ipend & IVG_IRPTEN_B);
snen = (SYSCFGREG & SYSCFG_SNEN);
if (curr_ivg == -1)
curr_ivg = IVG_USER;
/* Just check for higher latched interrupts. */
if (ivg == -1)
{
if (irpten)
goto done; /* All interrupts are masked anyways. */
ivg = __cec_get_ivg (cec->ilat & cec->imask);
if (ivg < 0)
goto done; /* Nothing latched. */
if (ivg > curr_ivg)
goto done; /* Nothing higher latched. */
if (!snen && ivg == curr_ivg)
goto done; /* Self nesting disabled. */
/* Still here, so fall through to raise to higher pending. */
}
cec->ilat |= (1 << ivg);
if (ivg <= IVG_EVX)
{
/* These two are always processed. */
if (ivg == IVG_EMU || ivg == IVG_RST)
goto process_int;
/* Anything lower might trigger a double fault. */
if (curr_ivg <= ivg)
{
/* Double fault ! :( */
SET_EXCAUSE (VEC_UNCOV);
/* XXX: SET_RETXREG (...); */
sim_io_error (sd, "%s: double fault at 0x%08x ! :(", __func__, PCREG);
excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
}
/* No double fault -> always process. */
goto process_int;
}
else if (irpten && curr_ivg != IVG_USER)
{
/* Interrupts are globally masked. */
}
else if (!(cec->imask & (1 << ivg)))
{
/* This interrupt is masked. */
}
else if (ivg < curr_ivg || (snen && ivg == curr_ivg))
{
/* Do transition! */
bu32 oldpc;
process_int:
cec->ipend |= (1 << ivg);
cec->ilat &= ~(1 << ivg);
/* Interrupts are processed in between insns which means the return
point is the insn-to-be-executed (which is the current PC). But
exceptions are handled while executing an insn, so we may have to
advance the PC ourselves when setting RETX.
XXX: Advancing the PC should only be for "service" exceptions, and
handling them after executing the insn should be OK, which
means we might be able to use the event interface for it. */
oldpc = PCREG;
switch (ivg)
{
case IVG_EMU:
/* Signal the JTAG ICE. */
/* XXX: what happens with 'raise 0' ? */
SET_RETEREG (oldpc);
excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
/* XXX: Need an easy way for gdb to signal it isnt here. */
cec->ipend &= ~IVG_EMU_B;
break;
case IVG_RST:
/* Have the core reset simply exit (i.e. "shutdown"). */
excp_to_sim_halt (sim_exited, 0);
break;
case IVG_NMI:
/* XXX: Should check this. */
SET_RETNREG (oldpc);
break;
case IVG_EVX:
/* Non-service exceptions point to the excepting instruction. */
if (EXCAUSE >= 0x20)
SET_RETXREG (oldpc);
else
{
bu32 nextpc = hwloop_get_next_pc (cpu, oldpc, INSN_LEN);
SET_RETXREG (nextpc);
}
break;
case IVG_IRPTEN:
/* XXX: what happens with 'raise 4' ? */
sim_io_error (sd, "%s: what to do with 'raise 4' ?", __func__);
break;
default:
SET_RETIREG (oldpc | (ivg == curr_ivg ? 1 : 0));
break;
}
/* If EVT_OVERRIDE is in effect (IVG7+), use the reset address. */
if ((cec->evt_override & 0xff80) & (1 << ivg))
SET_PCREG (cec_get_reset_evt (cpu));
else
SET_PCREG (cec_get_evt (cpu, ivg));
TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (to EVT%i):", ivg);
BFIN_CPU_STATE.did_jump = true;
/* Enable the global interrupt mask upon interrupt entry. */
if (ivg >= IVG_IVHW)
cec_irpten_enable (cpu, cec);
}
/* When moving between states, don't let internal states bleed through. */
DIS_ALGN_EXPT &= ~1;
/* When going from user to super, we set LSB in LB regs to avoid
misbehavior and/or malicious code.
Also need to load SP alias with KSP. */
if (curr_ivg == IVG_USER)
{
int i;
for (i = 0; i < 2; ++i)
if (!(LBREG (i) & 1))
SET_LBREG (i, LBREG (i) | 1);
SET_USPREG (SPREG);
SET_SPREG (KSPREG);
}
done:
TRACE_EVENTS (cpu, "now at EVT%i", _cec_get_ivg (cec));
}
