/*****************************************************************************
函 数 名 : DRV_DDR_PHY_TO_VIRT
功能描述 : DDR内存虚地址往实地址转换
输入参数 : ulPAddr；实地址
输出参数 : 无
返回值 ：虚地址
*****************************************************************************/
unsigned int DRV_DDR_PHY_TO_VIRT(unsigned int ulPAddr)
{
if((ulPAddr >= DDR_SHARED_MEM_ADDR)
&& (ulPAddr < DDR_SHARED_MEM_ADDR + DDR_SHARED_MEM_SIZE))
{
return SHD_DDR_P2V(ulPAddr);
}
if((ulPAddr >= DDR_GU_ADDR)
&& (ulPAddr < DDR_GU_ADDR + DDR_GU_SIZE))
{
return (ulPAddr - DDR_GU_ADDR + DDR_GU_ADDR_VIRT);
}
printk("DRV_DDR_PHY_TO_VIRT: ulVAddr(0x%x) is invalid!\n",ulPAddr);
return 0;
}
/*****************************************************************************
函 数 名 : DRV_DDR_PHY_TO_VIRT
功能描述 : DDR内存虚地址往实地址转换
输入参数 : ulPAddr；实地址
输出参数 : 无
返回值 ：虚地址
*****************************************************************************/
void* DRV_DDR_PHY_TO_VIRT(void* ulPAddr)
{
if(((u32)ulPAddr >= (u32)DDR_SHARED_MEM_ADDR)
&& ((u32)ulPAddr < (u32)DDR_SHARED_MEM_ADDR + DDR_SHARED_MEM_SIZE))
{
return (void *)SHD_DDR_P2V(ulPAddr);
}
if(((u32)ulPAddr >= (u32)DDR_GU_ADDR)
&& ((u32)ulPAddr < (u32)DDR_GU_ADDR + DDR_GU_SIZE))
{
return (void*)((u32)ulPAddr - (u32)DDR_GU_ADDR + (u32)DDR_GU_ADDR_VIRT);
}
printk("DRV_DDR_PHY_TO_VIRT: ulVAddr(0x%p) is invalid!\n",ulPAddr);
return (void*)0;
}
void show_shared_ddr_status(void)
{
/*请依照先后顺序增加打印输出项*/
int total_size = SHM_MEM_APPA9_PM_BOOT_SIZE + SHM_MEM_MDMA9_PM_BOOT_SIZE + SHM_MEM_SYNC_SIZE + SHM_MEM_ICC_SIZE +
SHM_MEM_IPF_SIZE + SHM_MEM_WAN_SIZE + SHM_MEM_NV_SIZE + SHM_MEM_M3_MNTN_SIZE +
SHM_MEM_HIFI_SIZE + SHM_MEM_HIFI_MBX_SIZE + SHM_DDM_LOAD_SIZE + SHM_TIMESTAMP_SIZE +
SHM_MEM_IOS_SIZE + SHM_MEM_MODEM_PINTRL_SIZE + SHM_MEM_TEMPERATURE_SIZE +SHM_MEM_RESTORE_AXI_SIZE +
SHM_MEMMGR_FLAG_SIZE + SHM_PMU_OCP_INFO_SIZE + SHM_PMU_VOLTTABLE_SIZE + SHM_MEM_HW_VER_SIZE +
SHM_MEM_PTABLE_SIZE + SHM_MEM_MEMMGR_SIZE + SHM_MEM_NAND_SPEC_SIZE +CORESHARE_MEM_TENCILICA_MULT_BAND_SIZE;
printf("%-30s%10s%10s%10s\n", "name", "phy addr", "virt addr", "size");
printf("%-30s%10x%10x%10x\n", "SHM_MEM_APPA9_PM_BOOT_ADDR", SHD_DDR_V2P(SHM_MEM_APPA9_PM_BOOT_ADDR), SHM_MEM_APPA9_PM_BOOT_ADDR, SHM_MEM_APPA9_PM_BOOT_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MDMA9_PM_BOOT_ADDR", SHD_DDR_V2P(SHM_MEM_MDMA9_PM_BOOT_ADDR), SHM_MEM_MDMA9_PM_BOOT_ADDR, SHM_MEM_MDMA9_PM_BOOT_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_SYNC_ADDR", SHD_DDR_V2P(SHM_MEM_SYNC_ADDR), SHM_MEM_SYNC_ADDR, SHM_MEM_SYNC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_ICC_ADDR", SHD_DDR_V2P(SHM_MEM_ICC_ADDR), SHM_MEM_ICC_ADDR, SHM_MEM_ICC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_IPF_ADDR", SHD_DDR_V2P(SHM_MEM_IPF_ADDR),SHM_MEM_IPF_ADDR, SHM_MEM_IPF_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_WAN_ADDR", SHD_DDR_V2P(SHM_MEM_WAN_ADDR), SHM_MEM_WAN_ADDR, SHM_MEM_WAN_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_NV_ADDR", SHD_DDR_V2P(SHM_MEM_NV_ADDR), SHM_MEM_NV_ADDR, SHM_MEM_NV_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_M3_MNTN_ADDR", SHD_DDR_V2P(SHM_MEM_M3_MNTN_ADDR), SHM_MEM_M3_MNTN_ADDR, SHM_MEM_M3_MNTN_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HIFI_ADDR", SHD_DDR_V2P(SHM_MEM_HIFI_ADDR), SHM_MEM_HIFI_ADDR, SHM_MEM_HIFI_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HIFI_MBX_ADDR", SHD_DDR_V2P(SHM_MEM_HIFI_MBX_ADDR), SHM_MEM_HIFI_MBX_ADDR, SHM_MEM_HIFI_MBX_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_DDM_LOAD_ADDR", SHD_DDR_V2P(SHM_DDM_LOAD_ADDR), SHM_DDM_LOAD_ADDR, SHM_DDM_LOAD_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_TIMESTAMP_ADDR", SHD_DDR_V2P(SHM_TIMESTAMP_ADDR), SHM_TIMESTAMP_ADDR, SHM_TIMESTAMP_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_IOS_ADDR", SHD_DDR_V2P(SHM_MEM_IOS_ADDR), SHM_MEM_IOS_ADDR, SHM_MEM_IOS_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MODEM_PINTRL_ADDR", SHD_DDR_V2P(SHM_MEM_MODEM_PINTRL_ADDR), SHM_MEM_MODEM_PINTRL_ADDR, SHM_MEM_MODEM_PINTRL_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_TEMPERATURE_ADDR", SHD_DDR_V2P(SHM_MEM_TEMPERATURE_ADDR), SHM_MEM_TEMPERATURE_ADDR, SHM_MEM_TEMPERATURE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_RESTORE_AXI_ADDR", SHD_DDR_V2P(SHM_MEM_RESTORE_AXI_ADDR), SHM_MEM_RESTORE_AXI_ADDR, SHM_MEM_RESTORE_AXI_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEMMGR_FLAG_ADDR", SHD_DDR_V2P(SHM_MEMMGR_FLAG_ADDR), SHM_MEMMGR_FLAG_ADDR, SHM_MEMMGR_FLAG_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_PMU_OCP_INFO_ADDR", SHD_DDR_V2P(SHM_PMU_OCP_INFO_ADDR), SHM_PMU_OCP_INFO_ADDR, SHM_PMU_OCP_INFO_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_PMU_VOLTTABLE_ADDR", SHD_DDR_V2P(SHM_PMU_VOLTTABLE_ADDR), SHM_PMU_VOLTTABLE_ADDR, SHM_PMU_VOLTTABLE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HW_VER_ADDR", SHD_DDR_V2P(SHM_MEM_HW_VER_ADDR), SHM_MEM_HW_VER_ADDR, SHM_MEM_HW_VER_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_DSP_FLAG_ADDR", SHD_DDR_V2P(SHM_MEM_DSP_FLAG_ADDR), SHM_MEM_DSP_FLAG_ADDR, SHM_MEM_DSP_FLAG_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_PTABLE_ADDR", SHD_DDR_V2P(SHM_MEM_PTABLE_ADDR), SHM_MEM_PTABLE_ADDR, SHM_MEM_PTABLE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_PASTAR_DPM_INFO_ADDR", SHD_DDR_V2P(SHM_MEM_PASTAR_DPM_INFO_ADDR), SHM_MEM_PASTAR_DPM_INFO_ADDR, SHM_MEM_PASTAR_DPM_INFO_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_LOADM_ADDR", SHD_DDR_V2P(SHM_MEM_LOADM_ADDR), SHM_MEM_LOADM_ADDR, SHM_MEM_LOADM_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_NAND_SPEC_ADDR", SHD_DDR_V2P(SHM_MEM_NAND_SPEC_ADDR), SHM_MEM_NAND_SPEC_ADDR, SHM_MEM_NAND_SPEC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MEMMGR_ADDR", SHD_DDR_V2P(SHM_MEM_MEMMGR_ADDR), SHM_MEM_MEMMGR_ADDR, SHM_MEM_MEMMGR_SIZE);
printf("%-30s%10x%10x%10x\n", "CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR", CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR, SHD_DDR_P2V(CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR), CORESHARE_MEM_TENCILICA_MULT_BAND_SIZE);/*lint !e778 */
printf("total size: 0x%x\n", total_size);
}
