//! Initialise SPI
//!
//! @param default ctar0 value for SPI.CTAR0 register
//! @param default ctar1 value for SPI.CTAR1 register
//!
//! @note a default frequency is used.
//!
void spi_init(uint32_t ctar0, uint32_t ctar1) {
ctar0Value = ctar0;
ctar1Value = ctar1;
// Configure SPI
(void)spi_setSpeed(0);
SPI0->MCR = SPI_MCR_CLR_RXF_MASK|SPI_MCR_ROOE_MASK|SPI_MCR_CLR_TXF_MASK|SPI_MCR_PCSIS((1<<0)|(1<<1))|
SPI_MCR_MSTR_MASK|SPI_MCR_FRZ_MASK|SPI_MCR_DCONF(0)|SPI_MCR_SMPL_PT(0);
}
/*********************************************************
* Name: SPI_Init
* Desc: Initialize SPI2 Module
* Parameter: None
* Return: None
**********************************************************/
void SPI_Init(void)
{
/*Body*/
/* set PORTE pin 1 to DSPI1.SOUT*/
#ifdef MCU_MK70F12
PORTE_PCR1 = PORT_PCR_MUX(7);
#else
PORTE_PCR1 = PORT_PCR_MUX(2);
#endif // MCU_MK70F12
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
#ifdef MCU_MK70F12
PORTE_PCR3 = PORT_PCR_MUX(7);
#else
PORTE_PCR3 = PORT_PCR_MUX(2);
#endif // MCU_MK70F12
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
#ifdef MCU_MK70F12
SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;
#else
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#endif // MCU_MK70F12
/* Enable master mode, disable both transmit and receive FIFO buffers,
set the inactive state for PCS2 high, enable the module (MDIS = 0),
delay the sample point from the leading edge of the clock and halt
any transfer
*/
SPI1_MCR = (SPI_MCR_MSTR_MASK |
SPI_MCR_PCSIS(1) |
SPI_MCR_SMPL_PT(2) |
SPI_MCR_HALT_MASK);
SPI1_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
// K60: bus clock: 48MHz, DSPI clock: ~107 KHz
// K70: bus clock: 60MHz, DSPI clock: ~156 KHz
/* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MK70F12
gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x07));
#else
gSPI_BaudRate = (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0x06));
#endif
/* Configure the rest of the delays */
gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x04));
gSPI_AfterTransfDelay = (SPI_CTAR_PASC(3) | SPI_CTAR_ASC(0x04));
gSPI_InterTransfDelay = (SPI_CTAR_PDT(3) | SPI_CTAR_DT(0x05));
}/*EndBody*/
/**
* @brief .
* @param None
* @retval None
*/
void SPI_Configuration (void)
{
/* note:ILI初始化需在AT25芯片初始化之�?*/
/* 开启对应时��?*/
SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
ILI_SIN_PORT->PCR[ILI_SIN_Pin] = (PORT_PCR_MUX(2)
|PORT_PCR_PE_MASK
|PORT_PCR_PS_MASK);
ILI_SOUT_PORT->PCR[ILI_SOUT_Pin] = (PORT_PCR_MUX(2)
|PORT_PCR_PE_MASK
|PORT_PCR_PS_MASK);
ILI_SCK_PORT->PCR[ILI_SCK_Pin] = (PORT_PCR_MUX(2)
|PORT_PCR_PE_MASK
|PORT_PCR_PS_MASK);
ILI_CS_PORT->PCR[ILI_CS_Pin] = (PORT_PCR_MUX(2)
|PORT_PCR_PE_MASK
|PORT_PCR_PS_MASK);
/* 主模�?*/
ILI_SPI->MCR = 0 & (~SPI_MCR_MDIS_MASK)
|SPI_MCR_HALT_MASK
|SPI_MCR_MSTR_MASK
|SPI_MCR_PCSIS_MASK
|SPI_MCR_CLR_TXF_MASK
|SPI_MCR_CLR_RXF_MASK
|SPI_MCR_DIS_TXF_MASK
|SPI_MCR_DIS_RXF_MASK
|SPI_MCR_SMPL_PT(2);
//��分频及波特率
ILI_SPI->CTAR[0] = 0| SPI_CTAR_DBR_MASK //设置�����?
| SPI_CTAR_PCSSCK(0)
| SPI_CTAR_PASC(0)
| SPI_CTAR_PBR(0)
| SPI_CTAR_CSSCK(0)
| SPI_CTAR_ASC (0)
| SPI_CTAR_FMSZ(8)
| SPI_CTAR_PDT(0);
//分频设置
ILI_SPI->CTAR[0] |=SPI_CTAR_BR(0xc);
//�߶钟相位、极��?
//ILI_SPI->CTAR[0] |= SPI_CTAR_CPHA_MASK;
//ILI_SPI->CTAR[0] |= SPI_CTAR_CPOL_MASK;
//ILI_SPI->CTAR[0] |= SPI_CTAR_LSBFE_MASK;
ILI_SPI->SR = SPI_SR_EOQF_MASK
| SPI_SR_TFUF_MASK
| SPI_SR_TFFF_MASK
| SPI_SR_RFOF_MASK
| SPI_SR_RFDF_MASK
| SPI_SR_TCF_MASK;
ILI_SPI->MCR &= ~SPI_MCR_HALT_MASK;
}
/* ===================================================================*/
void SM1_Deinit(LDD_TDeviceData *DeviceDataPtr)
{
(void)DeviceDataPtr; /* Parameter is not used, suppress unused argument warning */
/* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=0,??=0,??=0,PCSIS=0,DOZE=0,MDIS=1,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_MDIS_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Disable device */
/* Restoring the interrupt vector */
/* {Default RTOS Adapter} Restore interrupt vector: IVT is static, no code is generated */
/* Unregistration of the device structure */
PE_LDD_UnregisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID);
/* Deallocation of the device structure */
/* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
/* SIM_SCGC6: SPI1=0 */
SIM_SCGC6 &= (uint32_t)~(uint32_t)(SIM_SCGC6_SPI1_MASK);
}
/* ===================================================================*/
LDD_TDeviceData* SPI_SD_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SPI_SD_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->TxCommand = 0x80000000U; /* Initialization of current Tx command */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->CurrentAttributeSet = 0U; /* Init current attribute set */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* SIM_SCGC6: SPI1=1 */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
/* Interrupt vector(s) priority setting */
/* NVICIP27: PRI27=0x70 */
NVICIP27 = NVIC_IP_PRI27(0x70);
/* NVICISER0: SETENA|=0x08000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x08000000);
/* SIM_SCGC5: PORTD=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
/* PORTD_PCR7: ISF=0,MUX=7 */
PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* PORTD_PCR6: ISF=0,MUX=7 */
PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* PORTD_PCR5: ISF=0,MUX=7 */
PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI1_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_MSTR_MASK |
SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DIS_RXF_MASK |
SPI_MCR_CLR_TXF_MASK |
SPI_MCR_CLR_RXF_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI1_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=0,CSSCK=0,ASC=0,DT=0,BR=0 */
SPI1_CTAR0 = SPI_CTAR_DBR_MASK |
SPI_CTAR_FMSZ(0x07) |
SPI_CTAR_PCSSCK(0x00) |
SPI_CTAR_PASC(0x00) |
SPI_CTAR_PDT(0x00) |
SPI_CTAR_PBR(0x00) |
SPI_CTAR_CSSCK(0x00) |
SPI_CTAR_ASC(0x00) |
SPI_CTAR_DT(0x00) |
SPI_CTAR_BR(0x00); /* Set Clock and Transfer Attributes register */
/* SPI1_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
SPI1_SR = SPI_SR_TCF_MASK |
SPI_SR_EOQF_MASK |
SPI_SR_TFUF_MASK |
SPI_SR_TFFF_MASK |
SPI_SR_RFOF_MASK |
SPI_SR_RFDF_MASK |
SPI_SR_TXCTR(0x00) |
SPI_SR_TXNXTPTR(0x00) |
SPI_SR_RXCTR(0x00) |
SPI_SR_POPNXTPTR(0x00) |
0x00200000U; /* Clear flags */
/* SPI1_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SPI1_RSER = SPI_RSER_RFDF_RE_MASK; /* Set DMA Interrupt Request Select and Enable register */
SPI_SD_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SPI_SD_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/* ===================================================================*/
LDD_TDeviceData* SM1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SM1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_SPI0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->TxCommand = 0x80040000U; /* Initialization of current Tx command */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
/* SIM_SCGC6: SPI0=1 */
SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
/* Interrupt vector(s) priority setting */
/* NVIC_IPR2: PRI_10=1 */
NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_10(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_10(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=1,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA10_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* SIM_SCGC5: PORTE=1,PORTC=1 */
SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTC_MASK);
/* PORTE_PCR18: ISF=0,MUX=6 */
PORTE_PCR18 = (uint32_t)((PORTE_PCR18 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x01)
)) | (uint32_t)(
PORT_PCR_MUX(0x06)
));
/* PORTE_PCR19: ISF=0,MUX=6 */
PORTE_PCR19 = (uint32_t)((PORTE_PCR19 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x01)
)) | (uint32_t)(
PORT_PCR_MUX(0x06)
));
/* PORTC_PCR5: ISF=0,MUX=2 */
PORTC_PCR5 = (uint32_t)((PORTC_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTC_PCR2: ISF=0,MUX=2 */
PORTC_PCR2 = (uint32_t)((PORTC_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* SPI0_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI0_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x04) |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI0_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI0_MCR = SPI_MCR_MSTR_MASK |
SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x04) |
SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DIS_RXF_MASK |
SPI_MCR_CLR_TXF_MASK |
SPI_MCR_CLR_RXF_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI0_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=2,CSSCK=0,ASC=0,DT=0,BR=1 */
SPI0_CTAR0 = SPI_CTAR_DBR_MASK |
SPI_CTAR_FMSZ(0x07) |
SPI_CTAR_PCSSCK(0x00) |
SPI_CTAR_PASC(0x00) |
SPI_CTAR_PDT(0x00) |
SPI_CTAR_PBR(0x02) |
SPI_CTAR_CSSCK(0x00) |
SPI_CTAR_ASC(0x00) |
SPI_CTAR_DT(0x00) |
SPI_CTAR_BR(0x01); /* Set Clock and Transfer Attributes register */
/* SPI0_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
SPI0_SR = SPI_SR_TCF_MASK |
SPI_SR_EOQF_MASK |
SPI_SR_TFUF_MASK |
SPI_SR_TFFF_MASK |
SPI_SR_RFOF_MASK |
SPI_SR_RFDF_MASK |
SPI_SR_TXCTR(0x00) |
SPI_SR_TXNXTPTR(0x00) |
SPI_SR_RXCTR(0x00) |
SPI_SR_POPNXTPTR(0x00) |
0x00200000U; /* Clear flags */
/* SPI0_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SPI0_RSER = SPI_RSER_RFDF_RE_MASK; /* Set DMA Interrupt Request Select and Enable register */
/* SPI0_MCR: HALT=0 */
SPI0_MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/***********************************************************************************************
功能：SPI 初始化
形参：SPI_InitStruct SPI 初始化结构
返回：0
详解：0
************************************************************************************************/
void SPI_Init(SPI_InitTypeDef* SPI_InitStruct)
{
SPI_Type *SPIx = NULL;
PORT_Type *SPI_PORT = NULL;
SPI_DataMapTypeDef *pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct->SPIxDataMap);
SPI_CSMapTypeDef *pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct->SPIxPCSMap);
//参数检测
assert_param(IS_SPI_DATA_CHL(SPI_InitStruct->SPIxDataMap));
assert_param(IS_SPI_PCS_CHL(SPI_InitStruct->SPIxPCSMap));
assert_param(IS_SPI_BAUDRATE(SPI_InitStruct->SPI_BaudRatePrescaler));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
assert_param(IS_SPI_FIRSTBIT(SPI_InitStruct->SPI_FirstBit));
//找出SPI模块 开SPI模块时钟
switch(pSPI_DataMap->SPI_Index)
{
case 0:
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
SPIx = SPI0;
break;
case 1:
SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
SPIx = SPI1;
break;
case 2:
SIM->SCGC3 |= SIM_SCGC3_SPI2_MASK;
SPIx = SPI2;
break;
default:break;
}
//找出对应的PORT
switch(pSPI_DataMap->SPI_GPIO_Index)
{
case 0:
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SPI_PORT = PORTA;
break;
case 1:
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
SPI_PORT = PORTB;
break;
case 2:
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
SPI_PORT = PORTC;
break;
case 3:
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
SPI_PORT = PORTD;
break;
case 4:
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
SPI_PORT = PORTE;
break;
default:break;
}
//开启对应的引脚 SCK SOUT SIN
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
/*SCK配置开漏*/
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
//配置PCS
//找出对应的PORT
switch(pSPI_CSMap->SPI_GPIO_Index)
{
case 0:
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SPI_PORT = PORTA;
break;
case 1:
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
SPI_PORT = PORTB;
break;
case 2:
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
SPI_PORT = PORTC;
break;
case 3:
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
SPI_PORT = PORTD;
break;
case 4:
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
SPI_PORT = PORTE;
break;
default:break;
}
SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] |= PORT_PCR_MUX(pSPI_CSMap->SPI_Alt_Index);
//设置主从模式
(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)?(SPIx->MCR |= SPI_MCR_MSTR_MASK):(SPIx->MCR &= ~SPI_MCR_MSTR_MASK);
//配置SPI主模式寄存器
SPIx->MCR = 0 & (~SPI_MCR_MDIS_MASK)
|SPI_MCR_HALT_MASK //让SPI进入停止模式
|SPI_MCR_MSTR_MASK //配置SPI为主机模式
|SPI_MCR_PCSIS_MASK //PCS为高电平当在SPI不工作的时候
|SPI_MCR_CLR_TXF_MASK //首先要清除MDIS，清除TXF_MASK和RXF_MASK
|SPI_MCR_CLR_RXF_MASK
|SPI_MCR_DIS_TXF_MASK //然后再禁止TXD和RXD FIFO 模式 ，将SPI配置成正常模式
|SPI_MCR_DIS_RXF_MASK
|SPI_MCR_SMPL_PT(2);
//配置分频及波特率
SPIx->CTAR[1] = 0| SPI_CTAR_DBR_MASK //设置通信的
| SPI_CTAR_PCSSCK(0)
| SPI_CTAR_PASC(0)
| SPI_CTAR_PBR(0)
| SPI_CTAR_CSSCK(0)
| SPI_CTAR_FMSZ(SPI_InitStruct->SPI_DataSize -1) //设置数据传输的位数
| SPI_CTAR_PDT(0); //设置片选信号在数据完成后的延时值
//分频设置
SPIx->CTAR[1] |=SPI_CTAR_BR(SPI_InitStruct->SPI_BaudRatePrescaler);
//时钟相位设置
(SPI_InitStruct->SPI_CPHA == SPI_CPHA_1Edge)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPHA_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPHA_MASK);
//时钟极性
(SPI_InitStruct->SPI_CPOL == SPI_CPOL_Low)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPOL_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPOL_MASK);
//配置MSB或者LSD
(SPI_InitStruct->SPI_FirstBit == SPI_FirstBit_MSB)?(SPIx->CTAR[1] &= ~SPI_CTAR_LSBFE_MASK):(SPIx->CTAR[1] |= SPI_CTAR_LSBFE_MASK);
//清空状态
SPIx->SR = SPI_SR_EOQF_MASK //队列结束标志 w1c (write 1 to clear)
| SPI_SR_TFUF_MASK //TX FIFO underflow flag w1c
| SPI_SR_TFFF_MASK //TX FIFO fill flag w1c
| SPI_SR_RFOF_MASK //RX FIFO overflow flag w1c
| SPI_SR_RFDF_MASK //RX FIFO fill flasg w1c (0时为空)
| SPI_SR_TCF_MASK;
//开始传输
SPIx->MCR &= ~SPI_MCR_HALT_MASK; //开始传输，见参考手册1129页
}
void SPI_Configuration (void)
{
SPI_Type *SPIx = NULL;
PORT_Type *SPI_PORT = NULL;
SPI_InitTypeDef SPI_InitStruct;
SPI_DataMapTypeDef *pSPI_DataMap;
SPI_CSMapTypeDef *pSPI_CSMap;
SPI_InitStruct.SPIxDataMap = SPILCD_PORT_DATA;
SPI_InitStruct.SPIxPCSMap = SPILCD_PORT_CS;
SPI_InitStruct.SPI_DataSize = 16;
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStruct.SPI_Mode = SPI_Mode_Master;
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
//SPI_Init(&SPI_InitStruct);
pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct.SPIxPCSMap);
pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct.SPIxDataMap);
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
SPIx = SPI0;
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SPI_PORT = PORTA;
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
/*SCK配置开漏*/
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* SPI_PORT = PORTA;
SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] |= PORT_PCR_MUX(pSPI_CSMap->SPI_Alt_Index);*/
//设置主从模式
(SPI_InitStruct.SPI_Mode == SPI_Mode_Master)?(SPIx->MCR |= SPI_MCR_MSTR_MASK):(SPIx->MCR &= ~SPI_MCR_MSTR_MASK);
SPIx->MCR = 0 & (~SPI_MCR_MDIS_MASK)
|SPI_MCR_HALT_MASK //让SPI进入停止模式
|SPI_MCR_MSTR_MASK //配置SPI为主机模式
|SPI_MCR_PCSIS_MASK //PCS为高电平当在SPI不工作的时候
|SPI_MCR_CLR_TXF_MASK //首先要清除MDIS，清除TXF_MASK和RXF_MASK
|SPI_MCR_CLR_RXF_MASK
|SPI_MCR_DIS_TXF_MASK //然后再禁止TXD和RXD FIFO 模式 ，将SPI配置成正常模式
|SPI_MCR_DIS_RXF_MASK
|SPI_MCR_SMPL_PT(2);
SPIx->CTAR[1] = 0| SPI_CTAR_DBR_MASK //设置通信的
| SPI_CTAR_PCSSCK(0)
| SPI_CTAR_PASC(0)
| SPI_CTAR_ASC(0)
| SPI_CTAR_PBR(0)
| SPI_CTAR_CSSCK(0)
| SPI_CTAR_FMSZ(SPI_InitStruct.SPI_DataSize -1)//设置数据传输的位数
| SPI_CTAR_PDT(0);//设置片选信号在数据完成后的延时值
//分频设置
SPIx->CTAR[1] |=SPI_CTAR_BR(SPI_InitStruct.SPI_BaudRatePrescaler);
//时钟相位设置
(SPI_InitStruct.SPI_CPHA == SPI_CPHA_1Edge)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPHA_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPHA_MASK);
//时钟极性
(SPI_InitStruct.SPI_CPOL == SPI_CPOL_Low)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPOL_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPOL_MASK);
//配置MSB或者LSD
(SPI_InitStruct.SPI_FirstBit == SPI_FirstBit_MSB)?(SPIx->CTAR[1] &= ~SPI_CTAR_LSBFE_MASK):(SPIx->CTAR[1] |= SPI_CTAR_LSBFE_MASK);
//清空状态
SPIx->SR = SPI_SR_EOQF_MASK //队列结束标志 w1c (write 1 to clear)
| SPI_SR_TFUF_MASK //TX FIFO underflow flag w1c
| SPI_SR_TFFF_MASK //TX FIFO fill flag w1c
| SPI_SR_RFOF_MASK //RX FIFO overflow flag w1c
| SPI_SR_RFDF_MASK //RX FIFO fill flasg w1c (0时为空)
| SPI_SR_TCF_MASK;
//开始传输
SPIx->MCR &= ~SPI_MCR_HALT_MASK; //开始传输，见参考手册1129页
AD7687_ReceiveWord ();
NVIC_DisableIRQ (AD7687_SIN_IRQ);
AD7687_SIN_PORT->PCR[AD7687_SIN_Pin]&=~PORT_PCR_IRQC_MASK;
AD7687_SIN_PORT->PCR[AD7687_SIN_Pin]|=PORT_PCR_IRQC(GPIO_IT_RISING);
}
/*********************************************************
* Name: SPI_Init
* Desc: Initialize SPI2 Module
* Parameter: None
* Return: None
**********************************************************/
void SPI_Init(void)
{
/*Body*/
/* set PORTE pin 1 to DSPI1.SOUT*/
#ifdef MCU_MK70F12
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(7);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(7);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;
#elif defined MCU_MK20D5
/* set PORTD pin 1 to SPI0.SOUT*/
PORTD_PCR2 = PORT_PCR_MUX(2);
/* set PORTD pin 1 to SPI0.SCK*/
PORTD_PCR1 = PORT_PCR_MUX(2);
/* set PORTD pin 3 to SPI0.SIN*/
PORTD_PCR3 = PORT_PCR_MUX(2);
/* set PORTD pin 0 to SPI0.CS0*/
PORTD_PCR0 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
#elif defined MCU_MK20D7
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40D7
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40N512VMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK53N512CMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK60N512VMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK21D5
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
/* set PORTB pin 16 to DSPI1.SOUT*/
PORTB_PCR16 = PORT_PCR_MUX(2);
/* set PORTB pin 11 to DSPI1.SCK*/
PORTB_PCR11 = PORT_PCR_MUX(2);
/* set PORTB pin 17 to DSPI1.SIN*/
PORTB_PCR17 = PORT_PCR_MUX(2);
/* set PORTB pin 10 to DSPI1.CS0*/
PORTB_PCR10 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK | SIM_SCGC6_DMAMUX_MASK;
#elif defined MCU_MKL25Z4
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
#else
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_SPI1_MASK;
#endif
/* Enable master mode, disable both transmit and receive FIFO buffers,
set the inactive state for PCS2 high, enable the module (MDIS = 0),
delay the sample point from the leading edge of the clock and halt
any transfer
*/
#ifdef MCU_MK20D5
SPI0_MCR = (SPI_MCR_MSTR_MASK |
SPI_MCR_PCSIS(1) |
SPI_MCR_SMPL_PT(2) |
SPI_MCR_HALT_MASK);
SPI0_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#elif defined MCU_MKL25Z4
PORTE_PCR4 = PORT_PCR_MUX(1);
GPIOE_PDDR |= (1<<4);
SPI_clr_SS();
SPI1_C2 = SPI_C2_SPISWAI_MASK;
SPI1_C1 = SPI_C1_SPE_MASK | SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK;
#else
SPI1_MCR = (SPI_MCR_MSTR_MASK |
SPI_MCR_PCSIS(1) |
SPI_MCR_SMPL_PT(2) |
SPI_MCR_HALT_MASK);
SPI1_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#endif
/* DSPI clock 375 KHz */
/* The system clock fsys = 68 MHz */
// K60: bus clock: 48MHz, DSPI clock: ~107 KHz
// K70: bus clock: 60MHz, DSPI clock: ~156 KHz
/* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MKL25Z4
/* 375KHz SPI clock */
SPI1_BR = SPI_BR_SPPR(7) | SPI_BR_SPR(5); /* SCK = 10us */
#else
#ifdef MCU_MK70F12
gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x07));
#else
gSPI_BaudRate = (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0x06));
#endif
/* Configure the rest of the delays */
gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x04));
gSPI_AfterTransfDelay = (SPI_CTAR_PASC(3) | SPI_CTAR_ASC(0x04));
gSPI_InterTransfDelay = (SPI_CTAR_PDT(3) | SPI_CTAR_DT(0x05));
#endif
}/*EndBody*/
