/*!
\brief get SPI and I2S flag status
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_i2s_flag: SPI/I2S flag status
\arg SPI_FLAG_TBE: transmit buffer empty flag
\arg SPI_FLAG_RBNE: receive buffer not empty flag
\arg SPI_FLAG_TRANS: transmit on-going flag
\arg SPI_FLAG_RXORERR: receive overrun error flag
\arg SPI_FLAG_CONFERR: mode config error flag
\arg SPI_FLAG_CRCERR: CRC error flag
\arg SPI_FLAG_FERR: format error flag
\arg I2S_FLAG_TBE: transmit buffer empty flag
\arg I2S_FLAG_RBNE: receive buffer not empty flag
\arg I2S_FLAG_TRANS: transmit on-going flag
\arg I2S_FLAG_RXORERR: overrun error flag
\arg I2S_FLAG_TXURERR: underrun error flag
\arg I2S_FLAG_CH: channel side flag
\arg I2S_FLAG_FERR: format error flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag)
{
if (SPI_STAT(spi_periph) & spi_i2s_flag) {
return SET;
} else {
return RESET;
}
}
/*!
\brief get SPI and I2S interrupt flag status
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_i2s_int: SPI/I2S interrupt flag status
\arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
\arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
\arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
\arg SPI_INT_FLAG_CONFERR: config error interrupt flag
\arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag
\arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag
\arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
{
uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_CTL1(spi_periph);
switch (spi_i2s_int) {
/* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_FLAG_TBE :
reg1 = reg1 & SPI_STAT_TBE;
reg2 = reg2 & SPI_CTL1_TBEIE;
break;
/* SPI/I2S receive buffer not empty interrupt */
case SPI_I2S_INT_FLAG_RBNE :
reg1 = reg1 & SPI_STAT_RBNE;
reg2 = reg2 & SPI_CTL1_RBNEIE;
break;
/* SPI/I2S overrun interrupt */
case SPI_I2S_INT_FLAG_RXORERR :
reg1 = reg1 & SPI_STAT_RXORERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI config error interrupt */
case SPI_INT_FLAG_CONFERR :
reg1 = reg1 & SPI_STAT_CONFERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI CRC error interrupt */
case SPI_INT_FLAG_CRCERR :
reg1 = reg1 & SPI_STAT_CRCERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* I2S underrun error interrupt */
case I2S_INT_FLAG_TXURERR :
reg1 = reg1 & SPI_STAT_TXURERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI/I2S format error interrupt */
case SPI_I2S_INT_FLAG_FERR :
reg1 = reg1 & SPI_STAT_FERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
default :
break;
}
/*get SPI/I2S interrupt flag status */
if (reg1 && reg2) {
return SET;
} else {
return RESET;
}
}
/*!
\brief get interrupt flag status
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_i2s_int:
\arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
\arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
\arg SPI_I2S_INT_RXORERR: overrun interrupt
\arg SPI_INT_CONFERR: config error interrupt
\arg SPI_INT_CRCERR: CRC error interrupt
\arg I2S_INT_TXURERR: underrun error interrupt
\arg SPI_I2S_INT_FERR: format error interrupt
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
{
uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_CTL1(spi_periph);
uint32_t temp1 = 0U;
uint32_t temp2 = 0U;
switch(spi_i2s_int){
case SPI_I2S_INT_TBE :
temp1 = reg1 & SPI_STAT_TBE;
temp2 = reg2 & SPI_CTL1_TBEIE;
break;
case SPI_I2S_INT_RBNE :
temp1 = reg1 & SPI_STAT_RBNE;
temp2 = reg2 & SPI_CTL1_RBNEIE;
break;
case SPI_I2S_INT_RXORERR :
temp1 = reg1 & SPI_STAT_RXORERR;
temp2 = reg2 & SPI_CTL1_ERRIE;
break;
case SPI_INT_CONFERR :
temp1 = reg1 & SPI_STAT_CONFERR;
temp2 = reg2 & SPI_CTL1_ERRIE;
break;
case SPI_INT_CRCERR :
temp1 = reg1 & SPI_STAT_CRCERR;
temp2 = reg2 & SPI_CTL1_ERRIE;
break;
case I2S_INT_TXURERR :
temp1 = reg1 & SPI_STAT_TXURERR;
temp2 = reg2 & SPI_CTL1_ERRIE;
break;
case SPI_I2S_INT_FERR :
temp1 = reg1 & SPI_STAT_FERR;
temp2 = reg2 & SPI_CTL1_ERRIE;
break;
default :
break;
}
if(temp1 && temp2){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear SPI CRC error flag status
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none
\retval none
*/
void spi_crc_error_clear(uint32_t spi_periph)
{
SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
}