static SI
check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
address = fr400_check_data_read_address (current_cpu, address,
align_mask);
break;
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
case bfd_mach_frv:
address = fr500_check_data_read_address (current_cpu, address,
align_mask);
break;
case bfd_mach_fr550:
address = fr550_check_data_read_address (current_cpu, address,
align_mask);
break;
default:
break;
}
return address;
}
struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:
/* Some machines generate fp_exception for this case. */
if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
{
struct frv_fp_exception_info fp_info = {
FSR_NO_EXCEPTION, FTT_SEQUENCE_ERROR
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:
/* Some machines generate fp_exception or mp_exception for this case. */
if (frv_is_float_insn (insn))
{
struct frv_fp_exception_info fp_info = {
FSR_NO_EXCEPTION, FTT_UNIMPLEMENTED_FPOP
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
if (frv_is_media_insn (insn))
{
frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
0);
return NULL; /* no interrupt queued at this time. */
}
break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
void
frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
{
FRV_CACHE *cache;
/* Check for access errors. */
address = check_write_address (current_cpu, address, 7);
address = check_readwrite_address (current_cpu, address, 7);
/* If we need to count cycles, then submit the write request to the cache
and let it prioritize the request. Otherwise perform the write now. */
value = H2T_8 (value);
cache = CPU_DATA_CACHE (current_cpu);
if (model_insn)
{
int slot = UNIT_I0;
frv_cache_request_store (cache, address, slot,
(char *)&value, sizeof (value));
}
else
{
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
{
mem_set_unaligned_DI (current_cpu, pc, address, value);
return;
}
}
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
}
void
sim_board_reset (SIM_DESC sd)
{
struct hw *hw_cpu;
sim_cpu *cpu;
const struct bfd_arch_info *arch;
const char *cpu_type;
cpu = STATE_CPU (sd, 0);
arch = STATE_ARCHITECTURE (sd);
/* hw_cpu = sim_hw_parse (sd, "/"); */
if (arch->arch == bfd_arch_m68hc11)
{
cpu->cpu_type = CPU_M6811;
cpu_type = "/m68hc11";
}
else
{
cpu->cpu_type = CPU_M6812;
cpu_type = "/m68hc12";
}
hw_cpu = sim_hw_parse (sd, cpu_type);
if (hw_cpu == 0)
{
sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
return;
}
cpu_reset (cpu);
hw_port_event (hw_cpu, 3, 0);
cpu_restart (cpu);
}
/* Determine whether the given address is RAM access, assuming that HSR0.RME
is set. */
static int
ram_access (FRV_CACHE *cache, USI address)
{
int ihsr8;
int cwe;
USI start, end, way_size;
SIM_CPU *current_cpu = cache->cpu;
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr550:
/* IHSR8.DCWE or IHSR8.ICWE deternines which ways get RAM access. */
ihsr8 = GET_IHSR8 ();
if (cache == CPU_INSN_CACHE (current_cpu))
{
start = 0xfe000000;
end = 0xfe008000;
cwe = GET_IHSR8_ICWE (ihsr8);
}
else
{
start = 0xfe400000;
end = 0xfe408000;
cwe = GET_IHSR8_DCWE (ihsr8);
}
way_size = (end - start) / 4;
end -= way_size * cwe;
return address >= start && address < end;
default:
break;
}
return 1; /* RAM access */
}
/* Reset the cache configuration based on registers in the cpu. */
void
frv_cache_reconfigure (SIM_CPU *current_cpu, FRV_CACHE *cache)
{
int ihsr8;
int icdm;
SIM_DESC sd;
/* Set defaults for fields which are not initialized. */
sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr550:
if (cache == CPU_INSN_CACHE (current_cpu))
{
ihsr8 = GET_IHSR8 ();
icdm = GET_IHSR8_ICDM (ihsr8);
/* If IHSR8.ICDM is set, then the cache becomes a one way cache. */
if (icdm)
{
cache->sets = cache->sets * cache->ways;
cache->ways = 1;
break;
}
}
/* fall through */
default:
/* Set the cache to its original settings. */
cache->sets = cache->configured_sets;
cache->ways = cache->configured_ways;
break;
}
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
char *mm_cmd = "memory-map";
char *int_cmd = "interrupt";
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
/* Commands available from GDB: */
if (sim_args_command (sd, cmd) != SIM_RC_OK)
{
if (strncmp (cmd, "info", sizeof ("info") - 1) == 0)
sim_get_info (sd, &cmd[4]);
else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
sim_io_eprintf (sd,
"`memory-map' command replaced by `sim memory'\n");
else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
else
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
}
/* If the architecture changed, re-configure. */
if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
sim_hw_configure (sd);
}
void
frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
unsigned int map, int nr_bytes, address_word addr,
transfer_type transfer, sim_core_signals sig)
{
if (sig == sim_core_unaligned_signal)
{
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
frv_queue_data_access_error_interrupt (current_cpu, addr);
else
frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr);
}
frv_term (sd);
sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig);
}
static SIM_RC
sim_model_init (SIM_DESC sd)
{
SIM_CPU *cpu;
/* If both cpu model and state architecture are set, ensure they're
compatible. If only one is set, set the other. If neither are set,
use the default model. STATE_ARCHITECTURE is the bfd_arch_info data
for the selected "mach" (bfd terminology). */
/* Only check cpu 0. STATE_ARCHITECTURE is for that one only. */
/* ??? At present this only supports homogeneous multiprocessors. */
cpu = STATE_CPU (sd, 0);
if (! STATE_ARCHITECTURE (sd)
&& ! CPU_MACH (cpu))
{
/* Set the default model. */
const MODEL *model = sim_model_lookup (WITH_DEFAULT_MODEL);
sim_model_set (sd, NULL, model);
}
if (STATE_ARCHITECTURE (sd)
&& CPU_MACH (cpu))
{
if (strcmp (STATE_ARCHITECTURE (sd)->printable_name,
MACH_BFD_NAME (CPU_MACH (cpu))) != 0)
{
sim_io_eprintf (sd, "invalid model `%s' for `%s'\n",
MODEL_NAME (CPU_MODEL (cpu)),
STATE_ARCHITECTURE (sd)->printable_name);
return SIM_RC_FAIL;
}
}
else if (STATE_ARCHITECTURE (sd))
{
/* Use the default model for the selected machine.
The default model is the first one in the list. */
const MACH *mach = sim_mach_lookup_bfd_name (STATE_ARCHITECTURE (sd)->printable_name);
if (mach == NULL)
{
sim_io_eprintf (sd, "unsupported machine `%s'\n",
STATE_ARCHITECTURE (sd)->printable_name);
return SIM_RC_FAIL;
}
sim_model_set (sd, NULL, MACH_MODELS (mach));
}
else
{
STATE_ARCHITECTURE (sd) = bfd_scan_arch (MACH_BFD_NAME (CPU_MACH (cpu)));
}
return SIM_RC_OK;
}
/* Record state for media exception. */
void
frv_set_mp_exception_registers (
SIM_CPU *current_cpu, enum frv_msr_mtt mtt, int sie
)
{
/* Record the interrupt factor in MSR0. */
SI msr0 = GET_MSR (0);
if (GET_MSR_MTT (msr0) == MTT_NONE)
SET_MSR_MTT (msr0, mtt);
/* Also set the OVF bit in the appropriate MSR as well as MSR0.AOVF. */
if (mtt == MTT_OVERFLOW)
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
SIM_DESC sd = CPU_STATE (current_cpu);
/* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
otherwise set MSR0.OVF and MSR0.SIE. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550 && (*vliw->current_vliw)[slot] == UNIT_FM1)
{
SI msr = GET_MSR (1);
OR_MSR_SIE (msr, sie);
SET_MSR_OVF (msr);
SET_MSR (1, msr);
}
else
{
OR_MSR_SIE (msr0, sie);
SET_MSR_OVF (msr0);
}
/* Generate the interrupt now if MSR0.MPEM is set on fr550 */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550 && GET_MSR_MPEM (msr0))
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
else
{
/* Regardless of the slot, set MSR0.AOVF. */
SET_MSR_AOVF (msr0);
}
}
SET_MSR (0, msr0);
}
/* Handle the MTRAP insn. */
void
frv_mtrap (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* Check the status of media exceptions in MSR0. */
SI msr = GET_MSR (0);
if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
}
struct frv_interrupt_queue_element *
frv_queue_media_disabled_interrupt (SIM_CPU *current_cpu)
{
/* The fr550 has no mp_disabled interrupt. It uses illegal_instruction. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
}
struct frv_interrupt_queue_element *
frv_queue_privileged_instruction_interrupt (SIM_CPU *current_cpu, const CGEN_INSN *insn)
{
/* The fr550 has no privileged instruction interrupt. It uses
illegal_instruction. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
}
void
frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
{
/* Only applicable to fr550 */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
/* Adress must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}
/* Find the next available ESR and return its index */
static int
esr_for_data_access_exception (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return 8; /* Use ESR8, EPCR8. */
if (item->slot == UNIT_I0)
return 8; /* Use ESR8, EPCR8, EAR8, EDR8. */
return 9; /* Use ESR9, EPCR9, EAR9. */
}
/* Set FSR0, FQ0-FQ9, depending on the interrupt. */
static void
set_fp_exception_registers (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
int fq_index;
SI fq;
SI insn;
SI fsr0;
IADDR pc;
struct frv_fp_exception_info *fp_info;
SIM_DESC sd = CPU_STATE (current_cpu);
/* No FQ registers on fr550 */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
/* Update the fsr. */
fp_info = & item->u.fp_info;
fsr0 = GET_FSR (0);
SET_FSR_FTT (fsr0, fp_info->ftt);
SET_FSR (0, fsr0);
return;
}
/* Select an FQ and update it with the exception information. */
fq_index = fq_for_exception (current_cpu, item);
if (fq_index == -1)
return;
fp_info = & item->u.fp_info;
fq = GET_FQ (fq_index);
SET_FQ_MIV (fq, MIV_FLOAT);
SET_FQ_SIE (fq, SIE_NIL);
SET_FQ_FTT (fq, fp_info->ftt);
SET_FQ_CEXC (fq, fp_info->fsr_mask);
SET_FQ_VALID (fq);
SET_FQ (fq_index, fq);
/* Write the failing insn into FQx.OPC. */
pc = item->vpc;
insn = GETMEMSI (current_cpu, pc, pc);
SET_FQ_OPC (fq_index, insn);
/* Update the fsr. */
fsr0 = GET_FSR (0);
SET_FSR_QNE (fsr0); /* FQ not empty */
SET_FSR_FTT (fsr0, fp_info->ftt);
SET_FSR (0, fsr0);
}
/* Determine whether the given address should be accessed without using
the cache. */
static int
non_cache_access (FRV_CACHE *cache, USI address)
{
int hsr0;
SIM_DESC sd;
SIM_CPU *current_cpu = cache->cpu;
sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */
break;
case bfd_mach_fr550:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
return 1; /* non-cache access */
if (cache == CPU_INSN_CACHE (current_cpu))
{
if (address >= 0xfe000000 && address <= 0xfe007fff)
return 1; /* non-cache access */
}
else if (address >= 0xfe400000 && address <= 0xfe407fff)
return 1; /* non-cache access */
break;
default:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
return 1; /* non-cache access */
if (cache == CPU_INSN_CACHE (current_cpu))
{
if (address >= 0xfe000000 && address <= 0xfe003fff)
return 1; /* non-cache access */
}
else if (address >= 0xfe400000 && address <= 0xfe403fff)
return 1; /* non-cache access */
break;
}
hsr0 = GET_HSR0 ();
if (GET_HSR0_RME (hsr0))
return ram_access (cache, address);
return 0; /* cache-access */
}
/* Give some information about the simulator. */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
{
int i;
struct hw *hw_dev;
struct sim_info_list *dev_list;
const struct bfd_arch_info *arch;
arch = STATE_ARCHITECTURE (sd);
cmd++;
if (arch->arch == bfd_arch_m68hc11)
dev_list = dev_list_68hc11;
else
dev_list = dev_list_68hc12;
for (i = 0; dev_list[i].name; i++)
if (strcmp (cmd, dev_list[i].name) == 0)
break;
if (dev_list[i].name == 0)
{
sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
return;
}
hw_dev = sim_hw_parse (sd, dev_list[i].device);
if (hw_dev == 0)
{
sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
return;
}
hw_ioctl (hw_dev, 23, 0);
return;
}
cpu_info (sd, cpu);
interrupts_info (sd, &cpu->cpu_interrupts);
}
SIM_RC
sim_create_inferior (SIM_DESC sd,
struct bfd *prog_bfd,
char **argv,
char **env)
{
memset (&State, 0, sizeof (State));
if (prog_bfd != NULL) {
PC = bfd_get_start_address (prog_bfd);
} else {
PC = 0;
}
CPU_PC_SET (STATE_CPU (sd, 0), (unsigned64) PC);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
PSW |= PSW_FE;
return SIM_RC_OK;
}
/* Record state for media exception: media_register_not_aligned. */
void
frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* See comment in frvbf_cr_not_aligned(). */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
default:
frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
break;
}
}
void
sim_info (SIM_DESC sd, int verbose)
{
const char *cpu_type;
const struct bfd_arch_info *arch;
/* Nothing to do if there is no verbose flag set. */
if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
return;
arch = STATE_ARCHITECTURE (sd);
if (arch->arch == bfd_arch_m68hc11)
cpu_type = "68HC11";
else
cpu_type = "68HC12";
sim_io_eprintf (sd, "Simulator info:\n");
sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
sim_get_info (sd, 0);
sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}
UHI
frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
USI hsr0;
FRV_CACHE *cache;
/* Check for access exceptions. */
address = check_data_read_address (current_cpu, address, 1);
address = check_readwrite_address (current_cpu, address, 1);
/* If we need to count cycles, then the cache operation will be
initiated from the model profiling functions.
See frvbf_model_.... */
hsr0 = GET_HSR0 ();
cache = CPU_DATA_CACHE (current_cpu);
if (model_insn)
{
CPU_LOAD_ADDRESS (current_cpu) = address;
CPU_LOAD_LENGTH (current_cpu) = 2;
CPU_LOAD_SIGNED (current_cpu) = 0;
return 0xb711; /* any random value */
}
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
return read_mem_unaligned_HI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
}
return GETMEMUHI (current_cpu, pc, address);
}
/* Record state for media exception: media_cr_not_aligned. */
void
frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Note: there is a discrepancy between V2.2 of the FR400
instruction manual and the various FR4xx LSI specs. The former
claims that unaligned registers cause an mp_exception while the
latter say it's an illegal_instruction. The LSI specs appear
to be correct since MTT is fixed at 1. */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
default:
frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
break;
}
}
static SIM_RC
standard_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
int i,n;
switch ((STANDARD_OPTIONS) opt)
{
case OPTION_VERBOSE:
STATE_VERBOSE_P (sd) = 1;
break;
#ifdef SIM_HAVE_BIENDIAN
case OPTION_ENDIAN:
if (strcmp (arg, "big") == 0)
{
if (WITH_TARGET_BYTE_ORDER == LITTLE_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for little endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = BIG_ENDIAN;
}
else if (strcmp (arg, "little") == 0)
{
if (WITH_TARGET_BYTE_ORDER == BIG_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for big endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = LITTLE_ENDIAN;
}
else
{
sim_io_eprintf (sd, "Invalid endian specification `%s'\n", arg);
return SIM_RC_FAIL;
}
break;
#endif
case OPTION_ENVIRONMENT:
if (strcmp (arg, "user") == 0)
STATE_ENVIRONMENT (sd) = USER_ENVIRONMENT;
else if (strcmp (arg, "virtual") == 0)
STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
else if (strcmp (arg, "operating") == 0)
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
else
{
sim_io_eprintf (sd, "Invalid environment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
if (WITH_ENVIRONMENT != ALL_ENVIRONMENT
&& WITH_ENVIRONMENT != STATE_ENVIRONMENT (sd))
{
char *type;
switch (WITH_ENVIRONMENT)
{
case USER_ENVIRONMENT: type = "user"; break;
case VIRTUAL_ENVIRONMENT: type = "virtual"; break;
case OPERATING_ENVIRONMENT: type = "operating"; break;
}
sim_io_eprintf (sd, "Simulator compiled for the %s environment only.\n",
type);
return SIM_RC_FAIL;
}
break;
case OPTION_ALIGNMENT:
if (strcmp (arg, "strict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == STRICT_ALIGNMENT)
{
current_alignment = STRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "nonstrict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == NONSTRICT_ALIGNMENT)
{
current_alignment = NONSTRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "forced") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == FORCED_ALIGNMENT)
{
current_alignment = FORCED_ALIGNMENT;
break;
}
}
else
{
sim_io_eprintf (sd, "Invalid alignment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
switch (WITH_ALIGNMENT)
{
case STRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for strict alignment only.\n");
break;
case NONSTRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for nonstrict alignment only.\n");
break;
case FORCED_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for forced alignment only.\n");
break;
}
return SIM_RC_FAIL;
case OPTION_DEBUG:
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `-D' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
for (i = 0; i < MAX_DEBUG_VALUES; ++i)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[i] = 1;
}
break;
case OPTION_DEBUG_INSN :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-insn' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[DEBUG_INSN_IDX] = 1;
}
break;
case OPTION_DEBUG_FILE :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-file' ignored\n");
else
{
FILE *f = fopen (arg, "w");
if (f == NULL)
{
sim_io_eprintf (sd, "Unable to open debug output file `%s'\n", arg);
return SIM_RC_FAIL;
}
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FILE (STATE_CPU (sd, n)) = f;
}
break;
#ifdef SIM_H8300 /* FIXME: Can be moved to h8300 dir. */
case OPTION_H8300:
set_h8300h (1,0);
break;
case OPTION_H8300S:
set_h8300h (1,1);
break;
#endif
#ifdef SIM_HAVE_FLATMEM
case OPTION_MEM_SIZE:
{
unsigned long ul = strtol (arg, NULL, 0);
/* 16384: some minimal amount */
if (! isdigit (arg[0]) || ul < 16384)
{
sim_io_eprintf (sd, "Invalid memory size `%s'", arg);
return SIM_RC_FAIL;
}
STATE_MEM_SIZE (sd) = ul;
}
break;
#endif
case OPTION_DO_COMMAND:
sim_do_command (sd, arg);
break;
case OPTION_ARCHITECTURE:
{
const struct bfd_arch_info *ap = bfd_scan_arch (arg);
if (ap == NULL)
{
sim_io_eprintf (sd, "Architecture `%s' unknown\n", arg);
return SIM_RC_FAIL;
}
STATE_ARCHITECTURE (sd) = ap;
break;
}
case OPTION_ARCHITECTURE_INFO:
{
const char **list = bfd_arch_list();
const char **lp;
if (list == NULL)
abort ();
sim_io_printf (sd, "Possible architectures:");
for (lp = list; *lp != NULL; lp++)
sim_io_printf (sd, " %s", *lp);
sim_io_printf (sd, "\n");
free (list);
break;
}
case OPTION_TARGET:
{
STATE_TARGET (sd) = xstrdup (arg);
break;
}
case OPTION_LOAD_LMA:
{
STATE_LOAD_AT_LMA_P (sd) = 1;
break;
}
case OPTION_LOAD_VMA:
{
STATE_LOAD_AT_LMA_P (sd) = 0;
break;
}
case OPTION_HELP:
sim_print_help (sd, is_command);
if (STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE)
exit (0);
/* FIXME: 'twould be nice to do something similar if gdb. */
break;
}
return SIM_RC_OK;
}
static void
bfin_user_init (SIM_DESC sd, SIM_CPU *cpu, struct bfd *abfd,
const char * const *argv, const char * const *env)
{
/* XXX: Missing host -> target endian ... */
/* Linux starts the user app with the stack:
argc
argv[0] -- pointers to the actual strings
argv[1..N]
NULL
env[0]
env[1..N]
NULL
auxvt[0].type -- ELF Auxiliary Vector Table
auxvt[0].value
auxvt[1..N]
AT_NULL
0
argv[0..N][0..M] -- actual argv/env strings
env[0..N][0..M]
FDPIC loadmaps -- for FDPIC apps
So set things up the same way. */
int i, argc, envc;
bu32 argv_flat, env_flat;
bu32 sp, sp_flat;
/* start, at_phdr, at_phnum, at_base, at_entry, pt_dynamic */
bu32 elf_addrs[6];
bu32 auxvt;
bu32 exec_loadmap, ldso_loadmap;
char *ldso_path;
unsigned char null[4] = { 0, 0, 0, 0 };
host_callback *cb = STATE_CALLBACK (sd);
elf_addrs[0] = elf_addrs[4] = bfd_get_start_address (abfd);
elf_addrs[1] = elf_addrs[2] = elf_addrs[3] = elf_addrs[5] = 0;
/* Keep the load addresses consistent between runs. Also make sure we make
space for the fixed code region (part of the Blackfin Linux ABI). */
fdpic_load_offset = 0x1000;
/* First try to load this as an FDPIC executable. */
sp = SPREG;
if (!bfin_fdpic_load (sd, cpu, STATE_PROG_BFD (sd), &sp, elf_addrs, &ldso_path))
goto skip_fdpic_init;
exec_loadmap = sp;
/* If that worked, then load the fixed code region. We only do this for
FDPIC ELFs atm because they are PIEs and let us relocate them without
manual fixups. FLAT files however require location processing which
we do not do ourselves, and they link with a VMA of 0. */
sim_write (sd, 0x400, bfin_linux_fixed_code, sizeof (bfin_linux_fixed_code));
/* If the FDPIC needs an interpreter, then load it up too. */
if (ldso_path)
{
const char *ldso_full_path = concat (simulator_sysroot, ldso_path, NULL);
struct bfd *ldso_bfd;
ldso_bfd = bfd_openr (ldso_full_path, STATE_TARGET (sd));
if (!ldso_bfd)
{
sim_io_eprintf (sd, "bfin-sim: bfd open failed: %s\n", ldso_full_path);
goto static_fdpic;
}
if (!bfd_check_format (ldso_bfd, bfd_object))
sim_io_eprintf (sd, "bfin-sim: bfd format not valid: %s\n", ldso_full_path);
bfd_set_arch_info (ldso_bfd, STATE_ARCHITECTURE (sd));
if (!bfin_fdpic_load (sd, cpu, ldso_bfd, &sp, elf_addrs, &ldso_path))
sim_io_eprintf (sd, "bfin-sim: FDPIC ldso failed to load: %s\n", ldso_full_path);
if (ldso_path)
sim_io_eprintf (sd, "bfin-sim: FDPIC ldso (%s) needs an interpreter (%s) !?\n",
ldso_full_path, ldso_path);
ldso_loadmap = sp;
}
else
static_fdpic:
ldso_loadmap = 0;
/* Finally setup the registers required by the FDPIC ABI. */
SET_DREG (7, 0); /* Zero out FINI funcptr -- ldso will set this up. */
SET_PREG (0, exec_loadmap); /* Exec loadmap addr. */
SET_PREG (1, ldso_loadmap); /* Interp loadmap addr. */
SET_PREG (2, elf_addrs[5]); /* PT_DYNAMIC map addr. */
auxvt = 1;
SET_SPREG (sp);
skip_fdpic_init:
sim_pc_set (cpu, elf_addrs[0]);
/* Figure out how much storage the argv/env strings need. */
argc = count_argc (argv);
if (argc == -1)
argc = 0;
argv_flat = argc; /* NUL bytes */
for (i = 0; i < argc; ++i)
argv_flat += strlen (argv[i]);
if (!env)
env = simple_env;
envc = count_argc (env);
env_flat = envc; /* NUL bytes */
for (i = 0; i < envc; ++i)
env_flat += strlen (env[i]);
/* Push the Auxiliary Vector Table between argv/env and actual strings. */
sp_flat = sp = ALIGN (SPREG - argv_flat - env_flat - 4, 4);
if (auxvt)
{
# define AT_PUSH(at, val) \
auxvt_size += 8; \
sp -= 4; \
auxvt = (val); \
sim_write (sd, sp, (void *)&auxvt, 4); \
sp -= 4; \
auxvt = (at); \
sim_write (sd, sp, (void *)&auxvt, 4)
unsigned int egid = getegid (), gid = getgid ();
unsigned int euid = geteuid (), uid = getuid ();
bu32 auxvt_size = 0;
AT_PUSH (AT_NULL, 0);
AT_PUSH (AT_SECURE, egid != gid || euid != uid);
AT_PUSH (AT_EGID, egid);
AT_PUSH (AT_GID, gid);
AT_PUSH (AT_EUID, euid);
AT_PUSH (AT_UID, uid);
AT_PUSH (AT_ENTRY, elf_addrs[4]);
AT_PUSH (AT_FLAGS, 0);
AT_PUSH (AT_BASE, elf_addrs[3]);
AT_PUSH (AT_PHNUM, elf_addrs[2]);
AT_PUSH (AT_PHENT, sizeof (Elf32_External_Phdr));
AT_PUSH (AT_PHDR, elf_addrs[1]);
AT_PUSH (AT_CLKTCK, 100); /* XXX: This ever not 100 ? */
AT_PUSH (AT_PAGESZ, 4096);
AT_PUSH (AT_HWCAP, 0);
#undef AT_PUSH
}
SET_SPREG (sp);
/* Push the argc/argv/env after the auxvt. */
sp -= ((1 + argc + 1 + envc + 1) * 4);
SET_SPREG (sp);
/* First push the argc value. */
sim_write (sd, sp, (void *)&argc, 4);
sp += 4;
/* Then the actual argv strings so we know where to point argv[]. */
for (i = 0; i < argc; ++i)
{
unsigned len = strlen (argv[i]) + 1;
sim_write (sd, sp_flat, (void *)argv[i], len);
sim_write (sd, sp, (void *)&sp_flat, 4);
sp_flat += len;
sp += 4;
}
sim_write (sd, sp, null, 4);
sp += 4;
/* Then the actual env strings so we know where to point env[]. */
for (i = 0; i < envc; ++i)
{
unsigned len = strlen (env[i]) + 1;
sim_write (sd, sp_flat, (void *)env[i], len);
sim_write (sd, sp, (void *)&sp_flat, 4);
sp_flat += len;
sp += 4;
}
/* Set some callbacks. */
cb->syscall_map = cb_linux_syscall_map;
cb->errno_map = cb_linux_errno_map;
cb->open_map = cb_linux_open_map;
cb->signal_map = cb_linux_signal_map;
cb->stat_map = stat_map_32 = cb_linux_stat_map_32;
stat_map_64 = cb_linux_stat_map_64;
}
/* Set ESFR0, EPCRx, ESRx, EARx and EDRx, according to the given program
interrupt. */
static void
set_exception_status_registers (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind];
int slot = (item->vpc - previous_vliw_pc) / 4;
int reg_index = -1;
int set_ear = 0;
int set_edr = 0;
int set_daec = 0;
int set_epcr = 0;
SI esr = 0;
SIM_DESC sd = CPU_STATE (current_cpu);
/* If the interrupt is strict (precise) or the interrupt is on the insns
in the I0 pipe, then set the 0 registers. */
if (interrupt->precise)
{
reg_index = 0;
if (interrupt->kind == FRV_REGISTER_EXCEPTION)
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
/* For fr550, don't set epcr for precise interrupts. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
set_epcr = 1;
}
else
{
switch (interrupt->kind)
{
case FRV_DIVISION_EXCEPTION:
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
/* For fr550, always use ESR0. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
reg_index = 0;
else if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
reg_index = 14; /* Use ESR14. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
set_ear = 1;
break;
case FRV_DATA_ACCESS_EXCEPTION:
set_daec = 1;
/* fall through */
case FRV_DATA_ACCESS_MMU_MISS:
case FRV_MEM_ADDRESS_NOT_ALIGNED:
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
/* For fr550, never use EDRx. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
if (item->u.data_written.length != 0)
set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break;
default:
{
SIM_DESC sd = CPU_STATE (current_cpu);
IADDR pc = CPU_PC_GET (current_cpu);
sim_engine_abort (sd, current_cpu, pc,
"invalid non-strict program interrupt kind: %d\n",
interrupt->kind);
break;
}
}
} /* non-strict (imprecise) interrupt */
/* Now fill in the selected exception status registers. */
if (reg_index != -1)
{
/* Now set the exception status registers. */
SET_ESFR_FLAG (reg_index);
SET_ESR_EC (esr, interrupt->ec);
if (set_epcr)
{
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
SET_EPCR (reg_index, previous_vliw_pc);
else
SET_EPCR (reg_index, item->vpc);
}
if (set_ear)
{
SET_EAR (reg_index, item->eaddress);
SET_ESR_EAV (esr);
}
else
CLEAR_ESR_EAV (esr);
if (set_edr)
{
int edn = set_edr_register (current_cpu, item, 0/* EDR0-3 */);
SET_ESR_EDN (esr, edn);
SET_ESR_EDV (esr);
}
else
CLEAR_ESR_EDV (esr);
if (set_daec)
SET_ESR_DAEC (esr, item->u.daec);
SET_ESR_VALID (esr);
SET_ESR (reg_index, esr);
}
}
void
frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
{
int elements;
int i, j;
SIM_DESC sd;
/* Set defaults for fields which are not initialized. */
sd = CPU_STATE (cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
if (cache->configured_sets == 0)
cache->configured_sets = 512;
if (cache->configured_ways == 0)
cache->configured_ways = 2;
if (cache->line_size == 0)
cache->line_size = 32;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
case bfd_mach_fr550:
if (cache->configured_sets == 0)
cache->configured_sets = 128;
if (cache->configured_ways == 0)
cache->configured_ways = 4;
if (cache->line_size == 0)
cache->line_size = 64;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
default:
if (cache->configured_sets == 0)
cache->configured_sets = 64;
if (cache->configured_ways == 0)
cache->configured_ways = 4;
if (cache->line_size == 0)
cache->line_size = 64;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
}
frv_cache_reconfigure (cpu, cache);
/* First allocate the cache storage based on the given dimensions. */
elements = cache->sets * cache->ways;
cache->tag_storage = (FRV_CACHE_TAG *)
zalloc (elements * sizeof (*cache->tag_storage));
cache->data_storage = (char *) xmalloc (elements * cache->line_size);
/* Initialize the pipelines and status buffers. */
for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
{
cache->pipeline[i].requests = NULL;
cache->pipeline[i].status.flush.valid = 0;
cache->pipeline[i].status.return_buffer.valid = 0;
cache->pipeline[i].status.return_buffer.data
= (char *) xmalloc (cache->line_size);
for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
cache->pipeline[i].stages[j].request = NULL;
}
cache->BARS.valid = 0;
cache->NARS.valid = 0;
/* Now set the cache state. */
cache->cpu = cpu;
cache->statistics.accesses = 0;
cache->statistics.hits = 0;
}
static int
sim_hw_configure (SIM_DESC sd)
{
const struct bfd_arch_info *arch;
struct hw *device_tree;
sim_cpu *cpu;
arch = STATE_ARCHITECTURE (sd);
if (arch == 0)
return 0;
cpu = STATE_CPU (sd, 0);
cpu->cpu_configured_arch = arch;
device_tree = sim_hw_parse (sd, "/");
if (arch->arch == bfd_arch_m68hc11)
{
cpu->cpu_interpretor = cpu_interp_m6811;
if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
{
/* Allocate core managed memory */
/* the monitor */
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
/* MONITOR_BASE, MONITOR_SIZE */
0x8000, M6811_RAM_LEVEL, 0x8000);
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
M6811_RAM_LEVEL);
sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
if (cpu->bank_start < cpu->bank_end)
{
sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
cpu->bank_virtual, M6811_RAM_LEVEL);
sim_hw_parse (sd, "/m68hc11/use_bank 1");
}
}
if (cpu->cpu_start_mode)
{
sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
}
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
{
sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
}
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
{
/* M68hc11 Timer configuration. */
sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
}
/* Create the SPI device. */
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
{
sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
}
if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
{
/* M68hc11 persistent ram configuration. */
sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
/*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
}
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
{
sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
}
sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
}
else
{
cpu->cpu_interpretor = cpu_interp_m6812;
if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
{
/* Allocate core external memory. */
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
0x8000, M6811_RAM_LEVEL, 0x8000);
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
M6811_RAM_LEVEL);
if (cpu->bank_start < cpu->bank_end)
{
sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
cpu->bank_virtual, M6811_RAM_LEVEL);
sim_hw_parse (sd, "/m68hc12/use_bank 1");
}
sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
}
if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
{
sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
}
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
{
/* M68hc11 Timer configuration. */
sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
}
/* Create the SPI device. */
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
{
sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
}
if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
{
/* M68hc11 persistent ram configuration. */
sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
}
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
{
sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
}
sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
}
return 1;
}
