void send() {
// Need to flusb the 4 buffers
if(init < 4) {
init_waveform();
init++;
}
// ARM ep2 in
EP2BCH = MSB(BUFF_SIZE); SYNCDELAY();
EP2BCL = LSB(BUFF_SIZE); SYNCDELAY();
}
BOOL handle_vendorcommand(BYTE cmd)
{
WORD addr=SETUP_VALUE(),len=SETUP_LENGTH();
switch ( cmd ) {
case VC_EPSTAT:
{
xdata BYTE* pep= ep_addr(SETUPDAT[2]);
if (pep) {
EP0BUF[0] = *pep;
EP0BCH=0;
EP0BCL=1;
return TRUE;
}
}
break;
case VC_EEPROM:
{
// wait for ep0 not busy
switch (SETUP_TYPE) {
case 0xc0:
while (len) { // still have bytes to read
// can't read more than 64 bytes at a time
BYTE cur_read = len > 64 ? 64 : len;
while (EP0CS&bmEPBUSY); // can't do this until EP0 is ready
eeprom_read(0x51, addr, cur_read, EP0BUF );
EP0BCH=0;
SYNCDELAY();
EP0BCL=cur_read;
len -= cur_read;
addr += cur_read;
}
break;
case 0x40:
while (len) {
BYTE cur_write;
EP0BCL = 0; // allow pc transfer in
while(EP0CS & bmEPBUSY); // wait
cur_write=EP0BCL;
if ( !eeprom_write(0x51, addr, cur_write, EP0BUF ) ) return FALSE;
addr += cur_write;
len -= cur_write;
}
break;
default:
return FALSE; // bad type
}
printf ( "All OK\n" );
return TRUE;
}
break;
default:
{
printf ( "Need to implement vendor command: %02x\n", cmd );
return FALSE;
}
}
return FALSE;
}
static void set_output_lines_direction(void)
{
/* Populate the buffer. */
BYTE *const ols = (BYTE *)EP0BUF;
WORD wValue = MAKEWORD(SETUPDAT[3], SETUPDAT[2]);
if (wValue & 0xff) {
IOA = 0xff; // OUT, конфликта выходов нет
OEB = 0xff; // set direction port B as output
} else {
OEB = 0; // set direction port B as input
IOA = 0; //IN
}
SYNCDELAY();
ols[0] = LSB(IOA);
/* Send the message. */
EP0BCH = 0;
EP0BCL = 1;
}
BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) {
printf ( "Set interface %d to alt: %d\n" , ifc, alt_ifc );
if (ifc==0&&alt_ifc==0) {
// SEE TRM 2.3.7
// reset toggles
RESETTOGGLE(0x02);
RESETTOGGLE(0x86);
// restore endpoints to default condition
RESETFIFO(0x02);
EP2BCL=0x80;
SYNCDELAY();
EP2BCL=0X80;
SYNCDELAY();
RESETFIFO(0x86);
return TRUE;
} else
return FALSE;
}
bool start_capture()
{
/* Sample clear before each acquistion */
IOA &= 0xf7;
/* Abort currently executing GPIF waveform (if any). */
GPIFABORT = 0xff;
/* ... */
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY();
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY();
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY();
/* Ensure GPIF is idle before reconfiguration. */
while (!(GPIFTRIG & 0x80));
/* Clear the stop flag */
GPIFREADYCFG &= 0x7f;
/* Configure the EP6 FIFO. */
EP6FIFOCFG = bmAUTOIN | bmWORDWIDE;
SYNCDELAY();
/* sample clear end */
IOA |= 0x08;
/* Execute the whole GPIF waveform once. */
gpif_set_tc16(1);
/* Perform the initial GPIF read. */
gpif_fifo_read(GPIF_EP6);
/* Update the status. */
capturing = TRUE;
IOA |= 0x04;
return true;
}
static void setup_endpoints(void)
{
/* Setup EP2 (IN). */
EP2CFG = (1 << 7) | /* EP is valid/activated */
(1 << 6) | /* EP direction: IN */
(1 << 5) | (0 << 4) | /* EP Type: bulk */
(1 << 3) | /* EP buffer size: 1024 */
(0 << 2) | /* Reserved. */
(0 << 1) | (0 << 0); /* EP buffering: quad buffering */
SYNCDELAY();
/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
EP1INCFG &= ~bmVALID;
SYNCDELAY();
EP1OUTCFG &= ~bmVALID;
SYNCDELAY();
EP4CFG &= ~bmVALID;
SYNCDELAY();
EP6CFG &= ~bmVALID;
SYNCDELAY();
EP8CFG &= ~bmVALID;
SYNCDELAY();
/* EP2: Reset the FIFOs. */
/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
RESETFIFO(0x02)
/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
EP2FIFOCFG = bmAUTOIN;
SYNCDELAY();
/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
EP2AUTOINLENH = 0x02;
SYNCDELAY();
EP2AUTOINLENL = 0x00;
SYNCDELAY();
/* EP2: Set the GPIF flag to 'full'. */
EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
SYNCDELAY();
}
void configure_fifo() {
FIFOPINPOLAR = 0xFF; SYNCDELAY(); // Enable on high level
PINFLAGSAB = 0x00; SYNCDELAY(); // Don't care
PINFLAGSCD = 0x00; SYNCDELAY(); // Don't care
IFCONFIG = bmIFCLKSRC | bmASYNC; SYNCDELAY(); // External clock source, async
EP2AUTOINLENH = 0x02; SYNCDELAY();// EZ-USB automatically commits data in 512-byte chunks
EP2AUTOINLENL = 0x00; SYNCDELAY();
EP2FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY();
}
static void set_output_lines(void)
{
/* Populate the buffer. */
BYTE *const ols = (BYTE *)EP0BUF;
WORD wValue = MAKEWORD(SETUPDAT[3], SETUPDAT[2]);
IOB = LSB(wValue);
SYNCDELAY();
ols[0] = LSB(IOB);
/* Send the message. */
EP0BCH = 0;
EP0BCL = 1;
}
void reset() {
EP2CS &= ~bmBIT0; SYNCDELAY();// remove stall bit
EP6CS &= ~bmBIT0; SYNCDELAY();// remove stall bit
// Reset all the FIFOs
FIFORESET = bmNAKALL; SYNCDELAY();
FIFORESET = bmNAKALL | 2; SYNCDELAY(); // reset EP2
FIFORESET = bmNAKALL | 6; SYNCDELAY(); // reset EP6
FIFORESET = 0x00; SYNCDELAY();
EP2FIFOCFG &= ~bmBIT0; SYNCDELAY();// not worldwide
EP6FIFOCFG &= ~bmBIT0; SYNCDELAY();// not worldwide
IOA |= SIG_EN; // High at start
OEA |= SIG_EN; // OEA 3 Output
DISABLE_TIMER0();
usb_debug_disable();
}
void main() {
BOOL on=FALSE;
unsigned int size=0;
LED6 = 0;
REVCTL=0; // not using advanced endpoint controls
on=0;
lcount=0;
got_sud=FALSE;
icount=0;
gotbuf=FALSE;
bytes=0;
// renumerate
RENUMERATE_UNCOND();
SETCPUFREQ(CLK_48M);
sio0_init(57600);
USE_USB_INTS();
ENABLE_SUDAV();
ENABLE_SOF();
ENABLE_HISPEED();
ENABLE_USBRESET();
// only valid endpoints are 2/6
EP2CFG = 0xA2; // 10100010
SYNCDELAY();
EP6CFG = 0xE2; // 11100010
SYNCDELAY();
EP1INCFG &= ~bmVALID;
SYNCDELAY();
EP1OUTCFG &= ~bmVALID;
SYNCDELAY();
EP4CFG &= ~bmVALID;
SYNCDELAY();
EP8CFG &= ~bmVALID;
SYNCDELAY();
// arm ep2
EP2BCL = 0x80; // write once
SYNCDELAY();
EP2BCL = 0x80; // do it again
EA=1; // global interrupt enable
OEB |= 0x01; // set PB0 as output
LED6 = 0;
eeprom_write_local(LG_PROM, 0, IIC_SIZE, fx2_c0);
while(TRUE) {
if ( got_sud ) {
printf ( "Handle setupdata\n" );
handle_setupdata();
got_sud=FALSE;
}
if ( !(EP2468STAT & bmEP2EMPTY) ) { // EP2 received data
if ( !(EP2468STAT & bmEP6FULL) ) { // wait for at least one
// empty buffer
WORD i;
bytes = MAKEWORD(EP2BCH,EP2BCL);
for (i=0;i<bytes;++i) {
EP6FIFOBUF[i] = 0x00;
// arm ep6 out
EP6BCH=MSB(bytes);
SYNCDELAY();
EP6BCL=LSB(bytes);
REARM(); // re-arm ep2
}
}
}
//delay(40);
if (LED6) {LED6 = 0;} else {LED6 =1;}
}
}
void main() {
REVCTL=0; // not using advanced endpoint controls
d2off();
on=0;
lcount=0;
got_sud=FALSE;
icount=0;
gotbuf=FALSE;
bytes=0;
// renumerate
RENUMERATE_UNCOND();
SETCPUFREQ(CLK_48M);
SETIF48MHZ();
sio0_init(57600);
USE_USB_INTS();
ENABLE_SUDAV();
ENABLE_SOF();
ENABLE_HISPEED();
ENABLE_USBRESET();
// only valid endpoints are 2/6
EP2CFG = 0xA2; // 10100010
SYNCDELAY();
EP6CFG = 0xE2; // 11100010
SYNCDELAY();
EP1INCFG &= ~bmVALID;
SYNCDELAY();
EP1OUTCFG &= ~bmVALID;
SYNCDELAY();
EP4CFG &= ~bmVALID;
SYNCDELAY();
EP8CFG &= ~bmVALID;
SYNCDELAY();
// arm ep2
EP2BCL = 0x80; // write once
SYNCDELAY();
EP2BCL = 0x80; // do it again
// make it so we enumberate
EA=1; // global interrupt enable
printf ( "Done initializing stuff\n" );
d3off();
while(TRUE) {
if ( got_sud ) {
printf ( "Handle setupdata\n" );
handle_setupdata();
got_sud=FALSE;
}
if ( !(EP2468STAT & bmEP2EMPTY) ) {
printf ( "ep2 out received data\n" );
if ( !(EP2468STAT & bmEP6FULL) ) { // wait for at least one empty in buffer
WORD i;
printf ( "Sending data to ep6 in\n");
bytes = MAKEWORD(EP2BCH,EP2BCL);
for (i=0;i<bytes;++i) EP6FIFOBUF[i] = EP2FIFOBUF[i];
// can copy whole string w/ autoptr instead.
// or copy directly from one buf to another
// ARM ep6 out
EP6BCH=MSB(bytes);
SYNCDELAY();
EP6BCL=LSB(bytes);
REARM(); // ep2
//printf ( "Re-Armed ep2\n" );
}
}
}
}
BOOL handle_vendorcommand(BYTE cmd) {
if(cmd == 0x90) { // Reset
reset();
// Nothing to reply
EP0BCH = 0;
EP0BCL = 0;
EP0CS |= bmHSNAK;
return TRUE;
} else if(cmd == 0x91) { // Enable/Disable debug
short val = SETUP_VALUE();
if(val != 0) {
usb_debug_enable();
USB_DEBUG_PRINTF(6, "Debug enabled");
} else {
usb_debug_disable();
}
EP0BCH = 0;
EP0BCL = 0;
EP0CS |= bmHSNAK;
return TRUE;
} else if(cmd == 0x92) { // Start stream
USB_DEBUG_PRINTF(6, "Start");
IOA &= ~SIG_EN; // Low
// Nothing to reply
EP0BCH = 0;
EP0BCL = 0;
EP0CS |= bmHSNAK;
#ifdef SIMULATION
fx2_setup_timer0(29);
#else
IFCONFIG |= bmIFFIFO;
#endif
return TRUE;
} else if(cmd == 0x93) { // Stop stream
USB_DEBUG_PRINTF(6, "Stop");
IOA |= SIG_EN; // High
// Reset EP2
FIFORESET = bmNAKALL; SYNCDELAY();
FIFORESET = bmNAKALL | 2; SYNCDELAY();
FIFORESET = 0x00; SYNCDELAY();
// Nothing to reply
EP0BCH = 0;
EP0BCL = 0;
EP0CS |= bmHSNAK;
#ifdef SIMULATION
fx2_setup_timer0(0);
#else
IFCONFIG &= ~bmIFFIFO;
#endif
return TRUE;
} else if(cmd == 0x94) { // Get version
USB_PRINTF(0, "AdslSniffer V0.0.1");
EP0CS |= bmHSNAK;
return TRUE;
} else if(cmd == 0x95) { // Get bitrate
WORD size = sizeof(DWORD);
DWORD *rate = (DWORD*)EP0BUF;
*rate = 8832000;
EP0BCH = MSB(size);
EP0BCL = LSB(size);
EP0CS |= bmHSNAK;
return TRUE;
} else if(cmd == 0x99) { // Test debug EP
USB_DEBUG_PRINTF(6, "Test");
EP0BCH = 0;
EP0BCL = 0;
EP0CS |= bmHSNAK;
return TRUE;
}
return FALSE;
}
void main_init() {
REVCTL = 0x03;
SYNCDELAY();
SETIF48MHZ();
SYNCDELAY();
// Configure port
PORTACFG = 0x00; SYNCDELAY();
PORTCCFG = 0x00; SYNCDELAY();
PORTECFG = 0x00; SYNCDELAY();
// set IFCONFIG
EP1INCFG &= ~bmVALID; SYNCDELAY();
EP1OUTCFG &= ~bmVALID; SYNCDELAY();
EP2CFG = (bmVALID | bmBULK | bmBUF4X /*| bmBUF1024*/ | bmDIR); SYNCDELAY();
EP4CFG &= ~bmVALID; /* = (bmVALID | bmISO | bmBUF2X | bmDIR);*/ SYNCDELAY();
EP6CFG = (bmVALID | bmBULK | bmBUF2X | bmDIR); SYNCDELAY();
EP8CFG &= ~bmVALID; SYNCDELAY();
reset();
#ifndef SIMULATION
configure_fifo();
#endif
}