//Use this assume it passes !spiBufFull condition. so there is at least 1 space in the buf.
BOOL _spiBufAdd(uint32 slaveId, uint32 outData, uint32 *indata)
{
uint32 i;
//this area need to be protected if it is a pre-emptyive OS,
//or if we allow ISR/DSR to call. We will protect with disabling
//interrupts.
#ifdef _SPI_INTERRUPT_SAFE
TCInterruptGlobalDisable();
#endif
if(spiBufFull())
{
#ifdef _SPI_INTERRUPT_SAFE
TCInterruptGlobalRestore();
#endif
return FALSE;
}
i = spiBufTail;
spiBuf[i].ssId = slaveId;
spiBuf[i].outData = outData;
spiBuf[i].inData = indata;
spiBuf[i].bPending = FALSE;
spiBufTail = (spiBufTail+1) % SPI_MAX_BUF_SIZE;
spiSetInterrupt(SPI_TX_EMPTY | SPI_RX_FULL);
#ifdef _SPI_INTERRUPT_SAFE
TCInterruptGlobalRestore();
#endif
return TRUE;
}
void i2cIntDsr(void)
{
uint32 int_stat = MPTR(IC_INTR_STAT);
uint32 int_raw_stat = MPTR(IC_RAW_INTR_STAT);
//disable interrupt
TCInterruptGlobalDisable();
//SYS_TRACE3(SYSDEBUG_TRACE_I2C, int_stat, int_raw_stat, tempTran.status);
if((int_stat & BIT4) && ((int_raw_stat & BIT8) == 0)) { // TX empty and no activity
switch(tempTran.status) {
int i;
case 2:
//we are guranteed to have enough buf
for(i = 0; i < tempTran.length; i++) {
switch (tempTran.type) {
case 0:
_i2cIntWriteCmd(0x100);
break;
case 1:
_i2cIntWriteCmd(tempTran.data[tempTran.cur_pos]);
tempTran.cur_pos++;
break;
}
}
tempTran.status++;
break;
case 3:
MPTR(IC_INTR_MASK) &= ~BIT4; //clear TX empty interrupt
if(tempTran.type == 1) {
resetTran(&tempTran);
MPTR(IC_INTR_MASK) = 0;
//SYS_TRACE0(SYSDEBUG_TRACE_I2C);
TCSemaphoreSignal(i2cCompleteSemId);
}
break;
default:
break;
}
}
if(int_stat & BIT2) { // Rx not empty
//while(MPTR(IC_STATUS) & BIT3) {//rx not
while(MPTR(IC_RXFLR) != 0) {//rx not empty
tempTran.data[tempTran.cur_pos] = MPTR(IC_DATA_CMD);
tempTran.cur_pos++;
}
if(tempTran.cur_pos >= tempTran.length) {
resetTran(&tempTran);
MPTR(IC_INTR_MASK) = 0;
//SYS_TRACE1(SYSDEBUG_TRACE_I2C, tempTran.cur_pos);
TCSemaphoreSignal(i2cCompleteSemId);
}
}
if(int_stat & BIT6) { //Tx Error
i2c_tx_err_counter++;
i2c_last_tx_error = MPTR(IC_TX_ABRT_SOURCE);
resetTran(&tempTran);
MPTR(IC_INTR_MASK) = 0;
//SYS_TRACE2(SYSDEBUG_TRACE_I2C, i2c_last_tx_error, i2c_tx_err_counter);
TCSemaphoreSignal(i2cCompleteSemId);
}
_i2cClearIntr();
TCInterruptGlobalRestore();
}
static HRESULT context1PostPacket(PB * pPacket,uint32 semID)
{
HRESULT hResult = NO_ERROR;
//check if context is available, should be as we only have one thread using the context
volatile POSTED_TX_CONTEXT * pContext = &postedTxState.contexts[1];
if (pContext->bPosted)
{
hResult = E_LAL_RESPONSE_UNEXPECTED;
sysLogError(hResult, __LINE__, moduleName);
return hResult;
}
PB_HEADER* pHeader = 0;
uint32 speedCode = 0;
#ifdef _LOOSE_ISO
uint8 asyncStream = FALSE;
#endif //_LOOSE_ISO
// ML 140610: Busreset storm fix. Let's skip if we ar ein bus reset
if (postedTxState.inBr)
{
hResult = E_LAL_BUS_RESET_IN_PROGRESS;
sysLogError(hResult, __LINE__, moduleName);
return hResult;
}
pbGetPacketHeader(pPacket, &pHeader);
pbGetPacketSpeed(pPacket, &speedCode);
PB_PACKETTYPE packetType;
pbGetPacketType(pPacket, &packetType);
pContext->header.quadlets[0] = (pHeader->quadlets[0] & 0x0000ffff); // 0:spd,tag,ch,tcode,sy
pContext->header.quadlets[0]|= speedCode;
#ifdef _LOOSE_ISO
pbIsAsyncStreamPacket (pPacket, &asyncStream);
if (asyncStream == TRUE)
{
pContext->header.quadlets[1] = (pHeader->quadlets[1] & 0xffff0000); // 1:data_length,reserved
}
else
#endif //_LOOSE_ISO
if (packetType == TCODE_PHY_PACKET)
{
pContext->header.quadlets[0] = ((uint32)TCODE_LLC_SPECIFIC) << SHIFT_TCODE;
pContext->header.quadlets[1] = pHeader->quadlets[0];
pContext->header.quadlets[2] = ~pHeader->quadlets[0];
}
else
{
pContext->header.quadlets[0] |= LLC_SOURCEID_NODEID;
pContext->header.quadlets[1] = (pHeader->quadlets[0] & 0xffff0000); // 1:dstId,destination_offsetHigh
pContext->header.quadlets[1] |= (pHeader->quadlets[1] & 0x0000ffff);
pContext->header.quadlets[2] = pHeader->quadlets[2]; // 2:destination_offsetLow
pContext->header.quadlets[3] = pHeader->quadlets[3]; // 3:data_length,extended_tcode
}
hResult = lhlGetHeaderQuadSizeFromTCode(LHL_TX, packetType, (uint16 *)&pContext->headerLen);
if (hResult != NO_ERROR) return hResult;
uint32 payloadNumBytes=0;
pbGetPayload(pPacket, (void **)&pContext->pPayload);
pbGetPayloadSize(pPacket, &payloadNumBytes);
//Ugly, the payload is not always refering to the outgoing packet.
if ((packetType==PB_TYPE_READ_REQUEST) || (packetType==PB_TYPE_READ_REQUEST_QUADLET) ||(packetType==PB_TYPE_WRITE_RESPONSE) || (packetType==TCODE_PHY_PACKET))
payloadNumBytes=0;
//Another hack as the read resp payload should always be one quadlet even in case of error
if (packetType==PB_TYPE_READ_RESPONSE_QUADLET)
payloadNumBytes=4;
pContext->payloadLen = (payloadNumBytes+3)>>2;
// ML 140610: Busreset storm fix. There is potentially a race condition here if
// Isr or Dsr comes here. Fixed with interrupt disable.
TCInterruptGlobalDisable();
if (postedTxState.inBr)
{
TCInterruptGlobalEnable();
hResult = E_LAL_BUS_RESET_IN_PROGRESS;
sysLogError(hResult, __LINE__, moduleName);
return hResult;
}
pContext->semID = semID;
pContext->bPosted = TRUE;
fSYS_TRACE1(SYSDEBUG_TRACE_TESTS,0);
llcLinkRegWrite(INTERRUPT_REG_SET_DP, LLC_INT_BIT(LLCID_ASY_TX_CMPL));
TCInterruptGlobalEnable();
return hResult;
}
