__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL);
lcdc_clk_on(sel);
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if(gpanel_info[sel].tcon_index == 0)
{
TCON0_cfg(sel,(__panel_para_t*)&gpanel_info[sel]);
}
else
{
TCON1_cfg_ex(sel,(__panel_para_t*)&gpanel_info[sel]);
}
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD);
DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y);
DE_BE_Output_Select(sel, sel);
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL);
lcdc_clk_on(sel);
image_clk_on(sel);
/*
* set image normal channel start bit, because every de_clk_off( )
* will reset this bit
*/
Image_open(sel);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if (gpanel_info[sel].tcon_index == 0)
TCON0_cfg(sel, (__panel_para_t *) &gpanel_info[sel]);
else
TCON1_cfg_ex(sel, (__panel_para_t *) &gpanel_info[sel]);
#ifdef CONFIG_ARCH_SUN4I
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD);
#else
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD,
gdisp.screen[sel].iep_status & DRC_USED);
#endif
DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x,
gpanel_info[sel].lcd_y);
DE_BE_Output_Select(sel, sel);
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0);
lcdc_clk_on(sel);
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if(gpanel_info[sel].tcon_index == 0)
{
TCON0_cfg(sel,(__ebios_panel_para_t*)&gpanel_info[sel]);
}
else
{
TCON1_cfg_ex(sel,(__ebios_panel_para_t*)&gpanel_info[sel]);
}
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}