void vInitialiseTimerForIntQueueTest( void )
{
const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;
/* Enable the TC clocks. */
PMC->PMC_PCER0 = 1 << ID_TC0;
PMC->PMC_PCER0 = 1 << ID_TC1;
/* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger
on RC compare. */
TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_0_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger
on RC compare. */
TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = BOARD_MCK / ( tmrTIMER_1_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;
/* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on
RC compare. */
TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_2_FREQUENCY * ulDivider );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* Enable interrupts and start the timers. */
IRQ_ConfigureIT( ID_TC0, tmrLOWER_PRIORITY, prvTC0_Handler );
IRQ_ConfigureIT( ID_TC1, tmrHIGHER_PRIORITY, prvTC1_Handler );
IRQ_EnableIT( ID_TC0 );
IRQ_EnableIT( ID_TC1 );
TC_Start( TC0, tmrTC0_CHANNEL_0 );
TC_Start( TC0, tmrTC0_CHANNEL_1 );
TC_Start( TC1, tmrTC1_CHANNEL_0 );
}
void vInitialiseTimerForIntQueueTest( void )
{
const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;
/* Enable the TC clocks. */
PMC_EnablePeripheral( ID_TC0 );
PMC_EnablePeripheral( ID_TC1 );
/* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger
on RC compare. This is part of the IntQTimer test. */
TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( BOARD_MCK / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger
on RC compare. This is part of the IntQTimer test. */
TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( BOARD_MCK / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;
/* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on
RC compare. This is the very high frequency timer. */
TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_2_FREQUENCY * ulDivider );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* First setup TC0 interrupt, in which two channels are used. */
AIC->AIC_SSR = ID_TC0;
/* Ensure the interrupt is disabled before setting mode and handler. */
AIC->AIC_IDCR = AIC_IDCR_INTD;
AIC->AIC_SMR = AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE | tmrLOWER_PRIORITY;
AIC->AIC_SVR = ( uint32_t ) prvTC0_Handler;
/* Start with the interrupt clear. */
AIC->AIC_ICCR = AIC_ICCR_INTCLR;
/* Do the same for TC1 - which is the high frequency timer. */
AIC->AIC_SSR = ID_TC1;
AIC->AIC_IDCR = AIC_IDCR_INTD;
AIC->AIC_SMR = AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE | tmrHIGHER_PRIORITY;
AIC->AIC_SVR = ( uint32_t ) prvTC1_Handler;
AIC->AIC_ICCR = AIC_ICCR_INTCLR;
/* Finally enable the interrupts and start the timers. */
AIC_EnableIT( ID_TC0 );
AIC_EnableIT( ID_TC1 );
TC_Start( TC0, tmrTC0_CHANNEL_0 );
TC_Start( TC0, tmrTC0_CHANNEL_1 );
TC_Start( TC1, tmrTC1_CHANNEL_0 );
}
/**
* \brief usart-hard-handshaking Application entry point..
*
* Configures USART0 in hardware handshaking mode and
* Timer Counter 0 to generate an interrupt every second. Then, starts the first
* transfer on the USART and wait in an endless loop.
*
* \return Unused (ANSI-C compatibility).
* \callgraph
*/
extern int main( void )
{
/* Disable watchdog*/
WDT_Disable( WDT ) ;
/* Configure pins*/
PIO_Configure( pins, PIO_LISTSIZE( pins ) ) ;
/* Configure USART and display startup trace*/
_ConfigureUsart() ;
printf( "-- USART Hardware Handshaking Example %s --\n\r", SOFTPACK_VERSION ) ;
printf( "-- %s\n\r", BOARD_NAME ) ;
printf( "-- Compiled: %s %s --\n\r", __DATE__, __TIME__ ) ;
/* Configure TC0 to generate a 1s tick*/
_ConfigureTc0() ;
/* Start receiving data and start timer*/
USART_ReadBuffer( BOARD_USART_BASE, pBuffer, BUFFER_SIZE ) ;
BOARD_USART_BASE->US_IER = US_IER_RXBUFF ;
TC_Start( TC0, 0 ) ;
/* Infinite loop*/
while ( 1 ) ;
}
void tone(uint32_t ulPin, uint32_t frequency, int32_t duration)
{
const uint32_t rc = VARIANT_MCK / 256 / frequency;
tone_pin = ulPin;
toggle_count = 0; // strange wipe out previous duration
if (duration > 0 ) toggle_count = 2 * frequency * duration / 1000;
else toggle_count = -1;
if (!TCChanEnabled) {
pmc_set_writeprotect(false);
pmc_enable_periph_clk((uint32_t)TONE_IRQ);
TC_Configure(chTC, chNo,
TC_CMR_TCCLKS_TIMER_CLOCK4 |
TC_CMR_WAVE | // Waveform mode
TC_CMR_WAVSEL_UP_RC ); // Counter running up and reset when equals to RC
chTC->TC_CHANNEL[chNo].TC_IER=TC_IER_CPCS; // RC compare interrupt
chTC->TC_CHANNEL[chNo].TC_IDR=~TC_IER_CPCS;
NVIC_EnableIRQ(TONE_IRQ);
TCChanEnabled = 1;
}
if (!pinEnabled[ulPin]) {
pinMode(ulPin, OUTPUT);
pinEnabled[ulPin] = 1;
}
TC_Stop(chTC, chNo);
TC_SetRC(chTC, chNo, rc); // set frequency
TC_Start(chTC, chNo);
}
void
vMBPortTimersEnable( )
{
#if MB_TIMER_DEBUG == 1
PIO_Set( &xTimerDebugPins[0] );
#endif
TCX->TC_CHANNEL[TCCHANNEL].TC_IER = TC_IERX_CPAS;
TC_Start( TCX, 0 );
}
// Set the frequency (in Hz)
DueTimer DueTimer::setFrequency(long frequency){
Timer t = Timers[timer];
uint32_t rc = VARIANT_MCK/128/frequency; //128 because we selected TIMER_CLOCK4 above
TC_SetRA(t.tc, t.channel, rc/2); //50% high, 50% low
TC_SetRC(t.tc, t.channel, rc);
TC_Start(t.tc, t.channel);
t.tc->TC_CHANNEL[t.channel].TC_IER=TC_IER_CPCS;
t.tc->TC_CHANNEL[t.channel].TC_IDR=~TC_IER_CPCS;
return *this;
}
void TimerInit()
{
PMC_EnablePeripheral(AT91C_ID_TC0); // enable the Timer Counter from PMC
TC_Configure(AT91C_BASE_TC0, AT91C_TC_CPCTRG); // Configure TC-0 with RC compare trig.
AT91C_BASE_TC0->TC_RC = 24000; // Interrupt every 0.001s
TC_Start(AT91C_BASE_TC0); // start the timer
AIC_ConfigureIT(AT91C_ID_TC0, AT91C_AIC_PRIOR_LOWEST, ISR_TC0);
AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS;
AIC_EnableIT(AT91C_ID_TC0);
}
void startTimer(Tc *tc, uint32_t channel, IRQn_Type irq, uint32_t frequency) {
pmc_set_writeprotect(false);
pmc_enable_periph_clk((uint32_t)irq);
TC_Configure(tc, channel, TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_TCCLKS_TIMER_CLOCK4);
uint32_t rc = VARIANT_MCK/128/frequency; //128 because we selected TIMER_CLOCK4 above
tc->TC_CHANNEL[channel].TC_RA = rc/2;
tc->TC_CHANNEL[channel].TC_RC = rc;
TC_Start(tc, channel);
tc->TC_CHANNEL[channel].TC_IER=TC_IER_CPCS;
tc->TC_CHANNEL[channel].TC_IDR=~TC_IER_CPCS;
NVIC_EnableIRQ(irq);
}
void vInitialiseTimerForIntQueueTest( void )
{
const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;
/* Enable the TC clocks. */
PMC_EnablePeripheral( ID_TC0 );
PMC_EnablePeripheral( ID_TC1 );
/* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger
on RC compare. This is part of the IntQTimer test. */
TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger
on RC compare. This is part of the IntQTimer test. */
TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider );
TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;
/* Configure and enable TC0 interrupt on RC compare. */
NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );
NVIC_ClearPendingIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC0_IRQn );
/* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on
RC compare. This is the very high frequency timer. */
TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_2_FREQUENCY * ulDivider );
TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;
/* Configure and enable TC1 interrupt on RC compare */
// NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );
// NVIC_ClearPendingIRQ( TC1_IRQn );
// NVIC_EnableIRQ( TC1_IRQn );
TC_Start( TC0, tmrTC0_CHANNEL_0 );
TC_Start( TC0, tmrTC0_CHANNEL_1 );
// TC_Start( TC1, tmrTC1_CHANNEL_0 );
}
/**
* Enable/Disable audio channels
*/
static void AudioPlayEnable(uint8_t enable)
{
if (enable == 1) {
TC_Start(TC0, 0);
DACC_EnableChannel(DACC, CHANNEL_R);
DACC_EnableChannel(DACC, CHANNEL_L);
}
else if (enable == 0) {
TC_Stop(TC0, 0);
DACC_DisableChannel(DACC, CHANNEL_R);
DACC_DisableChannel(DACC, CHANNEL_R);
}
}
int platform_init()
{
int i;
// Enable the peripherals we use in the PMC
PMC_EnablePeripheral( AT91C_ID_US0 );
PMC_EnablePeripheral( AT91C_ID_US1 );
PMC_EnablePeripheral( AT91C_ID_PIOA );
PMC_EnablePeripheral( AT91C_ID_PIOB );
PMC_EnablePeripheral( AT91C_ID_TC0 );
PMC_EnablePeripheral( AT91C_ID_TC1 );
PMC_EnablePeripheral( AT91C_ID_TC2 );
PMC_EnablePeripheral( AT91C_ID_PWMC );
// Configure the timers
AT91C_BASE_TCB->TCB_BMR = 0x15;
for( i = 0; i < 3; i ++ )
TC_Configure( ( AT91S_TC* )timer_base[ i ], AT91C_TC_CLKS_TIMER_DIV5_CLOCK | AT91C_TC_WAVE );
// PWM setup (only the clocks are set at this point)
PWMC_ConfigureClocks( BOARD_MCK, BOARD_MCK, BOARD_MCK );
PWMC_ConfigureChannel( 0, AT91C_PWMC_CPRE_MCKA, 0, 0 );
PWMC_ConfigureChannel( 1, AT91C_PWMC_CPRE_MCKA, 0, 0 );
PWMC_ConfigureChannel( 2, AT91C_PWMC_CPRE_MCKB, 0, 0 );
PWMC_ConfigureChannel( 3, AT91C_PWMC_CPRE_MCKB, 0, 0 );
for( i = 0; i < 4; i ++ )
{
PWMC_EnableChannel( i );
PWMC_EnableChannelIt( i );
}
cmn_platform_init();
#if VTMR_NUM_TIMERS > 0
// Virtual timer initialization
TC_Configure( AT91C_BASE_TC2, AT91C_TC_CLKS_TIMER_DIV5_CLOCK | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO );
AT91C_BASE_TC2->TC_RC = ( BOARD_MCK / 1024 ) / VTMR_FREQ_HZ;
AIC_DisableIT( AT91C_ID_TC2 );
AIC_ConfigureIT( AT91C_ID_TC2, 0, ISR_Tc2 );
AT91C_BASE_TC2->TC_IER = AT91C_TC_CPCS;
AIC_EnableIT( AT91C_ID_TC2 );
TC_Start( AT91C_BASE_TC2 );
#endif
// Initialize the system timer
cmn_systimer_set_base_freq( BOARD_MCK / 16 );
cmn_systimer_set_interrupt_period_us( SYSTIMER_US_PER_INTERRUPT );
platform_systimer_init();
return PLATFORM_OK;
}
/**
* Configure TC0 to generate an interrupt every 4ms
*/
static void ConfigureTc0(void)
{
uint32_t div, tcclks;
/* Enable TC0 peripheral */
PMC_EnablePeripheral(ID_TC0);
/* Configure TC0 for 250Hz frequency and trigger on RC compare */
TC_FindMckDivisor(250, BOARD_MCK, &div, &tcclks, BOARD_MCK);
TC_Configure(TC0, 0, tcclks | TC_CMR_CPCTRG);
TC0->TC_CHANNEL[0].TC_RC = (BOARD_MCK / div) / 250;
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ(TC0_IRQn);
TC0->TC_CHANNEL[0].TC_IER = TC_IER_CPCS;
/* Start TC as event timer */
TC_Start(TC0, 0);
}
void BaseDMD::begin()
{
beginNoTimer(); // Do any generic setup
NVIC_DisableIRQ(TC7_IRQn);
register_running_dmd(this);
pmc_set_writeprotect(false);
pmc_enable_periph_clk(TC7_IRQn);
// Timer 7 is TC2, channel 1
TC_Configure(TC2, 1, TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_TCCLKS_TIMER_CLOCK4); // counter up, /128 divisor
TC_SetRC(TC2, 1, 2500); // approx 4ms at /128 divisor
TC2->TC_CHANNEL[1].TC_IER=TC_IER_CPCS;
NVIC_ClearPendingIRQ(TC7_IRQn);
NVIC_EnableIRQ(TC7_IRQn);
TC_Start(TC2, 1);
}
static void _initISR(Tc *tc, uint32_t channel, uint32_t id, IRQn_Type irqn) {
pmc_enable_periph_clk(id);
TC_Configure(tc, channel,
TC_CMR_TCCLKS_TIMER_CLOCK3 | // MCK/32
TC_CMR_WAVE | // Waveform mode
TC_CMR_WAVSEL_UP_RC ); // Counter running up and reset when equals to RC
/* 84MHz, MCK/32, for 1.5ms: 3937 */
TC_SetRA(tc, channel, 2625); // 1ms
/* Configure and enable interrupt */
NVIC_EnableIRQ(irqn);
// TC_IER_CPAS: RA Compare
tc->TC_CHANNEL[channel].TC_IER = TC_IER_CPAS;
// Enables the timer clock and performs a software reset to start the counting
TC_Start(tc, channel);
}
DueTimer& DueTimer::start(long microseconds){
/*
Start the timer
If a period is set, then sets the period and start the timer
*/
if(microseconds > 0)
setPeriod(microseconds);
if(_frequency[timer] <= 0)
setFrequency(1);
NVIC_ClearPendingIRQ(Timers[timer].irq);
NVIC_EnableIRQ(Timers[timer].irq);
TC_Start(Timers[timer].tc, Timers[timer].channel);
return *this;
}
void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
Tc *tc = TimerConfig[timer_num].pTimerRegs;
IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
uint32_t channel = TimerConfig[timer_num].channel;
pmc_set_writeprotect(false);
pmc_enable_periph_clk((uint32_t)irq);
NVIC_SetPriority(irq, TimerConfig [timer_num].priority);
TC_Configure(tc, channel, TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_TCCLKS_TIMER_CLOCK1);
TC_SetRC(tc, channel, VARIANT_MCK / 2 / frequency);
TC_Start(tc, channel);
// enable interrupt on RC compare
tc->TC_CHANNEL[channel].TC_IER = TC_IER_CPCS;
NVIC_EnableIRQ(irq);
}
/*------------------------------------------------------------------------------
Name: startTimer
parameters: tc - timer counter
channel - timer channel
irq - isr request
frequency - frequency of inetrrupts
description: initializes timer for periodic interrupt generation
------------------------------------------------------------------------------*/
void BldcControl::configureTimerInterrupt(Tc *tc,
uint32_t channel,
IRQn_Type irq,
uint32_t frequency)
{
pmc_set_writeprotect(false);
pmc_enable_periph_clk((uint32_t)irq);
TC_Configure(tc,
channel,
TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC |
TC_CMR_TCCLKS_TIMER_CLOCK4);
uint32_t rc = VARIANT_MCK/128/frequency; //128 because we selected
//TIMER_CLOCK4 above
TC_SetRA(tc, channel, rc/2); //50% high, 50% low
TC_SetRC(tc, channel, rc);
TC_Start(tc, channel);
tc->TC_CHANNEL[channel].TC_IER=TC_IER_CPCS;
tc->TC_CHANNEL[channel].TC_IDR=~TC_IER_CPCS;
NVIC_EnableIRQ(irq);
}
//--------------------------------------------------
// Init Timer 1 for Soft PWM (Hotend 1 & 2)
//--------------------------------------------------
void ConfigureTc_1(void)
{
// Enable peripheral clock
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_TC1;
unsigned int freq=10000;
// Configure TC for a 10 kHz frequency and trigger on RC compare
//TC_FindMckDivisor(freq, BOARD_MCK, &div, &tcclks);
TC_Configure(AT91C_BASE_TC1, 3 | AT91C_TC_CPCTRG);
AT91C_BASE_TC1->TC_RB = 3;
AT91C_BASE_TC1->TC_RC = (BOARD_MCK / 128) / freq; // timerFreq / desiredFreq
// Configure and enable interrupt on RC compare
//IRQ_ConfigureIT(AT91C_ID_TC1, 2, TC1_IrqHandler);
AT91C_BASE_TC1->TC_IER = AT91C_TC_CPCS | AT91C_TC_CPBS;
IRQ_EnableIT(AT91C_ID_TC1);
// Start the counter if LED is enabled.
TC_Start(AT91C_BASE_TC1);
}
/**
* Configure Timer Counter 0 to generate an interrupt every 250ms.
*/
static void _ConfigureTc(void)
{
uint32_t div;
uint32_t tcclks;
/** Enable peripheral clock. */
PMC_EnablePeripheral(ID_TC0);
/** Configure TC for a 4Hz frequency and trigger on RC compare. */
TC_FindMckDivisor(4, BOARD_MCK, &div, &tcclks, BOARD_MCK);
TC_Configure(TC0, 0, tcclks | TC_CMR_CPCTRG);
TC0->TC_CHANNEL[0].TC_RC = (BOARD_MCK / div) / 4;
/* Configure and enable interrupt on RC compare */
NVIC_ClearPendingIRQ(TC0_IRQn);
NVIC_EnableIRQ(TC0_IRQn);
TC0->TC_CHANNEL[0].TC_IER = TC_IER_CPCS;
/** Start the counter */
TC_Start(TC0, 0);
}
/**
* Initialize for timing operation
*/
void sys_init_timing(void)
{
uint32_t div;
uint32_t tcclks;
/* Clear tick value */
dwClockTick = 0;
/* Enable peripheral clock. */
PMC_EnablePeripheral( ID_TC0 ) ;
/* Configure TC for a CLOCK_CONF_SECOND frequency. */
TC_FindMckDivisor( CLOCK_CONF_SECOND, BOARD_MCK, &div, &tcclks, BOARD_MCK );
TC_Configure( TC0, 0, tcclks | TC_CMR_CPCTRG );
TC0->TC_CHANNEL[0].TC_RC = BOARD_MCK / (CLOCK_CONF_SECOND * div);
/* Configure and enable interrupt on RC compare */
NVIC_ClearPendingIRQ(TC0_IRQn);
NVIC_EnableIRQ(TC0_IRQn);
TC0->TC_CHANNEL[ 0 ].TC_IER = TC_IER_CPCS ;
/* Start timer */
TC_Start( TC0, 0 );
}
// Set up all timer interrupts
void HAL::setupTimer() {
uint32_t tc_count, tc_clock;
pmc_set_writeprotect(false);
// set 3 bits for interrupt group priority, 1 bits for sub-priority
//NVIC_SetPriorityGrouping(4);
#if USE_ADVANCE
// Timer for extruder control
pmc_enable_periph_clk(EXTRUDER_TIMER_IRQ); // enable power to timer
//NVIC_SetPriority((IRQn_Type)EXTRUDER_TIMER_IRQ, NVIC_EncodePriority(4, 4, 1));
NVIC_SetPriority((IRQn_Type)EXTRUDER_TIMER_IRQ, 6);
// count up to value in RC register using given clock
TC_Configure(EXTRUDER_TIMER, EXTRUDER_TIMER_CHANNEL, TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE | TC_CMR_TCCLKS_TIMER_CLOCK3);
TC_SetRC(EXTRUDER_TIMER, EXTRUDER_TIMER_CHANNEL, (F_CPU_TRUE / 32) / EXTRUDER_CLOCK_FREQ); // set frequency 43 for 60000Hz
TC_Start(EXTRUDER_TIMER, EXTRUDER_TIMER_CHANNEL); // start timer running
// enable RC compare interrupt
EXTRUDER_TIMER->TC_CHANNEL[EXTRUDER_TIMER_CHANNEL].TC_IER = TC_IER_CPCS;
// clear the "disable RC compare" interrupt
EXTRUDER_TIMER->TC_CHANNEL[EXTRUDER_TIMER_CHANNEL].TC_IDR = ~TC_IER_CPCS;
// allow interrupts on timer
NVIC_EnableIRQ((IRQn_Type)EXTRUDER_TIMER_IRQ);
#endif
// Regular interrupts for heater control etc
pmc_enable_periph_clk(PWM_TIMER_IRQ);
//NVIC_SetPriority((IRQn_Type)PWM_TIMER_IRQ, NVIC_EncodePriority(4, 6, 0));
NVIC_SetPriority((IRQn_Type)PWM_TIMER_IRQ, 15);
TC_FindMckDivisor(PWM_CLOCK_FREQ, F_CPU_TRUE, &tc_count, &tc_clock, F_CPU_TRUE);
TC_Configure(PWM_TIMER, PWM_TIMER_CHANNEL, TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE | tc_clock);
TC_SetRC(PWM_TIMER, PWM_TIMER_CHANNEL, (F_CPU_TRUE / tc_count) / PWM_CLOCK_FREQ);
TC_Start(PWM_TIMER, PWM_TIMER_CHANNEL);
PWM_TIMER->TC_CHANNEL[PWM_TIMER_CHANNEL].TC_IER = TC_IER_CPCS;
PWM_TIMER->TC_CHANNEL[PWM_TIMER_CHANNEL].TC_IDR = ~TC_IER_CPCS;
NVIC_EnableIRQ((IRQn_Type)PWM_TIMER_IRQ);
// Timer for stepper motor control
pmc_enable_periph_clk(TIMER1_TIMER_IRQ );
//NVIC_SetPriority((IRQn_Type)TIMER1_TIMER_IRQ, NVIC_EncodePriority(4, 7, 1)); // highest priority - no surprises here wanted
NVIC_SetPriority((IRQn_Type)TIMER1_TIMER_IRQ,2); // highest priority - no surprises here wanted
TC_Configure(TIMER1_TIMER, TIMER1_TIMER_CHANNEL, TC_CMR_WAVSEL_UP_RC |
TC_CMR_WAVE | TC_CMR_TCCLKS_TIMER_CLOCK1);
TC_SetRC(TIMER1_TIMER, TIMER1_TIMER_CHANNEL, (F_CPU_TRUE / TIMER1_PRESCALE) / TIMER1_CLOCK_FREQ);
TC_Start(TIMER1_TIMER, TIMER1_TIMER_CHANNEL);
TIMER1_TIMER->TC_CHANNEL[TIMER1_TIMER_CHANNEL].TC_IER = TC_IER_CPCS;
TIMER1_TIMER->TC_CHANNEL[TIMER1_TIMER_CHANNEL].TC_IDR = ~TC_IER_CPCS;
NVIC_EnableIRQ((IRQn_Type)TIMER1_TIMER_IRQ);
// Servo control
#if FEATURE_SERVO
#if SERVO0_PIN > -1
SET_OUTPUT(SERVO0_PIN);
WRITE(SERVO0_PIN, LOW);
#endif
#if SERVO1_PIN > -1
SET_OUTPUT(SERVO1_PIN);
WRITE(SERVO1_PIN, LOW);
#endif
#if SERVO2_PIN > -1
SET_OUTPUT(SERVO2_PIN);
WRITE(SERVO2_PIN, LOW);
#endif
#if SERVO3_PIN > -1
SET_OUTPUT(SERVO3_PIN);
WRITE(SERVO3_PIN, LOW);
#endif
pmc_enable_periph_clk(SERVO_TIMER_IRQ );
//NVIC_SetPriority((IRQn_Type)SERVO_TIMER_IRQ, NVIC_EncodePriority(4, 5, 0));
NVIC_SetPriority((IRQn_Type)SERVO_TIMER_IRQ,4);
TC_Configure(SERVO_TIMER, SERVO_TIMER_CHANNEL, TC_CMR_WAVSEL_UP_RC |
TC_CMR_WAVE | TC_CMR_TCCLKS_TIMER_CLOCK1);
TC_SetRC(SERVO_TIMER, SERVO_TIMER_CHANNEL, (F_CPU_TRUE / SERVO_PRESCALE) / SERVO_CLOCK_FREQ);
TC_Start(SERVO_TIMER, SERVO_TIMER_CHANNEL);
SERVO_TIMER->TC_CHANNEL[SERVO_TIMER_CHANNEL].TC_IER = TC_IER_CPCS;
SERVO_TIMER->TC_CHANNEL[SERVO_TIMER_CHANNEL].TC_IDR = ~TC_IER_CPCS;
NVIC_EnableIRQ((IRQn_Type)SERVO_TIMER_IRQ);
#endif
}
void tone(uint8_t _pin, unsigned int frequency, unsigned long duration)
{
uint8_t prescalarbits = 0b001;
long toggle_count = 0;
uint32_t ocr = 0;
int8_t _timer;
_timer = toneBegin(_pin);
if (_timer >= 0)
{
// Set the pinMode as OUTPUT
pinMode(_pin, OUTPUT);
// if we are using an 8 bit timer, scan through prescalars to find the best fit
if (_timer == 0 || _timer == 2)
{
ocr = F_CPU / frequency / 2 - 1;
prescalarbits = 0b001; // ck/1: same for both timers
if (ocr > 255)
{
ocr = F_CPU / frequency / 2 / 8 - 1;
prescalarbits = 0b010; // ck/8: same for both timers
if (_timer == 2 && ocr > 255)
{
ocr = F_CPU / frequency / 2 / 32 - 1;
prescalarbits = 0b011;
}
if (ocr > 255)
{
ocr = F_CPU / frequency / 2 / 64 - 1;
prescalarbits = _timer == 0 ? 0b011 : 0b100;
if (_timer == 2 && ocr > 255)
{
ocr = F_CPU / frequency / 2 / 128 - 1;
prescalarbits = 0b101;
}
if (ocr > 255)
{
ocr = F_CPU / frequency / 2 / 256 - 1;
prescalarbits = _timer == 0 ? 0b100 : 0b110;
if (ocr > 255)
{
// can't do any better than /1024
ocr = F_CPU / frequency / 2 / 1024 - 1;
prescalarbits = _timer == 0 ? 0b101 : 0b111;
}
}
}
}
#if defined(TCCR0B)
if (_timer == 0)
{
TCCR0B = prescalarbits;
}
else
#endif
#if defined(TCCR2B)
{
TCCR2B = prescalarbits;
}
#else
{
// dummy place holder to make the above ifdefs work
}
#endif
}
else
{
// two choices for the 16 bit timers: ck/1 or ck/64
ocr = F_CPU / frequency / 2 - 1;
prescalarbits = 0b001;
if (ocr > 0xffff)
{
ocr = F_CPU / frequency / 2 / 64 - 1;
prescalarbits = 0b011;
}
if (_timer == 1)
{
#if defined(TCCR1B)
TCCR1B = (TCCR1B & 0b11111000) | prescalarbits;
#endif
}
#if defined(TCCR3B)
else if (_timer == 3)
TCCR3B = (TCCR3B & 0b11111000) | prescalarbits;
#endif
#if defined(TCCR4B)
else if (_timer == 4)
TCCR4B = (TCCR4B & 0b11111000) | prescalarbits;
#endif
#if defined(TCCR5B)
else if (_timer == 5)
TCCR5B = (TCCR5B & 0b11111000) | prescalarbits;
#endif
}
// Calculate the toggle count
if (duration > 0)
{
toggle_count = 2 * frequency * duration / 1000;
}
else
{
toggle_count = -1;
}
// Set the OCR for the given timer,
// set the toggle count,
// then turn on the interrupts
switch (_timer)
{
#if defined(OCR0A) && defined(TIMSK0) && defined(OCIE0A)
case 0:
OCR0A = ocr;
timer0_toggle_count = toggle_count;
bitWrite(TIMSK0, OCIE0A, 1);
break;
#endif
case 1:
#if defined(OCR1A) && defined(TIMSK1) && defined(OCIE1A)
OCR1A = ocr;
timer1_toggle_count = toggle_count;
bitWrite(TIMSK1, OCIE1A, 1);
#elif defined(OCR1A) && defined(TIMSK) && defined(OCIE1A)
// this combination is for at least the ATmega32
OCR1A = ocr;
timer1_toggle_count = toggle_count;
bitWrite(TIMSK, OCIE1A, 1);
#endif
break;
#if defined(OCR2A) && defined(TIMSK2) && defined(OCIE2A)
case 2:
OCR2A = ocr;
timer2_toggle_count = toggle_count;
bitWrite(TIMSK2, OCIE2A, 1);
break;
#endif
#if defined(TIMSK3)
case 3:
OCR3A = ocr;
timer3_toggle_count = toggle_count;
bitWrite(TIMSK3, OCIE3A, 1);
break;
#endif
#if defined(TIMSK4)
case 4:
OCR4A = ocr;
timer4_toggle_count = toggle_count;
bitWrite(TIMSK4, OCIE4A, 1);
break;
#endif
#if defined(OCR5A) && defined(TIMSK5) && defined(OCIE5A)
case 5:
OCR5A = ocr;
timer5_toggle_count = toggle_count;
bitWrite(TIMSK5, OCIE5A, 1);
break;
#endif
#if defined(TC0) && defined(TC1) && defined(TC2)
case 6:
ocr = VARIANT_MCK / 256 / frequency;
TC_Stop(TC1, 0);
TC_SetRC(TC1, 0, ocr);
TC_Start(TC1, 0);
timer6_toggle_count = toggle_count;
break;
#endif
}
}
}
static uint32_t _WFE_Potentiometer_Initialize( void )
{
Adc *pAdc = ADC;
int32_t dwLowPotThreshold, dwHighPotThreshold;
/* STEP1: Realize a first measure to get potentiometer's initial position */
/* Initialize ADC*/
ADC_Initialize( pAdc,ID_ADC, ADC_MR_TRGEN_DIS,/*HARDWARE trigger*/
0,ADC_MR_SLEEP_NORMAL,ADC_MR_LOWRES_12_BIT,
BOARD_MCK,BOARD_ADC_FREQ,10,20);
/*Enable channel 5 (potentiometer) */
ADC_EnableChannel(pAdc, ADC_CHANNEL_5);
/* Start convrsion */
ADC_StartConversion(pAdc);
/* Wait for the end of conversion */
while ( !(ADC_GetStatus(pAdc) & ADC_ISR_EOC5) ) {}
/* Get the potentiometer initial value */
gdwPotentiometerValue = ADC_GetConvertedData(pAdc, ADC_CHANNEL_5);
/* Set Window threshold according to the initial values */
dwLowPotThreshold = gdwPotentiometerValue - (NB_INTERVALS * (0x1000 / 256));
if (dwLowPotThreshold < 0)
dwLowPotThreshold = 0;
dwHighPotThreshold = gdwPotentiometerValue + (NB_INTERVALS * (0x1000 / 256));
if (dwHighPotThreshold >= 0x1000)
dwHighPotThreshold = 0x1000 - 1;
/* Normalize the value 0 -> 255 */
gdwPotentiometerValue = (gdwPotentiometerValue * 256) / 0xFFF;
/* STEP2: Re configure ADC to use windowing */
/* Initialize ADC*/
ADC_Initialize( pAdc,ID_ADC, ADC_MR_TRGEN_EN,/*HARDWARE trigger*/
ADC_MR_TRGSEL_ADC_TRIG0,ADC_MR_SLEEP_NORMAL,ADC_MR_LOWRES_12_BIT,
BOARD_MCK,BOARD_ADC_FREQ,10,20);
/*Enable channel 5 (potentiometer) */
ADC_EnableChannel(pAdc, ADC_CHANNEL_5);
/* Configure TC*/
ConfigureTc0();
/*Channel 5 has to be compared*/
ADC_SetCompareChannel(pAdc, ADC_CHANNEL_5);
/*Compare mode, in the window*/
ADC_SetCompareMode(pAdc, ADC_EMR_CMPMODE_OUT);
/* Setup Threshold*/
ADC_SetComparisonWindow(pAdc,((dwHighPotThreshold<<16)|dwLowPotThreshold));
/* enable adc interrupt*/
NVIC_EnableIRQ(ADC_IRQn);
/* Enable Compare Interrupt*/
ADC_EnableIt(pAdc, ADC_IDR_COMPE);
/* Start TC0 and hardware trigger*/
TC_Start(TC0,0);
return SAMGUI_E_OK ;
}
void DACClass::begin(uint32_t period) {
// Enable clock for DAC
pmc_enable_periph_clk(dacId);
dacc_reset(dac);
// Set transfer mode to double word
dacc_set_transfer_mode(dac, 1);
// Power save:
// sleep mode - 0 (disabled)
// fast wakeup - 0 (disabled)
dacc_set_power_save(dac, 0, 0);
// DAC refresh/startup timings:
// refresh - 0x08 (1024*8 dacc clocks)
// max speed mode - 0 (disabled)
// startup time - 0x10 (1024 dacc clocks)
dacc_set_timing(dac, 0x08, 0, DACC_MR_STARTUP_1024);
// Flexible channel selection with tags
dacc_enable_flexible_selection(dac);
// Set up analog current
dacc_set_analog_control(dac,
DACC_ACR_IBCTLCH0(0x02) |
DACC_ACR_IBCTLCH1(0x02) |
DACC_ACR_IBCTLDACCORE(0x01));
// Enable output channels
dacc_enable_channel(dac, 0);
dacc_enable_channel(dac, 1);
// Configure Timer Counter to trigger DAC
// --------------------------------------
pmc_enable_periph_clk(ID_TC1);
TC_Configure(TC0, 1,
TC_CMR_TCCLKS_TIMER_CLOCK2 | // Clock at MCR/8
TC_CMR_WAVE | // Waveform mode
TC_CMR_WAVSEL_UP_RC | // Counter running up and reset when equals to RC
TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR);
const uint32_t TC = period / 8;
TC_SetRA(TC0, 1, TC / 2);
TC_SetRC(TC0, 1, TC);
TC_Start(TC0, 1);
// Configure clock source for DAC (2 = TC0 Output Chan. 1)
dacc_set_trigger(dac, 2);
// Configure pins
PIO_Configure(g_APinDescription[DAC0].pPort,
g_APinDescription[DAC0].ulPinType,
g_APinDescription[DAC0].ulPin,
g_APinDescription[DAC0].ulPinConfiguration);
PIO_Configure(g_APinDescription[DAC1].pPort,
g_APinDescription[DAC1].ulPinType,
g_APinDescription[DAC1].ulPin,
g_APinDescription[DAC1].ulPinConfiguration);
// Enable interrupt controller for DAC
dacc_disable_interrupt(dac, 0xFFFFFFFF);
NVIC_DisableIRQ(isrId);
NVIC_ClearPendingIRQ(isrId);
NVIC_SetPriority(isrId, 0);
NVIC_EnableIRQ(isrId);
}
void ADCSampler::begin(unsigned int samplingRate)
{
this->sampleingRate = sampleingRate;
// Turning devices Timer on.
pmc_enable_periph_clk(ID_TC0);
// Configure timer
TC_Configure(TC0, 0, TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET | TC_CMR_ASWTRG_CLEAR | TC_CMR_TCCLKS_TIMER_CLOCK1);
// It is good to have the timer 0 on PIN2, good for Debugging
//int result = PIO_Configure( PIOB, PIO_PERIPH_B, PIO_PB25B_TIOA0, PIO_DEFAULT);
// Configure ADC pin A7
// the below code is taken from adc_init(ADC, SystemCoreClock, ADC_FREQ_MAX, ADC_STARTUP_FAST);
ADC->ADC_CR = ADC_CR_SWRST; // Reset the controller.
ADC->ADC_MR = 0; // Reset Mode Register.
ADC->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS); // Reset PDC transfer.
ADC->ADC_MR |= ADC_MR_PRESCAL(3); // ADC clock = MSCK/((PRESCAL+1)*2), 13 -> 750000 Sps
ADC->ADC_MR |= ADC_MR_STARTUP_SUT0; // What is this by the way?
ADC->ADC_MR |= ADC_MR_TRACKTIM(15);
ADC->ADC_MR |= ADC_MR_TRANSFER(1);
ADC->ADC_MR |= ADC_MR_TRGEN_EN; // Hardware trigger selected by TRGSEL field is enabled. Включен аппаратный триггер, выбранный по полю TRGSEL.
ADC->ADC_MR |= ADC_MR_TRGSEL_ADC_TRIG1; // selecting TIOA0 as trigger.
ADC->ADC_MR |= ADC_MR_LOWRES_BITS_12; // brief (ADC_MR) 12-bit resolution
//ADC->ADC_ACR |= ADC_ACR_TSON; // Включить датчик температуры
ADC->ADC_CHER = ADC_CHANNELS; // Записать контролируемые входа
ADC->ADC_CHDR = ADC_CHANNELS_DIS; // Отключить не используемые входа
ADC->ADC_EMR = ADC_EMR_CMPMODE_IN // Генерирует событие, когда преобразованные данные пересекают окно сравнения.
// | ADC_EMR_CMPSEL(4) // Compare channel 4 = A3
| ADC_EMR_CMPALL // Compare ALL channel
| ADC_EMR_CMPFILTER(0); // Количество последовательных событий сравнения, необходимых для повышения флага = CMPFILTER + 1
// При запрограммированном значении 0 флаг увеличивается, как только происходит событие.
ADC->ADC_CWR = ADC_CWR_LOWTHRES(_compare_Low) | ADC_CWR_HIGHTHRES(_compare_High); // Установить высокий и низкий порог компаратора АЦП
//ADC->ADC_SEQR1 = 0x01234567; // использовать A0 до A7 в порядке в массив
//ADC->ADC_SEQR2 = 0x00dcba00; // использовать для А8 А11 следующие действия по порядку в массив
/* Interupts */
ADC->ADC_IDR = ~ADC_IDR_ENDRX; // сбросить регистры прерывания по готовности данных.
ADC->ADC_IDR = ~ADC_IDR_COMPE; // сбросить регистры копаратора.
ADC->ADC_IER = ADC_IER_ENDRX; // Включить прерывание по готовности данных.
// ADC->ADC_IER = ADC_IER_COMPE; // Прерывание по совпадению сравнения компаратором
ADC->ADC_ISR = ~ADC_ISR_COMPE; // ADC Interrupt Status Register Обнулить ошибку сравнения с момента последнего чтения ADC_ISR.
/* Waiting for ENDRX as end of the transfer is set
when the current DMA transfer is done (RCR = 0), i.e. it doesn't include the
next DMA transfer.
If we trigger on RXBUFF This flag is set if there is no more DMA transfer in
progress (RCR = RNCR = 0). Hence we may miss samples.
Ожидание окончания ENDRX в конце передачи
когда выполняется текущая передача DMA (RCR = 0), то есть она не включает следующая передача DMA.
Если мы запускаем RXBUFF, этот флаг устанавливается, если больше нет передачи DMA в прогресс (RCR = RNCR = 0).
Следовательно, мы можем пропустить образцы.
*/
unsigned int cycles = 42000000 / samplingRate;
/* timing of ADC */
TC_SetRC(TC0, 0, cycles); // TIOA0 goes HIGH on RC.
TC_SetRA(TC0, 0, cycles / 2); // TIOA0 goes LOW on RA.
// We have to reinitalise just in case the Sampler is stopped and restarted...
// Мы должны приступить к реинициализировать на случай, если Sampler остановлен и перезапущен ...
dataReady = false;
dataHigh = false; // Признак срабатывания компаратора
adcDMAIndex = 0;
adcTransferIndex = 0;
for (int i = 0; i < NUMBER_OF_BUFFERS; i++)
{
memset((void *)adcBuffer[i], 0, BUFFER_SIZE);
}
ADC->ADC_RPR = (unsigned long) adcBuffer[adcDMAIndex]; // DMA buffer
ADC->ADC_RCR = (unsigned int) BUFFER_SIZE; // ADC works in half-word mode.
ADC->ADC_RNPR = (unsigned long) adcBuffer[(adcDMAIndex + 1)]; // next DMA buffer
ADC->ADC_RNCR = (unsigned int) BUFFER_SIZE;
// Enable interrupts
NVIC_SetPriorityGrouping(NVIC_PriorityGroup_1);
NVIC_DisableIRQ(ADC_IRQn);
NVIC_ClearPendingIRQ(ADC_IRQn);
NVIC_SetPriority(ADC_IRQn, 6);
NVIC_EnableIRQ(ADC_IRQn);
ADC->ADC_PTCR = ADC_PTCR_RXTEN; // Enable receiving data.
ADC->ADC_CR |= ADC_CR_START; // start waiting for trigger.
// Start timer
TC0->TC_CHANNEL[0].TC_SR;
TC0->TC_CHANNEL[0].TC_CCR = TC_CCR_CLKEN;
TC_Start(TC0, 0);
}
/*----------------------------------------------------------------------------
* Handles interrupts coming from USART
*----------------------------------------------------------------------------*/
void USART_Handler(void)
{
uint32_t status;
unsigned short serialState;
status = BASE_USART->US_CSR;
status &= BASE_USART->US_IMR;
/* If USB device is not configured, do nothing */
if (!isSerialPortON) {
BASE_USART->US_IDR = 0xFFFFFFFF;
return;
}
/* Buffer has been read successfully */
if ((status & US_CSR_ENDRX) != 0) {
/* Disable timer */
TC_Stop(TC0, 0);
/* Send buffer through the USB */
while (CDCDSerial_Write(usartBuffers[usartCurrentBuffer],
DATABUFFERSIZE, 0, 0) != USBD_STATUS_SUCCESS);
/* Restart read on buffer */
USART_ReadBuffer(BASE_USART,
usartBuffers[usartCurrentBuffer],
DATABUFFERSIZE);
usartCurrentBuffer = 1 - usartCurrentBuffer;
/* Restart timer */
TC_Start(TC0, 0);
}
/* Buffer has been sent */
if ((status & US_IER_TXBUFE) != 0) {
/* Restart USB read */
CDCDSerial_Read(usbSerialBuffer0,
DATABUFFERSIZE,
(TransferCallback) UsbDataReceived,
0);
BASE_USART->US_IDR = US_IER_TXBUFE;
}
/* Errors */
serialState = CDCDSerial_GetSerialState();
/* Overrun */
if ((status & US_CSR_OVRE) != 0) {
TRACE_WARNING( "USART1_IrqHandler: Overrun\n\r");
serialState |= CDCSerialState_OVERRUN;
}
/* Framing error */
if ((status & US_CSR_FRAME) != 0) {
TRACE_WARNING( "USART1_IrqHandler: Framing error\n\r");
serialState |= CDCSerialState_FRAMING;
}
CDCDSerial_SetSerialState(serialState);
}
