void test_andlw_with_valid_operand1_0xAA_should_xor_to_WREG_return_0x00_and_set_the_zero_flag_in_STATUS_REG(){
CEXCEPTION_T operandERR;
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0xAA,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x90
};
FSR[WREG] = 0x00;
//10101010 -> AA
//00000000 -> 00
//00000000 -> 00
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x04,FSR[STATUS]);
TEST_ASSERT_EQUAL_HEX8(0x91,code.absoluteAddress);
}
void test_andlw_with_valid_operand1_0xA5_should_xor_to_WREG_return_0x05_and_do_not_set_any_flag_in_STATUS_REG(){
CEXCEPTION_T operandERR;
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0xA5,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x34
};
FSR[WREG] = 0x55;
//10100101 -> A5
//01010101 -> 55
//00000101 -> 05
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x05,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[STATUS]);
TEST_ASSERT_EQUAL_HEX8(0x35,code.absoluteAddress);
}
void test_andlw_with_valid_operand1_0xCD_should_and_to_WREG_return_0x85_and_set_the_neg_flag_in_STATUS_REG(){
CEXCEPTION_T operandERR;
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0xCD,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x18
};
FSR[WREG] = 0x85;
//11001101 -> CD
//10000101 -> 85
//10000101 -> 85
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x85,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x10,FSR[STATUS]);
TEST_ASSERT_EQUAL_HEX8(0x19,code.absoluteAddress);
}
void test_xorlw_with_non_empty_operand2_0x00_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with 0x0A
//-1 represent empty
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0x0A,
.operand2 = 0,
.operand3 = -1,
.absoluteAddress = 0x04
};
FSR[WREG] = 0xB5;
//00001010 -> 0A
//10110101 -> B5
//10111111 -> BF
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND2,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x04,code.absoluteAddress);
}
void test_lfsr_should_load_0x4A2_into_LFSR0(){
CEXCEPTION_T catchError;
int result;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = LFSR, .name = "lfsr"},
.operand1 = 0,
.operand2 = 0x4A2,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize FSR[FSR0L] and FSR[FSR0H] to 0
FSR[FSR0H] = 0x00;
FSR[FSR0L] = 0x00;
Try{
result = lfsr(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0x04, FSR[FSR0H]);
TEST_ASSERT_EQUAL_HEX8(0xA2, FSR[FSR0L]);
TEST_ASSERT_EQUAL(1, result);
}
void test_andlw_with_valid_operand1_0x5A_should_xor_to_WREG_return_0x10(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and AND with 0x0A
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0x5A,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x100
};
FSR[WREG] = 0xB5;
//01011010 -> 5A
//10110101 -> B5
//00010000 -> 10
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x10,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x101,code.absoluteAddress);
}
void test_tblrdPreInc_should_read_data_from_TABLE_addr_0x200000_and_store_in_TABLAT_without_increment_on_tblptr(){
CEXCEPTION_T operandERR;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = TBLRD_PREINC, .name = "tblrd_PreInc"},
.operand1 = -1,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0xAA
};
FSR[TABLAT] = 0xCB;
FSR[TBLPTRU] = 0x20;
FSR[TBLPTRH] = 0x00;
FSR[TBLPTRL] = 0x00;
TABLE[0x200000] = 0xAC;
Try{
tblrd_PreInc(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_NON_EMPTY_OPERAND,operandERR);
}
TEST_ASSERT_EQUAL(0xAB, code.absoluteAddress);
TEST_ASSERT_EQUAL_HEX8(0xAC, FSR[TABLAT]);
TEST_ASSERT_EQUAL_HEX8(0x20, FSR[TBLPTRU]);
TEST_ASSERT_EQUAL_HEX8(0x00, FSR[TBLPTRH]);
TEST_ASSERT_EQUAL_HEX8(0x00, FSR[TBLPTRL]);
}
void test_CALL_should_go_to_0xAC_and_0x5026_will_push_to_TOS_and_STKPTR_increment_by1(){
CEXCEPTION_T operandERR;
Bytecode code = {.instruction = {.mnemonic = CALL, .name = "CALL"},
.operand1 = 0xAC,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x5024
};
//Next two address from 0x5024 - 0x5026
FSR[STKPTR] = 1;
FSR[TOSU] = 0x00;
FSR[TOSH] = 0x00;
FSR[TOSL] = 0xAC;
Try{
call(&code);
}Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xAC,code.absoluteAddress);
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[TOSU]);
TEST_ASSERT_EQUAL_HEX8(0x50,FSR[TOSH]);
TEST_ASSERT_EQUAL_HEX8(0x26,FSR[TOSL]);
TEST_ASSERT_EQUAL(2,FSR[STKPTR]);
}
void test_xorlw_with_valid_operand1_0x0A_should_xor_to_WREG_return_0xBF(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with 0x0A
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0x0A,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x03
};
FSR[WREG] = 0xB5;
//00001010 -> 0A
//10110101 -> B5
//10111111 -> BF
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xBF,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x04,code.absoluteAddress);
}
void test_xorlw_with_valid_operand1_0xA5_should_xor_to_WREG_return_0x20_and_do_not_set_any_flag_in_STATUS_REG(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with A5h and XOR with 0x0A
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0xA5,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x11
};
FSR[WREG] = 0x85;
//10100101 -> A5
//10000101 -> 85
//00100000 -> 20
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x20,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[STATUS]);
TEST_ASSERT_EQUAL_HEX8(0x12,code.absoluteAddress);
}
void test_addlw_should_set_digital_carry_flag(){
CEXCEPTION_T catchError;
int result;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = ADDLW, .name = "addlw"},
.operand1 = 0x08,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize WREG to 0x08 and add 0x08 to WREG
FSR[WREG] = 0x08;
//Initialize STATUS to 0x00
FSR[STATUS] = 0x00;
Try{
result = addlw(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0x10, FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x02, FSR[STATUS]);
TEST_ASSERT_EQUAL(1, result);
}
void test_tblrd_postdec_should_read_data_from_TABLE_addr_0x03A526_and_store_in_TABLAT_then_decrement_tblptr(){
CEXCEPTION_T catchError;
int result;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = TBLRD_POSTDEC, .name = "tblrd_postdec"},
.operand1 = -1,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize FSR[TABLAT] to 0, FSR[TBLPTRU] to 0x03, FSR[TBLPTRH] to 0xA5,
//FSR[TBLPTRL] to 0x26, TABLE[0x03A526] to 0x85
FSR[TABLAT] = 0;
FSR[TBLPTRU] = 0x03;
FSR[TBLPTRH] = 0xA5;
FSR[TBLPTRL] = 0x26;
TABLE[0x03A526] = 0x85;
Try{
result = tblrd_postdec(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL(1, result);
TEST_ASSERT_EQUAL_HEX8(0x85, FSR[TABLAT]);
TEST_ASSERT_EQUAL_HEX8(0x03, FSR[TBLPTRU]);
TEST_ASSERT_EQUAL_HEX8(0xA5, FSR[TBLPTRH]);
TEST_ASSERT_EQUAL_HEX8(0x25, FSR[TBLPTRL]);
}
static void given(int charsWritten) {
TEST_ASSERT_EQUAL(strlen(expected), charsWritten);
TEST_ASSERT_EQUAL_STRING(expected, &output[1]);
TEST_ASSERT_EQUAL_HEX8(0xaa, output[strlen(expected)+2]);
TEST_ASSERT_EQUAL_HEX8(0xaa, output[0]);
}
void test_MakeSureLedTurnsOnMenacingly(void)
{
PORT_A_DIR = 0xFF;
PORT_A_OUT = 0x00;
MenacingLed_Init();
TEST_ASSERT_EQUAL_HEX8(0xFD, PORT_A_DIR);
TEST_ASSERT_EQUAL_HEX8(0x02, PORT_A_OUT);
}
void test_addlw_should_set_overflow_flag(){
CEXCEPTION_T catchError;
int result, result2;
//Test fixture 1
Bytecode code = {.instruction = {.mnemonic = ADDLW, .name = "addlw"},
.operand1 = 0x40,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize WREG to 0x60 and add 0x40 to WREG
FSR[WREG] = 0x60;
//Initialize STATUS to 0x00
FSR[STATUS] = 0x00;
Try{
result = addlw(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0xA0, FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x18, FSR[STATUS]); // 0x18 = 0001 1000, negative flag is also set
TEST_ASSERT_EQUAL(1, result);
//Test fixture 2
Bytecode code2 = {.instruction = {.mnemonic = ADDLW, .name = "addlw"},
.operand1 = 0x84,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize WREG to 0x80 and add 0x84 to WREG
FSR[WREG] = 0x80;
//Initialize STATUS to 0x00
FSR[STATUS] = 0x00;
Try{
result2 = addlw(&code2);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0x04, FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x09, FSR[STATUS]); // 0x09 = 0000 1001, carry flag is also set
TEST_ASSERT_EQUAL(1, result2);
}
void test_setOneByteWithWriteMask(void)
{
i2c_setRegister(4,0);
i2c_setRegisterReadWriteMasks(4,0x00,0xF0);
setOneByte(address,4,0xFF);
TEST_ASSERT_EQUAL_HEX8(0x0F,getOneByte(address,4));
}
void test_ONFI_Features_CouldBeChange(void)
{
ONFI_SetFeatures(1, 0x05000000);
TEST_ASSERT_EQUAL_HEX8(0xe0, ONFI_ReadStatus());
//----------------------------------------------------------------
// !!! need to check if set to mode 4 successfully here !!!
//----------------------------------------------------------------
uint8_t buff[5];
buff[4] = 0;
ONFI_GetFeatures(1);
ONFI_receive8(buff, 4);
TEST_ASSERT_EQUAL_HEX8(0x05, buff[0]);
TEST_ASSERT_EQUAL_HEX32(0, get_count(NFC_REG[NFC_FMICFF_SLOT]));
TEST_ASSERT_EQUAL_HEX8(0xe0, ONFI_ReadStatus());
}
void test_movwf_should_move_content_inside_WREG_to_selected_file_register(){
CEXCEPTION_T errorStatus;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = MOVWF, .name = "movwf"},
.operand1 = 0x23,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x80
};
//Initialize WREG with value 0x45
FSR[WREG] = 0x45;
Try{
movwf(&code);
}Catch(errorStatus){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1, errorStatus);
}
TEST_ASSERT_EQUAL_HEX8(0x45,FSR[code.operand1]);
TEST_ASSERT_EQUAL_HEX8(0x81,code.absoluteAddress);
}
void testNotEqualHex8s(void)
{
_UU8 v0, v1;
v0 = 0x23;
v1 = 0x22;
EXPECT_ABORT_BEGIN
TEST_ASSERT_EQUAL_HEX8(v0, v1);
VERIFY_FAILS_END
}
void testNotEqualHex8sIfSigned(void)
{
_US8 v0, v1;
v0 = -2;
v1 = 2;
EXPECT_ABORT_BEGIN
TEST_ASSERT_EQUAL_HEX8(v0, v1);
VERIFY_FAILS_END
}
void test_andlw_with_non_empty_operand3_ACCESS_should_throw_exception(){
CEXCEPTION_T operandERR;
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0x0A,
.operand2 = -1,
.operand3 = ACCESS,
.absoluteAddress = 0x15
};
FSR[WREG] = 0xB5;
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND3,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x15,code.absoluteAddress);
}
void test_andlw_with_invalid_operand1_256_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and AND with 256
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 256,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x120
};
FSR[WREG] = 0xB5;
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x120,code.absoluteAddress);
}
void test_andlw_with_non_empty_operand2_0x00_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//-1 represent empty
Bytecode code = {.instruction = {.mnemonic = ANDLW, .name = "andlw"},
.operand1 = 0x0A,
.operand2 = 0,
.operand3 = -1,
.absoluteAddress = 0x11
};
FSR[WREG] = 0xB5;
Try{
andlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND2,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x11,code.absoluteAddress);
}
void test_s_operand1_0xffe_should_mock_and_return_0(void){
int value;
int e;
Text *text = textNew("135");
String *str = stringNew(text);
extractValue_ExpectAndReturn(str, 0xffe);
value = S(str);
TEST_ASSERT_EQUAL_HEX8(value, 0x0);
}
void test_addlw_should_add_a_hex_value_to_WREG(){
CEXCEPTION_T catchError;
int result;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = ADDLW, .name = "addlw"},
.operand1 = 0x20,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0
};
//Initialize WREG to 0x00 and add 0x20 to WREG
FSR[WREG] = 0x00;
Try{
result = addlw(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0x20, FSR[WREG]);
TEST_ASSERT_EQUAL(1, result);
//Initialize WREG to 0xFF and add 0x20 to WREG
FSR[WREG] = 0xFF;
result = 0;
Try{
result = addlw(&code);
} Catch(catchError){
TEST_FAIL_MESSAGE("Exception thrown when it should not have.");
}
TEST_ASSERT_EQUAL_HEX8(0x1F, FSR[WREG]);
TEST_ASSERT_EQUAL(1, result);
}
void test_xorlw_with_invalid_operand1_negative1_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with -1
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = -1,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x01
};
FSR[WREG] = 0xB5;
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x01,code.absoluteAddress);
}
void test_movwf_should_throw_an_exception_if_operand2_and_3_are_ACCESS_and_BANKED(){
CEXCEPTION_T errorStatus;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = MOVWF, .name = "movwf"},
.operand1 = 0x63,
.operand2 = ACCESS,
.operand3 = BANKED,
.absoluteAddress = 0x101
};
//Initialize WREG with value 0x45
FSR[code.operand1] = 0xA0;
FSR[WREG] = 0x45;
Try{
movwf(&code);
}Catch(errorStatus){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND3, errorStatus);
}
TEST_ASSERT_EQUAL_HEX8(0xA0,FSR[code.operand1]);
TEST_ASSERT_EQUAL_HEX8(0x101,code.absoluteAddress);
}
void test_movwf_with_valid_op2_op3_should_move_0x58_inside_WREG_to_selected_file_register_0x237(){
CEXCEPTION_T errorStatus;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = MOVWF, .name = "movwf"},
.operand1 = 0x88,
.operand2 = BANKED,
.operand3 = -1,
.absoluteAddress = 0x11
};
//Initialize WREG with value 0x58
FSR[BSR] = 0x02;
FSR[WREG] = 0x58;
Try{
movwf(&code);
}Catch(errorStatus){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND3, errorStatus);
}
TEST_ASSERT_EQUAL_HEX8(0x58,FSR[code.operand1+(FSR[BSR]<<8)]);
TEST_ASSERT_EQUAL_HEX8(0x12,code.absoluteAddress);
}
void test_movwf_with_invalid_bsr_should_throw_exception(){
CEXCEPTION_T errorStatus;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = MOVWF, .name = "movwf"},
.operand1 = 0x40,
.operand2 = BANKED,
.operand3 = -1,
.absoluteAddress = 0xAD
};
//Initialize WREG with value 0x58
FSR[BSR] = 0x10;
FSR[WREG] = 0x58;
Try{
movwf(&code);
}Catch(errorStatus){
TEST_ASSERT_EQUAL(ERR_INVALID_BSR, errorStatus);
}
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[code.operand1]);
TEST_ASSERT_EQUAL_HEX8(0xAD,code.absoluteAddress);
}
void test_movwf_should_throw_an_exception_if_operand2_is_F(){
CEXCEPTION_T errorStatus;
//Test fixture
Bytecode code = {.instruction = {.mnemonic = MOVWF, .name = "movwf"},
.operand1 = 0xB3,
.operand2 = F,
.operand3 = -1,
.absoluteAddress = 0x9A
};
//Initialize WREG with value 0x45
FSR[code.operand1] = 0x00;
FSR[WREG] = 0x45;
Try{
movwf(&code);
}Catch(errorStatus){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND2, errorStatus);
}
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[code.operand1]);
TEST_ASSERT_EQUAL_HEX8(0x9A,code.absoluteAddress);
}
