extern "C" unsigned int ds_get_clock_time(void)
{
if (((TIMER_DATA(3) << 16) | TIMER_DATA(2)) < 12)
return 0;
else
return ((TIMER_DATA(3) << 16) | TIMER_DATA(2)) - 12;
}
void
benchmark_timer_initialize (void)
{
TIMER_CR (1) = 0x0000;
TIMER_CR (2) = 0x0000;
TIMER_DATA (1) = TIMER_FREQ (1000000);
TIMER_DATA (2) = 0x0000;
TIMER_CR (1) = TIMER_ENABLE | TIMER_DIV_1;
TIMER_CR (2) = TIMER_ENABLE | TIMER_CASCADE;
}
static inline u32 stopTimer() {
#ifndef NATIVE
TIMER_CR(0) = 0;
TIMER_CR(1) = 0;
u32 data = TIMER_DATA(0) | (TIMER_DATA(1) << 16);
TIMER_DATA(0) = TIMER_DATA(1) = 0;
return data;
#else
return 0;
#endif
}
uint32_t
benchmark_timer_read (void)
{
uint32_t ticks;
/* stop counters */
TIMER_CR (1) = 0x0000;
TIMER_CR (2) = 0x0000;
/* read counter */
ticks = (TIMER_DATA (2) << 16) | TIMER_DATA (1);
return ticks;
}
//extern volatile int timer_hit;
extern "C" void ds_start_loop_timer(unsigned int frequency, unsigned int multiplier, unsigned int num_samples, void (*function)(void), void (*function2)(void))
{
unsigned short timer_value1 = 0xffff - ((32 * 1024 * 1024) / frequency) * multiplier + 1;
unsigned short timer_value2 = 0;
unsigned short timer_value3 = 0;
TIMER_DATA(1) = timer_value1;
TIMER_DATA(2) = timer_value2;
TIMER_DATA(3) = timer_value3;
TIMER_CR(1) = TIMER_ENABLE | TIMER_DIV_1;
TIMER_CR(2) = TIMER_ENABLE | TIMER_CASCADE;
TIMER_CR(3) = TIMER_ENABLE | TIMER_CASCADE;
}
void timerlen()
{
u32 min = 0xFFFF;
int i = 0;
while(i < 8)
{
if(soundLentimefild[i] != 0)
{
if(1 == soundLentimefild[i])
{
soundLentimefild[i] = 0xFFFFFFFF;
}
else if(0xFFFFFFFF == soundLentimefild[i])
{
//jump
u32 temp5 = lenfunctions[i](i);
if(temp5 != 0)soundLentimefild[i] = temp5 + nexttimelendurchlauf;
else soundLentimefild[i] = 0;
}
else
{
soundLentimefild[i]-= nexttimelen;
if(min > soundLentimefild[i] - 1)
{
min = (soundLentimefild[i] - 1);
}
}
}
i++;
}
nexttimelendurchlauf = nexttimelen;
nexttimelen = min;
min = (min > minval) ? min : minval;
TIMER_DATA(2) = (u32)(0x10000-min);
}
void resetMemory2_ARM9()
{
register int i;
//clear out ARM9 DMA channels
for (i=0; i<4; i++) {
DMA_CR(i) = 0;
DMA_SRC(i) = 0;
DMA_DEST(i) = 0;
TIMER_CR(i) = 0;
TIMER_DATA(i) = 0;
}
VRAM_CR = 0x80808080;
VRAM_E_CR = 0x80;
VRAM_F_CR = 0x80;
VRAM_G_CR = 0x80;
VRAM_H_CR = 0x80;
VRAM_I_CR = 0x80;
// clear vram
u16 * vram = 0x6800000;
zeroMemory(vram, 656 * 1024 );
// clear video palette
zeroMemory( BG_PALETTE, 2048 );//BG_PALETTE[0] = RGB15(1,1,1);
zeroMemory( BG_PALETTE_SUB, 2048 );
// clear video object attribution memory
zeroMemory( OAM, 2048 );
zeroMemory( OAM_SUB, 2048 );
// clear video object data memory
zeroMemory( SPRITE_GFX, 128 * 1024 );
zeroMemory( SPRITE_GFX_SUB, 128 * 1024 );
// clear main display registers
zeroMemory( (void*)0x04000000, 0x6c );
// clear sub display registers
zeroMemory( (void*)0x04001000, 0x6c );
// clear maths registers
zeroMemory( (void*)0x04000280, 0x40 );
REG_DISPSTAT = 0;
videoSetMode(0);
videoSetModeSub(0);
VRAM_A_CR = 0;
VRAM_B_CR = 0;
VRAM_C_CR = 0;
VRAM_D_CR = 0;
VRAM_E_CR = 0;
VRAM_F_CR = 0;
VRAM_G_CR = 0;
VRAM_H_CR = 0;
VRAM_I_CR = 0;
VRAM_CR = 0x03000000;
REG_POWERCNT = 0x820F;
//set shared ram to ARM7
WRAM_CR = 0x03;
}
/*
* initialize clock on timer 0.
*/
void Clock_driver_support_initialize_hardware (void)
{
uint32_t freq =
1000 / (rtems_configuration_get_microseconds_per_tick () / 1000);
printk ("[+] clock started\n");
TIMER_CR (0) = TIMER_ENABLE | TIMER_IRQ_REQ | TIMER_DIV_64;
printk ("[#] setting clock to %u hz\n", freq);
TIMER_DATA (0) = TIMER_FREQ_64 ((uint16_t) freq);
}
void configureTimer() {
// Initialize timer_ticks
timer_ticks = 0;
// Configure timer to trigger an interrupt every 100 ms
TIMER_CR(0) = TIMER_ENABLE | TIMER_DIV_64 | TIMER_IRQ_REQ;
TIMER_DATA(0) = TIMER_FREQ_64(10);
// Associate the ISR (timerISR) to the interrupt line and enable it
irqSet(IRQ_TIMER0, &timerISR);
irqEnable(IRQ_TIMER0);
}
void __attribute__ ((long_call)) resetArm9()
{
int i, reg;
for(i=0; i<4; i++)
{
DMA_CR(i) = 0;//Reset DMA.
DMA_SRC(i) = 0;
DMA_DEST(i) = 0;
TIMER_CR(i) = 0;//Reset timers.
TIMER_DATA(i) = 0;
if(DSi_mode)
{
for(reg=0; reg<0x1c; reg+=4)*((u32*)(0x04004104 + ((i*0x1c)+reg))) = 0;//Reset NDMA.
}
}
VRAM_CR = (VRAM_CR & 0xffff0000) | 0x00008080;//This is from bootloader.
//This DMA gfx reset code is from bootloader boot.c.
dmaFillWords( 0, (void*)0x04000000, 0x56); //clear main display registers
dmaFillWords( 0, (void*)0x04001000, 0x56); //clear sub display registers
REG_DISPSTAT = 0;
REG_DISPCNT = 0;
REG_DISPCNT_SUB = 0;
for(i=0; i<7; i++)//Clear VRAM.
{
if(i==2)continue;
((vu8*)0x04000240)[i] = 0x80;
}
VRAM_H_CR = 0x80;
VRAM_I_CR = 0x80;
memset16((void*)0x6800000, 0, 0xa4000);
for(i=0; i<7; i++)//Reset VRAM.
{
if(i==2)continue;
((vu8*)0x04000240)[i] = 0;
}
VRAM_H_CR = 0;
VRAM_I_CR = 0;
memset((void*)0x05000000, 0, 0x800);//Clear palettes.
memset((void*)0x07000000, 0, 0x800);//Clear OAM.
memset(SPRITE_GFX, 0, 128 * 1024);
memset(SPRITE_GFX_SUB, 0, 128 * 1024);
REG_POWERCNT = 0x820f;
WRAM_CR = 0x03;
REG_EXMEMCNT = 0xE880;
}
void coopTimerStart(int timer, ClockDivider divider, u16 ticks, VoidFn callback)
{
timer &= 3;
TIMER_DATA(timer) = ticks;
if (callback)
{
coopIrqSet(IRQ_TIMER(timer), callback);
irqEnable(IRQ_TIMER(timer));
TIMER_CR(timer) = TIMER_IRQ_REQ | divider | TIMER_ENABLE;
}else
TIMER_CR(timer) = divider | TIMER_ENABLE;
}
ITCM_CODE void resetARM9Memory(void)
{
// DMA & TIMERS
for(u32 ii=0;ii<4;++ii)
{
DMA_CR(ii)=0;
DMA_SRC(ii)=0;
DMA_DEST(ii)=0;
DMA_FILL(ii)=0;
TIMER_CR(ii)=0;
TIMER_DATA(ii)=0;
}
while(REG_DISPSTAT&DISP_IN_VBLANK) ;
while((REG_DISPSTAT&DISP_IN_VBLANK)==0) ; // wait for VBLANK to avoid screen picture break
// VIDEO
VRAM_CR=0x80808080;
VRAM_E_CR=0x80;
VRAM_F_CR=0x80;
VRAM_G_CR=0x80;
VRAM_H_CR=0x80;
VRAM_I_CR=0x80;
zeroMemoryITCM(BG_PALETTE,2048); //0x05000000
zeroMemoryITCM(OAM,2048); //0x07000000
zeroMemoryITCM((void*)0x04000000,0x60);
zeroMemoryITCM((void*)0x04001000,0x60);
zeroMemoryITCM(VRAM,656*1024); //0x06800000..0x068a3fff
VRAM_CR=0x00000000;
VRAM_E_CR=0;
VRAM_F_CR=0;
VRAM_G_CR=0;
VRAM_H_CR=0;
VRAM_I_CR=0;
REG_POWERCNT=0x820f; // turn on all engines
REG_EXMEMCNT=0xe880; // restore memory control
// Interrupt
REG_IE=0;
REG_IF=~0;
REG_IPC_SYNC=0;
#if defined(_STORAGE_ak2i)
*(u32*)0x27ffc00=0x0fc2;
*(u16*)0x27ffc10=0x5835;
#endif
}
//---------------------------------------------------------------------------------
// Reset the DS registers to sensible defaults
//---------------------------------------------------------------------------------
void __attribute__((weak)) initSystem(void) {
//---------------------------------------------------------------------------------
register int i;
// stop timers and dma
for (i=0; i<4; i++)
{
DMA_CR(i) = 0;
DMA_SRC(i) = 0;
DMA_DEST(i) = 0;
TIMER_CR(i) = 0;
TIMER_DATA(i) = 0;
}
// clear video display registers
dmaFillWords(0, (void*)0x04000000, 0x56);
dmaFillWords(0, (void*)0x04001008, 0x56);
videoSetModeSub(0);
vramDefault();
VRAM_E_CR = 0;
VRAM_F_CR = 0;
VRAM_G_CR = 0;
VRAM_H_CR = 0;
VRAM_I_CR = 0;
irqInit();
fifoInit();
fifoSetValue32Handler(FIFO_PM, powerValueHandler, 0);
fifoSetDatamsgHandler(FIFO_SYSTEM, systemMsgHandler, 0);
if(REG_DSIMODE) {
fifoSendValue32(FIFO_PM,PM_DSI_HACK);
__dsimode = true;
}
__transferRegion()->buttons = 0xffff;
punixTime = (time_t*)memUncached((void *)&__transferRegion()->unixTime);
__syscalls.exit = __libnds_exit;
extern char *fake_heap_end;
__transferRegion()->bootcode = (struct __bootstub *)fake_heap_end;
irqEnable(IRQ_VBLANK);
}
//---------------------------------------------------------------------------------
u16 timerElapsed(int timer) {
//---------------------------------------------------------------------------------
sassert(timer < 4, "timer must be in range 0 - 3");
u16 time = TIMER_DATA(timer);
s32 result = (s32)time - (s32)elapsed[timer];
//overflow...this will only be accurate if it has overflowed no more than once.
if(result < 0) {
result = time + (0x10000 - elapsed[timer]);
}
elapsed[timer] = time;
return (u16) result;
}
//---------------------------------------------------------------------------------
void timerStart(int timer, ClockDivider divider, u16 ticks, VoidFn callback){
//---------------------------------------------------------------------------------
sassert(timer < 4, "timer must be in range 0 - 3");
TIMER_DATA(timer) = ticks;
if(callback)
{
irqSet(IRQ_TIMER(timer), callback);
irqEnable(IRQ_TIMER(timer));
TIMER_CR(timer) = TIMER_IRQ_REQ | divider | TIMER_ENABLE;
}
else
{
TIMER_CR(timer) = divider | TIMER_ENABLE;
}
}
void test_core_timer_repeat_01(void)
{
s_clock clock;
t_uint64 start;
i_timer tid;
if (timer_reserve(TIMER_TYPE_FUNCTION,
TIMER_ROUTINE(test_core_timer_repeat_01_handler),
TIMER_DATA(NULL),
1500,
TIMER_OPTION_REPEAT,
&tid) != STATUS_OK)
TEST_ERROR("[timer_reserve] error");
if (clock_current(&clock) != STATUS_OK)
TEST_ERROR("[clock_current] error");
start = CLOCK_UNIQUE(&clock);
if (event_enable() != STATUS_OK)
TEST_ERROR("[event_enable] error");
while (1)
{
t_uint64 current;
if (clock_current(&clock) != STATUS_OK)
TEST_ERROR("[clock_current] error");
current = CLOCK_UNIQUE(&clock);
if (current > (start + 3500))
break;
}
if (event_disable() != STATUS_OK)
TEST_ERROR("[event_disable] error");
if (timed != 2)
TEST_ERROR("the timer has not been triggered twice as expected but %u",
timed);
TEST_SIGNATURE(sdiocvjigi4h4h3);
TEST_LEAVE();
}
void timerlenadd(u8 chan,u32 val,Functiondec func) //val min 0x20000
{
if(val != 0)
{
//val =+ 0x10000-TIMER_DATA(2);
//val =- nexttimelendurchlauf;
soundLentimefild[chan] = 0;
lenfunctions[chan] = func;
val = val + nexttimelendurchlauf-(u32)TIMER_DATA(2);
soundLentimefild[chan] = val;
}
else
{
soundLentimefild[chan] = 0;
}
}
void gzmcpc_init_time(void) {
TIMER0_CR = 0;
// 16khz timer
TIMER_DATA(0) = TIMER_FREQ(16384);
// note: emacs syntax tab auto formatting did this to the line extensions.
TIMER_CR(0) = \
TIMER_ENABLE | \
TIMER_DIV_1 | \
TIMER_IRQ_REQ;
// configure gzmcp tick timer interrupt handler
irqSet(IRQ_TIMER0, ms_timer_handler);
// enable the ms timer irq
irqEnable(IRQ_TIMER0);
}
CpuTickType GetCurrFrameElapsedTicks()
{
//@TODO: Add cpuGetElapsed() that does the following...
return ( (TIMER_DATA(gTimerChannel) | (TIMER_DATA(gTimerChannel+1)<<16) ));
}
//---------------------------------------------------------------------------------
int main(int argc, char ** argv) {
//---------------------------------------------------------------------------------
readUserSettings();
irqInit();
initClockIRQ();
fifoInit();
SetYtrigger(80);
#ifdef USE_WIFI
installWifiFIFO();
#endif
//installSoundFIFO();
installSystemFIFO();
//TIMER_CR(0) = TIMER_ENABLE | TIMER_IRQ_REQ | TIMER_DIV_1;
vcount = 80;
irqSet(IRQ_VBLANK, VblankHandler);
irqSet(IRQ_VCOUNT, VcountHandler);
irqSet(IRQ_HBLANK, hblank_handler);
irqEnable(IRQ_VBLANK | IRQ_VCOUNT | IRQ_HBLANK);
setPowerButtonCB(powerButtonCB);
fifoSetDatamsgHandler(FIFO_9to7, fifo_DataHandler, 0);
// irqSet(IRQ_LID, lid);
// irqEnable(IRQ_LID);
#ifdef IPC_IN_TIMER
irqSet(IRQ_TIMER0, handle_ipc);
TIMER_DATA(0) = TIMER_FREQ_256(20 * 60);
TIMER_CR(0) = TIMER_ENABLE | TIMER_IRQ_REQ | TIMER_DIV_256;
#endif
#ifdef USE_WIFI
#ifndef WIFI_ON_DEMAND
wifi_go();
#endif
#endif
#ifdef USE_ADHOC
IPC_Init() ;
LWIFI_Init() ;
#endif
// Keep the ARM7 idle
while (!exitflag)
{
//ARM7_PRINT("arm7 ");
if ( 0 == (REG_KEYINPUT & (KEY_SELECT | KEY_START | KEY_L | KEY_R))) {
exitflag = true;
}
#ifdef USE_ADHOC
LWIFI_IPC_UpdateNOIRQ() ;
#endif
if (do_mp3 != 0)
{
#ifdef USE_MP3
ds_enable_interrupts(0);
if (helix_initialised == 0)
{
ARM7_PRINT("beginning helix init\n");
helix_init();
ARM7_PRINT("helix init done\n");
helix_initialised = 1;
}
char helix_argv1[100];
char helix_argv2[100];
memset(helix_argv1, 0, 100);
memset(helix_argv2, 0, 100);
strcpy(helix_argv1, "/jones.mp3");
// sprintf(helix_argv1, "/quake soundtrack/0%d-AudioTrack 0%d.mp3", mp3_track_no, mp3_track_no);
// strcpy(helix_argv2, "/jones.pcm");
char *proper_helix_argv[3];
proper_helix_argv[0] = NULL;
proper_helix_argv[1] = helix_argv1;
// proper_helix_argv[1] = (char *)track_name;
proper_helix_argv[2] = helix_argv2;
ARM7_PRINT("Starting Helix...\n");
decoder_stopped = 0;
ds_enable_interrupts(1);
helix_main(3, proper_helix_argv);
ds_enable_interrupts(0);
decoder_stopped = 1;
ARM7_PRINT("out of helix\n");
// ARM7_HALT();
send_mp3_stop_message();
ds_enable_interrupts(1);
#endif
}
// if (REG_KEYXY & (1 << 7))
// {
// while (quake_ipc_7to9->message == 0xffffffff);
//
// quake_ipc_7to9->message_type = kLidHasClosed;
// quake_ipc_7to9->message = 0xffffffff;
//
// while (quake_ipc_7to9->message == 0xffffffff);
//
// ARM7_PRINT("ARM7: waiting...\n");
// while (REG_IPC_FIFO_CR&IPC_FIFO_RECV_EMPTY);
// ARM7_PRINT("ARM7: disabling interrupts\n");
//
// irqDisable(IRQ_HBLANK);
// irqDisable(IRQ_VBLANK);
// irqDisable(IRQ_VCOUNT);
//
//// irqEnable(IRQ_LID);
//
// powerOFF(POWER_SOUND);
//
// swiWaitForVBlank(); //wake up when the lid re-enables the interrupt
// }
if (arm7_initialised && ((hblanks & 0x3f) == 0))
{
arm7_initialised = 1;
//ARM7_PRINT("ping");
//while (quake_ipc_7to9->message == 0xffffffff);
//quake_ipc_7to9->message_type = kPing;
//quake_ipc_7to9->message = 0xffffffff;
//while (quake_ipc_7to9->message == 0xffffffff);
}
// int total = 0;
// for (int count = 0 ; count < 16; count++)
// if (!is_channel_enabled(count))
// total++;
// if (free_time == kFreeTime)
// ARM7_PRINTF("%d channels free\n", total);
// if (free_time == kFreeTime)
// if (needs_defrag())
// {
// ARM7_PRINT("NEEDS DEFRAG\n");
// defrag(&free_time);
// }
// swiWaitForVBlank();
#ifdef IPC_IN_MAIN_THREAD
//handle_ipc();
#endif
// if (arm7_initialised == true)
// {
//// temp_test();
//
// arm7_initialised = false;
// ARM7_PRINT("installing exception handler\n");
// install();
// register unsigned int sp asm ("13");
// ARM7_PRINT("done\nlet\'s try and crash it\n");
// /*ARM7_PRINT_NUMBER(sp);*/
//
//// asm("LDR r12,=MyReg2\n"
//// "STMIA r12,{r0-r15}\n"
//// :
//// :
//// : "r12");
//
//// ARM7_PRINT_NUMBER(MyReg2[12]);
//
//// for (int count = 0; count < 16; count++)
//// ARM7_PRINT_NUMBER(MyReg2[count]);
//// ARM7_PRINT("\n");
//// while(1);
//// asm (".word 0xffffffff");
//// asm (".word 0x0");
//
//
//// Exception();
//
//// asm (".word 0xe6000010");
//
//// asm("LDR r12,=MyReg2\n"
//// "STMIA r12,{r0-r15}\n"
//// :
//// :
//// : "r12");
////
//// for (int count = 0; count < 8; count++)
//// {
//// ARM7_PRINT_NUMBER(MyReg[count + 8]);
//// ARM7_PRINT_NUMBER(MyReg2[count + 8]);
//// }
//
//
//// asm ("mcr 15,0,r0,c0,c0,0");
//// asm ("bkpt");
//// *(int *)0 = 0;
//// asm ("b debugger_hit");
//// debugger_hit();
//// debugger_handle_breakpoint(0,0,0);
//
//// asm (".word 0xe6000010");
//// asm (".short 0xe801");
// ARM7_PRINT("shouldn\'t make it here\n");
// ARM7_PRINT_NUMBER(ProperCPSR);
// while(1);
// }
swiIntrWait(1, 1);
}
}
//---------------------------------------------------------------------------------
int loadNDS(int socket, u32 remote) {
//---------------------------------------------------------------------------------
int len;
int i=0;
ioctl(socket,FIONBIO,&i);
len = recvall(socket,__NDSHeader,512,0);
if (len != 512) {
kprintf("Error reading header.\n");
return 1;
}
int arm7dest = __NDSHeader->arm7destination;
int arm7size = __NDSHeader->arm7binarySize;
int arm9dest = __NDSHeader->arm9destination;
int arm9size = __NDSHeader->arm9binarySize;
volatile int response = 0;
if (arm9dest + arm9size > (int)_start) response = 1;
if (arm7dest >= 0x02000000 && arm7dest < 0x03000000 && arm7dest + arm7size > (int)_start) response = 2;
send(socket,(int *)&response,sizeof(response),0);
if(response) return 1;
kprintf("Reading arm7 binary: ");
if (progressRead(socket,(char *)memUncached((void*)0x02000000),arm7size)) {
kprintf("\nReceive error.\n");
return 1;
}
fifoSendValue32(FIFO_USER_01,1);
while(!fifoCheckValue32(FIFO_USER_01)) {
swiIntrWait(1,IRQ_FIFO_NOT_EMPTY);
}
fifoGetValue32(FIFO_USER_01);
kprintf("Reading arm9 binary: ");
if(progressRead(socket,(char *)arm9dest,arm9size)) {
kprintf("\nReceive error.\n");
return 1;
}
volatile int cmdlen=0;
char *cmdline;
if (arm9size != 0){
cmdline = (char*)(arm9dest+arm9size);
} else {
cmdline = (char*)(arm7dest+arm7size);
}
len = recvall(socket,(char*)&cmdlen,4,0);
if (cmdlen) {
len = recvall(socket,cmdline,cmdlen,0);
__system_argv->argvMagic = ARGV_MAGIC;
__system_argv->commandLine = cmdline;
__system_argv->length = cmdlen;
__system_argv->host = remote;
}
Wifi_DisableWifi();
DC_FlushAll();
REG_IPC_SYNC = 0;
fifoSendValue32(FIFO_USER_01,2);
fifoSendValue32(FIFO_USER_01,__NDSHeader->arm9executeAddress);
irqDisable(IRQ_ALL);
REG_IME = 0;
//clear out ARM9 DMA channels
for (i=0; i<4; i++) {
DMA_CR(i) = 0;
DMA_SRC(i) = 0;
DMA_DEST(i) = 0;
TIMER_CR(i) = 0;
TIMER_DATA(i) = 0;
}
u16 *mainregs = (u16*)0x04000000;
u16 *subregs = (u16*)0x04001000;
for (i=0; i<43; i++) {
mainregs[i] = 0;
subregs[i] = 0;
}
REG_DISPSTAT = 0;
dmaFillWords(0, BG_PALETTE, (2*1024));
VRAM_A_CR = 0x80;
dmaFillWords(0, VRAM, 128*1024);
VRAM_A_CR = 0;
VRAM_B_CR = 0;
// Don't mess with the ARM7's VRAM
// VRAM_C_CR = 0;
VRAM_D_CR = 0;
VRAM_E_CR = 0;
VRAM_F_CR = 0;
VRAM_G_CR = 0;
VRAM_H_CR = 0;
VRAM_I_CR = 0;
REG_POWERCNT = 0x820F;
//set shared ram to ARM7
WRAM_CR = 0x03;
// Return to passme loop
*((vu32*)0x02FFFE04) = (u32)0xE59FF018; // ldr pc, 0x02FFFE24
*((vu32*)0x02FFFE24) = (u32)0x02FFFE04; // Set ARM9 Loop address
REG_IPC_SYNC = 0x500;
arm9Reset();
while(1);
}
extern "C" unsigned short ds_get_loop_timer(void)
{
return TIMER_DATA(2);
}
