void
OMR::CodeGenPhase::performInstructionSelectionPhase(TR::CodeGenerator * cg, TR::CodeGenPhase * phase)
{
TR::Compilation* comp = cg->comp();
phase->reportPhase(InstructionSelectionPhase);
if (comp->getOption(TR_TraceCG) || comp->getOption(TR_TraceTrees) || comp->getOptions()->getTraceCGOption(TR_TraceCGPreInstructionSelection))
comp->dumpMethodTrees("Pre Instruction Selection Trees");
TR::LexicalMemProfiler mp(phase->getName(), comp->phaseMemProfiler());
LexicalTimer pt(phase->getName(), comp->phaseTimer());
cg->doInstructionSelection();
if (comp->getOption(TR_TraceCG) || comp->getOptions()->getTraceCGOption(TR_TraceCGPostInstructionSelection))
comp->getDebug()->dumpMethodInstrs(comp->getOutFile(), "Post Instruction Selection Instructions", false, true);
// check reference counts
#if defined(DEBUG) || defined(PROD_WITH_ASSUMES)
for (int r=0; r<NumRegisterKinds; r++)
{
if (TO_KIND_MASK(r) & cg->getSupportedLiveRegisterKinds())
{
cg->checkForLiveRegisters(cg->getLiveRegisters((TR_RegisterKinds)r));
}
}
#endif
// check interrupt
if (comp->compilationShouldBeInterrupted(AFTER_INSTRUCTION_SELECTION_CONTEXT))
{
comp->failCompilation<TR::CompilationInterrupted>("interrupted after instruction selection");
}
}
TR_GPR = 0,
TR_FPR = 1,
TR_CCR = 2,
TR_X87 = 3,
TR_VRF = 4,
TR_VSX_SCALAR = 5,
TR_VSX_VECTOR = 6,
TR_SSR = 7, // used for TR_PseudoRegisters for SS (storage to storage) instructions to return results
TR_HPR = 8, // High word register for zGryphon
LastRegisterKind = TR_HPR,
NumRegisterKinds = LastRegisterKind+1,
TR_NoRegister = LastRegisterKind+1,
TR_NoKind_Mask = 0,
TR_GPR_Mask = TO_KIND_MASK(TR_GPR),
TR_FPR_Mask = TO_KIND_MASK(TR_FPR),
TR_CCR_Mask = TO_KIND_MASK(TR_CCR),
TR_X87_Mask = TO_KIND_MASK(TR_X87),
TR_VRF_Mask = TO_KIND_MASK(TR_VRF),
TR_VSX_SCALAR_Mask = TO_KIND_MASK(TR_VSX_SCALAR),
TR_VSX_VECTOR_Mask = TO_KIND_MASK(TR_VSX_VECTOR),
TR_SSR_Mask = TO_KIND_MASK(TR_SSR),
TR_HPR_Mask = TO_KIND_MASK(TR_HPR)
};
enum TR_RegisterSizes
{
TR_UnknownSizeReg = -1,
TR_ByteReg = 0,
TR_HalfWordReg = 1,
