static void nve0_graph_mp_trap(struct nvc0_graph_priv *priv, int gpc, int tp) { int i; u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x648)); u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x650)); nv_error(priv, "GPC%i/TP%i/MP trap:", gpc, tp); for (i = 0; i <= 31; ++i) { if (!(gerr & (1 << i))) continue; pr_cont(" "); nouveau_enum_print(nve0_mp_global_error, i); } if (werr) { pr_cont(" "); nouveau_enum_print(nve0_mp_warp_error, werr & 0xffff); } pr_cont("\n"); /* disable MP trap to avoid spam */ nv_mask(priv, TPC_UNIT(gpc, tp, 0x50c), 0x2, 0x0); /* TODO: figure out how to resume after an MP trap */ }
static void gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); }
void gm200_grctx_generate_tpcid(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; for (tpc = 0, id = 0; tpc < TPC_MAX_PER_GPC; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); id++; } } } }
static void gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) { int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { for (gpc = 0; gpc < priv->gpc_nr; gpc++) { if (tpc < priv->tpc_nr[gpc]) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); id++; } nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); } } }
static void nve0_graph_tp_trap(struct nvc0_graph_priv *priv, int gpc, int tp) { u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x508)); if (stat & 0x1) { u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x224)); nv_error(priv, "GPC%i/TP%i/TEX trap: %08x\n", gpc, tp, trap); nv_wr32(priv, TPC_UNIT(gpc, tp, 0x224), 0xc0000000); stat &= ~0x1; } if (stat & 0x2) { nve0_graph_mp_trap(priv, gpc, tp); stat &= ~0x2; } if (stat & 0x4) { u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x084)); nv_error(priv, "GPC%i/TP%i/POLY trap: %08x\n", gpc, tp, trap); nv_wr32(priv, TPC_UNIT(gpc, tp, 0x084), 0xc0000000); stat &= ~0x4; } if (stat & 0x8) { u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x48c)); nv_error(priv, "GPC%i/TP%i/L1C trap: %08x\n", gpc, tp, trap); nv_wr32(priv, TPC_UNIT(gpc, tp, 0x48c), 0xc0000000); stat &= ~0x8; } if (stat) { nv_error(priv, "GPC%i/TP%i: unknown stat %08x\n", gpc, tp, stat); } }
void nvc1_grctx_generate_attrib(struct nvc0_grctx *info) { struct nvc0_graph_priv *priv = info->priv; const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; int gpc, tpc; mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_wr32(info, 0x405830, (beta << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { const u32 a = alpha; const u32 b = beta; const u32 t = timeslice_mode; const u32 o = TPC_UNIT(gpc, tpc, 0x500); mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo); mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo); bo += impl->attrib_nr_max; mmio_wr32(info, o + 0x44, (a << 16) | ao); ao += impl->alpha_nr_max; } } }
int nve4_graph_init(struct nouveau_object *object) { struct nvc0_graph_oclass *oclass = (void *)object->oclass; struct nvc0_graph_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; ret = nouveau_graph_init(&priv->base); if (ret) return ret; nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); nvc0_graph_mmio(priv, oclass->mmio); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { do { gpc = (gpc + 1) % priv->gpc_nr; } while (!tpcnr[gpc]); tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nv_wr32(priv, GPC_BCAST(0x0980), data[0]); nv_wr32(priv, GPC_BCAST(0x0984), data[1]); nv_wr32(priv, GPC_BCAST(0x0988), data[2]); nv_wr32(priv, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); } nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); nv_wr32(priv, 0x409ffc, 0x00000000); nv_wr32(priv, 0x409c14, 0x00003e3e); nv_wr32(priv, 0x409c24, 0x000f0001); nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404600, 0xc0000000); nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < priv->rop_nr; rop++) { nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); nv_wr32(priv, 0x400118, 0xffffffff); nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); nv_wr32(priv, 0x400054, 0x34ce3464); return nvc0_graph_init_ctxctl(priv); }
int gm107_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_fb *fb = device->fb; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); gf100_gr_mmio(gr, gr->func->mmio); gm107_gr_init_bios(gr); nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); gr->func->init_rop_active_fbps(gr); nvkm_wr32(device, 0x400500, 0x00010001); nvkm_wr32(device, 0x400100, 0xffffffff); nvkm_wr32(device, 0x40013c, 0xffffffff); nvkm_wr32(device, 0x400124, 0x00000002); nvkm_wr32(device, 0x409c24, 0x000e0000); nvkm_wr32(device, 0x404000, 0xc0000000); nvkm_wr32(device, 0x404600, 0xc0000000); nvkm_wr32(device, 0x408030, 0xc0000000); nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x406018, 0xc0000000); nvkm_wr32(device, 0x407020, 0x40000000); nvkm_wr32(device, 0x405840, 0xc0000000); nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); gr->func->init_ppc_exceptions(gr); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } nvkm_wr32(device, 0x400108, 0xffffffff); nvkm_wr32(device, 0x400138, 0xffffffff); nvkm_wr32(device, 0x400118, 0xffffffff); nvkm_wr32(device, 0x400130, 0xffffffff); nvkm_wr32(device, 0x40011c, 0xffffffff); nvkm_wr32(device, 0x400134, 0xffffffff); nvkm_wr32(device, 0x400054, 0x2c350f63); gf100_gr_zbc_init(gr); return gf100_gr_init_ctxctl(gr); }
int gm204_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; u32 tmp; ret = nvkm_gr_init(&priv->base); if (ret) return ret; tmp = nv_rd32(priv, 0x100c80); /*XXX: mask? */ nv_wr32(priv, 0x418880, 0x00001000 | (tmp & 0x00000fff)); nv_wr32(priv, 0x418890, 0x00000000); nv_wr32(priv, 0x418894, 0x00000000); nv_wr32(priv, 0x4188b4, priv->unk4188b4->addr >> 8); nv_wr32(priv, 0x4188b8, priv->unk4188b8->addr >> 8); nv_mask(priv, 0x4188b0, 0x00040000, 0x00040000); /*XXX: belongs in fb */ nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); nv_mask(priv, 0x100cc4, 0x00040000, 0x00040000); gf100_gr_mmio(priv, oclass->mmio); gm107_gr_init_bios(priv); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { do { gpc = (gpc + 1) % priv->gpc_nr; } while (!tpcnr[gpc]); tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nv_wr32(priv, GPC_BCAST(0x0980), data[0]); nv_wr32(priv, GPC_BCAST(0x0984), data[1]); nv_wr32(priv, GPC_BCAST(0x0988), data[2]); nv_wr32(priv, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); } nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, GPC_BCAST(0x033c), nv_rd32(priv, 0x100804)); nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); nv_wr32(priv, 0x400124, 0x00000002); nv_wr32(priv, 0x409c24, 0x000e0000); nv_wr32(priv, 0x405848, 0xc0000000); nv_wr32(priv, 0x40584c, 0x00000001); nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404600, 0xc0000000); nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < priv->rop_nr; rop++) { nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); nv_wr32(priv, 0x400118, 0xffffffff); nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); nv_wr32(priv, 0x400054, 0x2c350f63); gf100_gr_zbc_init(priv); return gm204_gr_init_ctxctl(priv); }