string vcSystem::Print_VHDL_Pipe_Ports(string semi_colon, ostream& ofile)
{
for(map<string, vcPipe*>::iterator pipe_iter = _pipe_map.begin();
pipe_iter != _pipe_map.end();
pipe_iter++)
{
vcPipe* p =(*pipe_iter).second;
string pipe_id = To_VHDL(p->Get_Id());
int pipe_width = p->Get_Width();
int num_reads = p->Get_Pipe_Read_Count();
int num_writes = p->Get_Pipe_Write_Count();
if(num_reads > 0 && num_writes == 0)
{
// input pipe
ofile << semi_colon << endl;
semi_colon = ";";
ofile << pipe_id << "_pipe_write_data: in std_logic_vector(" << pipe_width-1 << " downto 0);" << endl;
ofile << pipe_id << "_pipe_write_req : in std_logic_vector(0 downto 0);" << endl;
ofile << pipe_id << "_pipe_write_ack : out std_logic_vector(0 downto 0)";
}
if(num_writes > 0 && num_reads == 0)
{
// output
ofile << semi_colon << endl;
semi_colon = ";";
ofile << pipe_id << "_pipe_read_data: out std_logic_vector(" << pipe_width-1 << " downto 0);" << endl;
ofile << pipe_id << "_pipe_read_req : in std_logic_vector(0 downto 0);" << endl;
ofile << pipe_id << "_pipe_read_ack : out std_logic_vector(0 downto 0)";
}
}
return(semi_colon);
}
virtual string Get_VHDL_Id() {return(To_VHDL(this->Get_Id()));}
