#include "ucg.h"
//static const uint8_t ucg_dev_ssd1351_128x128_init_seq[] PROGMEM = {
static const ucg_pgm_uint8_t ucg_tft_240x320_ili9341_init_seq[] = {
UCG_CFG_CD(0,1), /* DC=0 for command mode, DC=1 for data and args */
UCG_RST(1),
UCG_CS(1), /* disable chip */
UCG_DLY_MS(5),
UCG_RST(0),
UCG_DLY_MS(5),
UCG_RST(1),
UCG_DLY_MS(50),
UCG_CS(0), /* enable chip */
UCG_C10(0x011), /* sleep out */
UCG_DLY_MS(10),
//UCG_C10(0x038), /* idle mode off */
UCG_C10(0x013), /* normal display on */
//UCG_C14(0x0ed, 0x055, 0x001, 0x023, 0x001), /* power on sequence control (POR values) */
//UCG_C11(0x0f7, 0x020), /* pump ratio control (POR value) */
UCG_C10(0x20), /* not inverted */
//UCG_C10(0x21), /* inverted */
UCG_C11(0x03a, 0x066), /* set pixel format to 18 bit */
//UCG_C11(0x03a, 0x055), /* set pixel format to 16 bit */
//UCG_C12(0x0b1, 0x000, 0x01b), /* frame rate control (POR values) */
#include "ucg.h"
//static const uint8_t ucg_dev_ssd1351_132x132_init_seq[] PROGMEM = {
static const ucg_pgm_uint8_t ucg_tft_132x132_pcf8833_init_seq_OBSOLETE[] = {
UCG_CFG_CD(0,1), /* DC=0 for command mode, DC=1 for data and args */
UCG_RST(1),
UCG_CS(1), /* disable chip */
UCG_DLY_MS(5),
UCG_RST(0),
UCG_DLY_MS(5),
UCG_RST(1),
UCG_DLY_MS(50),
UCG_CS(0), /* enable chip */
UCG_C10(0x01), /* reset */
UCG_DLY_MS(199),
UCG_C10(0x011), /* sleep out */
UCG_DLY_MS(10),
UCG_C10(0x038), /* idle mode off */
//UCG_C10(0x0b5), /* mirror */
//UCG_C10(0x0b7), /* mirror */
UCG_C10(0x013), /* normal display on */
UCG_C10(0x020), /* not inverted */
UCG_C10(0x029), /* display on */
UCG_C11(0x025, 0x03f), /* set contrast -64 ... 63 */
#include "ucg.h"
static const ucg_pgm_uint8_t ucg_univision_ssd1331_init_seq[] = {
UCG_CFG_CD(0,0), /* First arg: level for commands, Second arg: level for command arguments */
UCG_RST(1),
UCG_CS(1), /* disable chip */
UCG_DLY_MS(1),
UCG_RST(0),
UCG_DLY_MS(1),
UCG_RST(1),
UCG_DLY_MS(50),
UCG_CS(0), /* enable chip */
//UCG_C11(0x0fd, 0x012), /* Unlock normal commands, reset default: unlocked */
UCG_C10(0x0ae), /* Set Display Off */
//UCG_C10(0x0af), /* Set Display On */
UCG_C11(0x0a0, 0x0b2), /* 65k format 2, RGB Mode */
UCG_C11(0x0a1, 0x000), /* Set Display Start Line */
UCG_C11(0x0a2, 0x000), /* Set Display Offset */
UCG_C11(0x0a8, 0x03f), /* Multiplex, reset value = 0x03f */
UCG_C11(0x0ad, 0x08e), /* select supply (must be set before 0x0af) */
UCG_C11(0x0b0, 0x00b), /* Disable power save mode */
UCG_C11(0x0b1, 0x031), /* Set Phase Length, reset default: 0x74 */
UCG_C11(0x0b3, 0x0f0), /* Display Clock Divider/Osc, reset value=0x0d0 */
UCG_C12(0x015, 0x000, 0x05f), /* Set Column Address */
UCG_C12(0x075, 0x000, 0x03f), /* Set Row Address */
UCG_C11(0x081, 0x080), /* contrast red, Adafruit: 0x091, UC9664: 0x080 */
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "ucg.h"
const ucg_pgm_uint8_t ucg_st7735_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11( 0x036, 0x000),
UCG_C10(0x02a), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), UCG_A2(0x000, 0x07f), /* set x position */
UCG_C10(0x02b), UCG_VARY(0,0x00, 0), UCG_VARY(0,0x0ff, 0), UCG_A2(0x000, 0x09f), /* set y position */
UCG_C10(0x02c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_st7735_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
/* 0x000 horizontal increment (dir = 0) */
/* 0x000 vertical increment (dir = 1) */
/* 0x040 horizontal deccrement (dir = 2) */
/* 0x080 vertical deccrement (dir = 3) */
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "ucg.h"
const ucg_pgm_uint8_t ucg_ili9163_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11( 0x036, 0x008),
UCG_C10(0x02a), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), UCG_D2(0x000, 0x07f), /* set x position */
UCG_C10(0x02b), UCG_VARY(0,0x00, 0), UCG_VARY(0,0x0ff, 0), UCG_D2(0x000, 0x0a1), /* set y position */
UCG_C10(0x02c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_ili9163_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
/* 0x008 horizontal increment (dir = 0) */
/* 0x008 vertical increment (dir = 1) */
/* 0x048 horizontal deccrement (dir = 2) */
/* 0x088 vertical deccrement (dir = 3) */
//static const uint8_t ucg_dev_ssd1351_128x128_init_seq[] PROGMEM = {
static const ucg_pgm_uint8_t ucg_ilsoft_ssd1351_init_seq[] = {
UCG_CFG_CD(0,1), /* DC=0 for command mode, DC=1 for data and args */
UCG_RST(1),
UCG_CS(1), /* disable chip */
UCG_DLY_MS(1),
UCG_RST(0),
UCG_DLY_MS(1),
UCG_RST(1),
UCG_DLY_MS(50),
UCG_CS(0), /* enable chip */
//UCG_C11(0x0fd, 0x012), /* Unlock normal commands, reset default: unlocked */
UCG_C11(0x0fd, 0x0b1), /* Unlock extra commands, reset default: locked */
//UCG_C10(0x0ae), /* Set Display Off */
UCG_C10(0x0af), /* Set Display On */
UCG_C10(0x0a6), /* Set Display Mode Reset */
UCG_C11(0x0a0, 0x0b4), /* Set Colour Depth */
UCG_C11(0x0a1, 0x000), /* Set Display Start Line */
UCG_C11(0x0a2, 0x000), /* Set Display Offset */
UCG_C12(0x015, 0x000, 0x07f), /* Set Column Address */
UCG_C12(0x075, 0x000, 0x07f), /* Set Row Address */
UCG_C11(0x0b3, 0x0f1), /* Front Clock Div */
//UCG_C11(0x0ca, 0x07f), /* Set Multiplex Ratio, reset default: 0x7f */
UCG_C11(0x0b5, 0x000), /* Set GPIO */
//UCG_C11(0x0ab, 0x001), /* Set Function Selection, reset default: 0x01 */
UCG_C11(0x0b1, 0x032), /* Set Phase Length, reset default: 0x82 */
UCG_C13(0x0b4, 0xa0,0xb5,0x55), /* Set Segment Low Voltage, reset default: 0xa2 0xb5 0x55 */
//UCG_C11(0x0bb, 0x017), /* Set Precharge Voltage, reset default: 0x17 */
//UCG_C11(0x0be, 0x005), /* Set VComH Voltage, reset default: 0x05 */
Bit 0-2: Direction
0x05, 0x00 dir 0
0x05, 0x05 dir 1
0x05, 0x03 dir 2
0x05, 0x06 dir 3
Data Reading/Writing Box: 0x0a
8 bytes as arguments: xs, ys, xe, ye
*/
const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11(0x05, 0x00),
UCG_C10(0x0a), UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f), /* set x position */
UCG_VARY(4,0x0f, 0), UCG_VARY(0,0x0f, 0), UCG_A2(0x09, 0x0f), /* set y position */
UCG_C10(0x0c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11(0x05, 0x00),
UCG_C10(0x0a),
UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f), /* set x position */
UCG_VARY(4,0x0f, 0), UCG_VARY(0,0x0f, 0), UCG_A2(0x09, 0x0f), /* set y position */
//UCG_C10(0x022),
UCG_CS(1), /* disable chip */
//UCG_DATA(),
UCG_END(), /* end of sequence */
};
static const ucg_pgm_uint8_t ucg_seps255_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11(0x016, 0x066), /* Memory Mode */
UCG_C11(0x020, 0), /* set x position */
UCG_C11(0x021, 0), /* set y position */
UCG_C10(0x022), /* prepare for data */
UCG_DATA(), /* change to data mode */
UCG_END()
};
ucg_int_t ucg_dev_seps225_16x128x128_univision(ucg_t *ucg, ucg_int_t msg, void *data)
{
switch(msg)
{
case UCG_MSG_DEV_POWER_UP:
/* 1. Call to the controller procedures to setup the com interface */
if ( ucg_dev_ic_seps225_16(ucg, msg, data) == 0 )
return 0;
/* 2. Send specific init sequence for this display module */
ucg_com_SendCmdSeq(ucg, ucg_univision_seps225_init_seq);
//UCG_C12( 0x06a, 0x000, 0x000), /* Vertical Scroll Control */
//UCG_C12( 0x080, 0x000, 0x000), /* Partial Image 1 Display Position */
//UCG_C12( 0x081, 0x000, 0x000), /* Partial Image 1 RAM Start Address */
//UCG_C12( 0x082, 0x000, 0x000), /* Partial Image 1 RAM End Address */
//UCG_C12( 0x083, 0x000, 0x000), /* Partial Image 2 Display Position */
//UCG_C12( 0x084, 0x000, 0x000), /* Partial Image 2 RAM Start Address */
//UCG_C12( 0x085, 0x000, 0x000), /* Partial Image 2 RAM End Address */
UCG_C12( 0x090, 0x000, 0x010), /* Panel Interface Control 1 */
UCG_C12( 0x092, 0x000, 0x000), /* Panel Interface Control 2 */
/* 0x006, 0x000 */
UCG_C12( 0x007, 0x001, 0x033), /* Display Control 1: Operate, display ON, Partial image off */
UCG_DLY_MS(10), /* delay 10 ms */
/* write test pattern */
//UCG_C12( 0x020, 0x000, 0x000), /* Horizontal GRAM Address Set */
//UCG_C12( 0x021, 0x000, 0x011), /* Vertical GRAM Address Set */
UCG_C10( 0x022), /* Write Data to GRAM */
UCG_CS(1), /* disable chip */
UCG_END(), /* end of sequence */
};
ucg_int_t ICACHE_FLASH_ATTR ucg_dev_ili9325_spi_18x240x320(ucg_t *ucg, ucg_int_t msg, void *data)
{
switch(msg)
{
case UCG_MSG_DEV_POWER_UP:
/* 1. Call to the controller procedures to setup the com interface */
if ( ucg_dev_ic_ili9325_spi_18(ucg, msg, data) == 0 )
return 0;
/* 2. Send specific init sequence for this display module */
