UCG_DLY_MS(50),
  UCG_CS(0),					/* enable chip */
  
  UCG_C10(0x011),				/* sleep out */
  UCG_DLY_MS(10),
  //UCG_C10(0x038),				/* idle mode off */
  UCG_C10(0x013),				/* normal display on */

  //UCG_C14(0x0ed, 0x055, 0x001, 0x023, 0x001), 	/* power on sequence control (POR values) */
  //UCG_C11(0x0f7, 0x020), 		/* pump ratio control (POR value) */
  

  UCG_C10(0x20), 				/* not inverted */
  //UCG_C10(0x21), 				/* inverted */

  UCG_C11(0x03a, 0x066), 		/* set pixel format to 18 bit */
  //UCG_C11(0x03a, 0x055), 		/* set pixel format to 16 bit */

  //UCG_C12(0x0b1, 0x000, 0x01b), 	/* frame rate control (POR values) */

  UCG_C14(0x0b6, 0x00a, 0x082 | (1<<5), 0x027, 0x000), 	/* display function control (POR values, except for shift direction bit) */
  
  //UCG_C11(0x0b7, 0x006), 		/* entry mode, bit 0: Low voltage detection control (0=off) */

  UCG_C11(0x0c0, 0x021), 		/* power control 1 (reference voltage level), POR=21 */
  UCG_C11(0x0c1, 0x002), 		/* power control 2 (step up factor), POR=2 */
  UCG_C11(0x0c7, 0x0c0), 		/* VCOM control 2, enable VCOM control 1 */
  UCG_C12(0x0c5, 0x031, 0x03c), 	/* VCOM control 1, POR=31,3C */
  
  UCG_C15(0x0cb, 0x039, 0x02c, 0x000, 0x034, 0x002), 	/* power control A (POR values) */
  UCG_C13(0x0cf, 0x000, 0x081, 0x030), 	/* power control B (POR values) */
  UCG_C10(0x01),				/* reset */
  UCG_DLY_MS(199),
  
  UCG_C10(0x011),				/* sleep out */
  UCG_DLY_MS(10),
  
  UCG_C10(0x038),				/* idle mode off */
  
  //UCG_C10(0x0b5),				/* mirror */
  //UCG_C10(0x0b7),				/* mirror */
  
  UCG_C10(0x013),				/* normal display on */
  UCG_C10(0x020), 				/* not inverted */
  UCG_C10(0x029), 				/* display on */

  UCG_C11(0x025, 0x03f), 		/* set contrast  -64 ... 63 */

  
  //UCG_C11(0x03a, 0x003), 		/* set pixel format to 12 bit per pixel */
  UCG_C11(0x03a, 0x005), 		
  
  //UCG_C10(0x003), 				/* booster on */
  
  UCG_C10(0x023),				/* all pixel on */
  UCG_DLY_MS(199),
  UCG_C10(0x013),				/* normal display on */

  UCG_C11( 0x036, 0x000),		/* memory control */

  UCG_C12(  0x02a, 0x000, 0x07f),              /* Horizontal GRAM Address Set */
  UCG_C12(  0x02b, 0x000, 0x07f),              /* Vertical GRAM Address Set */
  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  

*/

#include "ucg.h"


const ucg_pgm_uint8_t ucg_st7735_set_pos_seq[] = 
{
  UCG_CS(0),					/* enable chip */
  UCG_C11( 0x036, 0x000),
  UCG_C10(0x02a),	UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), UCG_A2(0x000, 0x07f),					/* set x position */
  UCG_C10(0x02b),	UCG_VARY(0,0x00, 0), UCG_VARY(0,0x0ff, 0), UCG_A2(0x000, 0x09f),		/* set y position */
  UCG_C10(0x02c),							/* write to RAM */
  UCG_DATA(),								/* change to data mode */
  UCG_END()
};


const ucg_pgm_uint8_t ucg_st7735_set_pos_dir0_seq[] = 
{
  UCG_CS(0),					/* enable chip */
  
  /* 0x000 horizontal increment (dir = 0) */
  /* 0x000 vertical increment (dir = 1) */
  /* 0x040 horizontal deccrement (dir = 2) */
static const ucg_pgm_uint8_t ucg_univision_ssd1331_init_seq[] = {
	UCG_CFG_CD(0,0),				/* First arg: level for commands, Second arg: level for command arguments */
  	UCG_RST(1),					
	UCG_CS(1),					/* disable chip */
	UCG_DLY_MS(1),
  	UCG_RST(0),					
	UCG_DLY_MS(1),
  	UCG_RST(1),
	UCG_DLY_MS(50),
	UCG_CS(0),					/* enable chip */
  
	//UCG_C11(0x0fd, 0x012),			/* Unlock normal commands, reset default: unlocked */
	UCG_C10(0x0ae),				/* Set Display Off */
  	//UCG_C10(0x0af),				/* Set Display On */
  	UCG_C11(0x0a0, 0x0b2),			/* 65k format 2, RGB Mode */
  	UCG_C11(0x0a1, 0x000),			/* Set Display Start Line */
  	UCG_C11(0x0a2, 0x000),			/* Set Display Offset */
  	UCG_C11(0x0a8, 0x03f),			/* Multiplex, reset value = 0x03f  */
  	UCG_C11(0x0ad, 0x08e),			/* select supply (must be set before 0x0af) */
  
  	UCG_C11(0x0b0, 0x00b),		/* Disable power save mode */
  	UCG_C11(0x0b1, 0x031),		/* Set Phase Length, reset default: 0x74 */
  	UCG_C11(0x0b3, 0x0f0),			/* Display Clock Divider/Osc, reset value=0x0d0 */

  	UCG_C12(0x015, 0x000, 0x05f),	/* Set Column Address */
  	UCG_C12(0x075, 0x000, 0x03f),	/* Set Row Address */

  	UCG_C11(0x081, 0x080),		/* contrast red, Adafruit: 0x091, UC9664: 0x080 */
  	UCG_C11(0x082, 0x080),		/* contrast green, Adafruit: 0x050, UC9664: 0x080 */
  	UCG_C11(0x083, 0x080),		/* contrast blue, Adafruit: 0x07d, UC9664: 0x080  */
#include "ucg.h"

//static const uint8_t ucg_dev_ssd1351_128x128_init_seq[] PROGMEM = {
static const ucg_pgm_uint8_t ucg_ilsoft_ssd1351_init_seq[] = {
	UCG_CFG_CD(0,1),				/* DC=0 for command mode, DC=1 for data and args */
  	UCG_RST(1),					
	UCG_CS(1),					/* disable chip */
	UCG_DLY_MS(1),
  	UCG_RST(0),					
	UCG_DLY_MS(1),
  	UCG_RST(1),
	UCG_DLY_MS(50),
	UCG_CS(0),					/* enable chip */
	//UCG_C11(0x0fd, 0x012),			/* Unlock normal commands, reset default: unlocked */
	UCG_C11(0x0fd, 0x0b1),			/* Unlock extra commands, reset default: locked */
  
	//UCG_C10(0x0ae),				/* Set Display Off */
  	UCG_C10(0x0af),				/* Set Display On */
	UCG_C10(0x0a6),				/* Set Display Mode Reset */
  	UCG_C11(0x0a0, 0x0b4),			/* Set Colour Depth */
  	UCG_C11(0x0a1, 0x000),			/* Set Display Start Line */
  	UCG_C11(0x0a2, 0x000),			/* Set Display Offset */
  	UCG_C12(0x015, 0x000, 0x07f),	/* Set Column Address */
  	UCG_C12(0x075, 0x000, 0x07f),	/* Set Row Address */

  	UCG_C11(0x0b3, 0x0f1),			/* Front Clock Div */
  	//UCG_C11(0x0ca, 0x07f),			/* Set Multiplex Ratio, reset default: 0x7f */
  	UCG_C11(0x0b5, 0x000),		/* Set GPIO */
  	//UCG_C11(0x0ab, 0x001),			/* Set Function Selection, reset default: 0x01  */
  	UCG_C11(0x0b1, 0x032),		/* Set Phase Length, reset default: 0x82 */
  Bit 3: RGB/BGR
  Bit 0-2: Direction
    0x05, 0x00		dir 0
    0x05, 0x05		dir 1
    0x05, 0x03		dir 2
    0x05, 0x06		dir 3
  
  Data Reading/Writing Box: 0x0a
    8 bytes as arguments: xs, ys, xe, ye
    
*/

const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_seq[] = 
{
  UCG_CS(0),					/* enable chip */
  UCG_C11(0x05, 0x00),
  UCG_C10(0x0a), UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f),					/* set x position */
  UCG_VARY(4,0x0f, 0), UCG_VARY(0,0x0f, 0), UCG_A2(0x09, 0x0f),		/* set y position */
  UCG_C10(0x0c),							/* write to RAM */
  UCG_DATA(),								/* change to data mode */
  UCG_END()
};


const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_dir0_seq[] = 
{
  UCG_CS(0),					/* enable chip */
  
  UCG_C11(0x05, 0x00),
  UCG_C10(0x0a), 
    UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f),					/* set x position */
#include "ucg.h"

/* the following code is from the UG2828GDEAF02 Datasheet */
static const ucg_pgm_uint8_t aaa_ucg_univision_seps225_init_seq[] = {
	UCG_CFG_CD(0,1),				/* First arg: level for commands, Second arg: level for command arguments */
  	UCG_RST(1),					
	UCG_CS(1),					/* disable chip */
	UCG_DLY_MS(1),
  	UCG_RST(0),					
	UCG_DLY_MS(1),
  	UCG_RST(1),
	UCG_DLY_MS(50),
	UCG_CS(0),					/* enable chip */
  
  	UCG_C11(0x002, 0x001),		/* OSC_CTL: external resistor, internal OSC */
  	UCG_C11(0x004, 0x000),		/* REDUCE_CURRENT: normal operation, no current reduction */
  	UCG_C11(0x003, 0x030),		/* CLK_DIV: 90Hz, ratio 1 */
  
  	UCG_C11(0x008, 0x000),		/* Precharge time red */
  	UCG_C11(0x009, 0x000),		/* Precharge time green */
  	UCG_C11(0x00a, 0x000),			/* Precharge time blue */

  	UCG_C11(0x00b, 0x000),		/* Precharge current red */
  	UCG_C11(0x00c, 0x000),			/* Precharge current green */
  	UCG_C11(0x00d, 0x000),		/* Precharge current blue */


  	UCG_C11(0x010, 0x04a),			/* Driving current red */
  	UCG_C11(0x011, 0x025),		/* Driving current green, original value 0x011 replaced by 0x025 */
  	UCG_C11(0x012, 0x02f),			/* Driving current blue */