void initClocks()
{
// Set core power mode
PMM_setVCore(PMM_CORE_LEVEL_3);
// Configure pins for crystals
GPIO_setAsPeripheralModuleFunctionInputPin(
GPIO_PORT_P5,
GPIO_PIN4+GPIO_PIN2
);
GPIO_setAsPeripheralModuleFunctionOutputPin(
GPIO_PORT_P5,
GPIO_PIN5+GPIO_PIN3
);
// Inform the system of the crystal frequencies
UCS_setExternalClockSource(
XT1_FREQ, // Frequency of XT1 in Hz.
XT2_FREQ // Frequency of XT2 in Hz.
);
// Initialize the crystals
UCS_turnOnXT2( // used to be UCS_XT2Start in previous driverlib version
UCS_XT2_DRIVE_4MHZ_8MHZ
);
UCS_turnOnLFXT1( //used to be UCS_LFXT1Start in previous driverlib version
UCS_XT1_DRIVE_0,
UCS_XCAP_3
);
UCS_initClockSignal(
UCS_FLLREF, // The reference for Frequency Locked Loop
UCS_XT2CLK_SELECT, // Select XT2
UCS_CLOCK_DIVIDER_4 // The FLL reference will be 1 MHz (4MHz XT2/4)
);
// Start the FLL and let it settle
// This becomes the MCLCK and SMCLK automatically
UCS_initFLLSettle(
MCLK_FREQ_KHZ,
MCLK_FLLREF_RATIO
);
// Optional: set SMCLK to something else than full speed
UCS_initClockSignal(
UCS_SMCLK,
UCS_DCOCLKDIV_SELECT,
UCS_CLOCK_DIVIDER_1
);
// Set auxiliary clock
UCS_initClockSignal(
UCS_ACLK,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
}
void clock_init(clock_speed_t speed) {
// Turn on XT1 crystal
#ifndef USE_DRIVERLIB
P5SEL |= BIT4;
UCSCTL6 |= XCAP_3; // Internal load cap of 12pF
do { // Wait until XT1 stabilizes
UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); // Clear XT1 fault flag
//
// The DCO fault flag is also cleared,
// since it is supposed to be faulty at startup
// and thus OFIFG will continue to be set unless
// we clear it...
SFRIFG1 &= ~OFIFG; // Clear oscillator fault flag
} while (SFRIFG1 & OFIFG); // Re-test oscillator fault flag
UCSCTL6 &= ~XT1DRIVE_3; // Decrease XT1 drive as it is stabilized
#else
GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5, GPIO_PIN4);
UCS_turnOnLFXT1(XT1DRIVE_0, UCS_XCAP_3);
#endif
// Set the FLL reference select to XT1 (external 32KHz clock),
// and set the FLL reference divider to 1
#ifndef USE_DRIVERLIB
UCSCTL3 = SELREF__XT1CLK | FLLREFDIV_0;
// Set the MCLK source to DCOCLKDIV
UCSCTL4 = (UCSCTL4 & ~SELM_7) | SELM__DCOCLKDIV;
// Set the SMCLK source to DCOCLKDIV
UCSCTL4 = (UCSCTL4 & ~SELS_7) | SELS__DCOCLKDIV;
#else
UCS_initClockSignal(
UCS_FLLREF,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1);
#endif
// Initialize the FLL
#ifndef USE_DRIVERLIB
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
uint16_t ratio;
switch (speed) {
case CLKSPEED_16MHZ:
clock_speed = 16000000;
ratio = clock_speed/XT1_FREQ;
UCSCTL1 = DCORSEL_6;
UCSCTL2 = FLLD_1 | (ratio - 1); // FLLD doesn't really matter, since we feed MCLK and SMCLK off DCOCLKDIV and not DCOCLK
break;
case CLKSPEED_1MHZ:
clock_speed = 1000000;
ratio = clock_speed/XT1_FREQ;
UCSCTL1 = DCORSEL_2;
UCSCTL2 = FLLD_1 | (ratio - 1); // FLLD doesn't really matter, since we feed MCLK and SMCLK off DCOCLKDIV and not DCOCLK
break;
}
__bic_SR_register(SCG0); // Enable the FLL control loop
do { // Wait until DCO stabilizes
UCSCTL7 &= ~(DCOFFG); // Clear DCO fault flag
SFRIFG1 &= ~OFIFG; // Clear oscillator fault flag
} while (SFRIFG1 & OFIFG); // Re-test oscillator fault flag
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
while (ratio--)
__delay_cycles(32*32);
#else
switch (speed) {
case CLKSPEED_16MHZ:
clock_speed = 16000000;
break;
case CLKSPEED_1MHZ:
clock_speed = 1000000;
break;
}
UCS_initFLLSettle(clock_speed/1000, clock_speed/XT1_FREQ);
#endif
}
