static int open_clock(struct sw_hci_hcd *sw_hci, u32 ohci)
{
DMSG_INFO("[%s]: open clock\n", sw_hci->hci_name);
if (sw_hci->sie_clk && sw_hci->phy_gate
&& sw_hci->phy_reset && !sw_hci->clk_is_open) {
sw_hci->clk_is_open = 1;
clk_enable(sw_hci->phy_gate);
clk_enable(sw_hci->phy_reset);
clk_reset(sw_hci->phy_reset, 0);
if (ohci && sw_hci->ohci_gate)
clk_enable(sw_hci->ohci_gate);
mdelay(10);
clk_enable(sw_hci->sie_clk);
mdelay(10);
UsbPhyInit(sw_hci->usbc_no);
} else {
DMSG_PANIC
("[%s]: wrn: open clock failed, (0x%p, 0x%p, 0x%p, %d, 0x%p)\n",
sw_hci->hci_name, sw_hci->sie_clk, sw_hci->phy_gate,
sw_hci->phy_reset, sw_hci->clk_is_open, sw_hci->ohci_gate);
}
dbg_clocks(sw_hci);
return 0;
}
/*
*******************************************************************************
* open_usb_clock
*
* Description:
*
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
u32 open_usb_clock(sw_udc_io_t *sw_udc_io)
{
DMSG_INFO_UDC("open_usb_clock\n");
if(sw_udc_io->sie_clk && sw_udc_io->phy_clk && sw_udc_io->phy0_clk && !sw_udc_io->clk_is_open){
clk_enable(sw_udc_io->sie_clk);
mdelay(10);
clk_enable(sw_udc_io->phy_clk);
clk_enable(sw_udc_io->phy0_clk);
clk_reset(sw_udc_io->phy0_clk, 0);
mdelay(10);
sw_udc_io->clk_is_open = 1;
}else{
DMSG_PANIC("ERR: clock handle is null, sie_clk(0x%p), phy_clk(0x%p), phy0_clk(0x%p), open(%d)\n",
sw_udc_io->sie_clk, sw_udc_io->phy_clk, sw_udc_io->phy0_clk, sw_udc_io->clk_is_open);
}
UsbPhyInit(0);
#if 0
DMSG_INFO("[udc0]: open, 0x60(0x%x), 0xcc(0x%x)\n",
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
#endif
return 0;
}
/*
*******************************************************************************
* open_clock
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static int open_clock(struct sw_hci_hcd *sw_hci, u32 ohci)
{
DMSG_INFO("[%s]: open clock\n", sw_hci->hci_name);
if(sw_hci->sie_clk && sw_hci->phy_gate
&& sw_hci->phy_reset && !sw_hci->clk_is_open){
sw_hci->clk_is_open = 1;
clk_enable(sw_hci->phy_gate);
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
clk_enable(sw_hci->phy_reset);
clk_reset(sw_hci->phy_reset, 0);
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
if(ohci && sw_hci->ohci_gate){
clk_enable(sw_hci->ohci_gate);
}
mdelay(10);
clk_enable(sw_hci->sie_clk);
mdelay(10);
UsbPhyInit(sw_hci->usbc_no);
}else{
DMSG_PANIC("[%s]: wrn: open clock failed, (0x%p, 0x%p, 0x%p, %d, 0x%p)\n",
sw_hci->hci_name,
sw_hci->sie_clk, sw_hci->phy_gate,
sw_hci->phy_reset, sw_hci->clk_is_open,
sw_hci->ohci_gate);
}
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
return 0;
}
static int open_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci)
{
#ifndef CONFIG_ARCH_SUN9IW1
u32 reg_value = 0;
u32 ccmu_base = (u32 __force)SUNXI_CCM_VBASE;
DMSG_INFO("[%s]: open clock\n", sunxi_hci->hci_name);
//Gating AHB clock for USB_phy1
reg_value = USBC_Readl(ccmu_base + 0x60);
reg_value |= (1 << 26); /* AHB clock gate ehci */
reg_value |= (1 << 29); /* AHB clock gate ohci */
USBC_Writel(reg_value, (ccmu_base + 0x60));
reg_value = USBC_Readl(ccmu_base + 0x2c0);
reg_value |= (1 << 26); /* ehci reset control, de-assert */
reg_value |= (1 << 29); /* ohci reset control, de-assert */
USBC_Writel(reg_value, (ccmu_base + 0x2c0));
//delay to wati SIE stable
reg_value = 10000;
while(reg_value--);
//Enable module clock for USB phy1
reg_value = USBC_Readl(ccmu_base + 0xcc);
reg_value |= (1 << 16); /* gating specal clock for ohci */
reg_value |= (1 << 9); /* gating specal clock for usb phy1(ehci0,ohci0) */
reg_value |= (1 << 8); /* gating specal clock for usb phy0(otg) */
reg_value |= (1 << 1); /* usb phy1 reset */
reg_value |= (1 << 0); /* usb phy0 reset */
USBC_Writel(reg_value, (ccmu_base + 0xcc));
//delay some time
reg_value = 10000;
while(reg_value--);
UsbPhyInit(sunxi_hci->usbc_no);
printk("open_clock 0x60(0x%x), 0xcc(0x%x),0x2c0(0x%x)\n",
(u32)USBC_Readl(ccmu_base + 0x60),
(u32)USBC_Readl(ccmu_base + 0xcc),
(u32)USBC_Readl(ccmu_base + 0x2c0));
return 0;
#else
u32 reg_value = 0;
u32 i = 0;
u32 ccmu_base = (u32)SUNXI_CCM_VBASE;
DMSG_INFO("[%s]: open clock\n", sunxi_hci->hci_name);
usb_hci_clock_cnt ++ ;
//AHB ALL clock gate
reg_value = USBC_Readl(ccmu_base + 0x184);
reg_value |= (1 << 1); /* AHB clock gate usb0 */
USBC_Writel(reg_value, (ccmu_base + 0x184));
reg_value = USBC_Readl(ccmu_base + 0x1A4);
reg_value |= (1 << 0); /* AHB clock gate usb0 */
USBC_Writel(reg_value, (ccmu_base + 0x1A4));
reg_value = USBC_Readl(SUNXI_USB_CTRL_VBASE + 0x04);
reg_value &= ~(0x1f<<1);
reg_value &= ~(0x01<<10);
reg_value &= ~(0x01<<12);
reg_value &= ~(0x1f<<17);
reg_value |= (0x01<<3);
USBC_Writel(reg_value, SUNXI_USB_CTRL_VBASE + 0x04);
for(i=0; i<0x10; i++);
reg_value = USBC_Readl(SUNXI_USB_CTRL_VBASE + 0x04);
reg_value |= (0x01<<19);
USBC_Writel(reg_value, SUNXI_USB_CTRL_VBASE + 0x04);
reg_value = USBC_Readl(SUNXI_USB_CTRL_VBASE);
reg_value &= ~(0xf<<1);
reg_value &= ~(0xf<<17);
reg_value |= (0x1<<3);
reg_value |= (0x1<<4);
USBC_Writel(reg_value, SUNXI_USB_CTRL_VBASE);
for(i=0; i<0x10; i++);
reg_value = USBC_Readl(SUNXI_USB_CTRL_VBASE);
reg_value |= (0x01<<18);
USBC_Writel(reg_value, SUNXI_USB_CTRL_VBASE);
printk("open_clock 0x184(0x%x), 0x1A4(0x%x),0x%x(0x%x),0x%x(0x%x)\n",
(u32)USBC_Readl(ccmu_base + 0x184),
(u32)USBC_Readl(ccmu_base + 0x1A4),
(u32)(SUNXI_USB_CTRL_VBASE + 0x04),(u32)USBC_Readl(SUNXI_USB_CTRL_VBASE + 0x04),
(u32)SUNXI_USB_CTRL_VBASE, (u32)USBC_Readl(SUNXI_USB_CTRL_VBASE));
return 0;
#endif
}
static int open_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci)
{
DMSG_INFO("[%s]: open clock, is_open: %d\n", sunxi_hci->hci_name, sunxi_hci->clk_is_open);
#ifdef CONFIG_ARCH_SUN9IW1
#ifdef CONFIG_USB_SUNXI_HSIC
if(regulator_enable(vbat_hsic_hdle) < 0){
DMSG_INFO("ERR: vbat_hsic: regulator_enable fail\n");
return 0;
}
#else
if(regulator_enable(vbat_usbh_hdle) < 0){
DMSG_INFO("ERR: vbat_usbh: regulator_enable fail\n");
return 0;
}
#endif
if(usb_hci_clock_cnt == 0 && (hci_ahb_gate != NULL)){
DMSG_INFO("clk_prepare_enable: hci_ahb_gate\n");
if(clk_prepare_enable(hci_ahb_gate)){
DMSG_PANIC("ERR:try to prepare_enable %s_ahb failed!\n", sunxi_hci->hci_name);
}
}
usb_hci_clock_cnt ++;
if(!sunxi_hci->clk_is_open){
sunxi_hci->clk_is_open = 1;
open_hci_clock(sunxi_hci,ohci);
}
#else
if(sunxi_hci->ahb && sunxi_hci->mod_usbphy && !sunxi_hci->clk_is_open){
sunxi_hci->clk_is_open = 1;
if(clk_prepare_enable(sunxi_hci->ahb)){
DMSG_PANIC("ERR:try to prepare_enable %s_ahb failed!\n", sunxi_hci->hci_name);
}
mdelay(10);
#ifdef CONFIG_USB_SUNXI_HSIC
{
u32 reg_value = 0;
u32 i = 0;
u32 ccmu_base = (u32)SUNXI_CCM_VBASE;
reg_value = USBC_Readl(ccmu_base + 0xcc);
reg_value |= (0x01<<10);
reg_value |= (0x01<<11);
USBC_Writel(reg_value, (ccmu_base + 0xcc));
for(i=0; i < 0x100; i++);
reg_value |= (0x01 << 2);
USBC_Writel(reg_value, (ccmu_base + 0xcc));
}
#else
if(clk_prepare_enable(sunxi_hci->mod_usbphy)){
DMSG_PANIC("ERR:try to prepare_enable %s_usbphy failed!\n", sunxi_hci->hci_name);
}
mdelay(10);
#endif
UsbPhyInit(sunxi_hci->usbc_no);
}else{
DMSG_PANIC("[%s]: wrn: open clock failed, (0x%p, 0x%p, %d, 0x%p)\n",
sunxi_hci->hci_name,
sunxi_hci->ahb, sunxi_hci->mod_usbphy, sunxi_hci->clk_is_open,
sunxi_hci->mod_usb);
}
#endif
return 0;
}
