void vidc_720p_decode_skip_frm_details(u32 *free_luma_dpb)
{
u32 disp_frm;
VIDC_IO_IN(REG_697961, &disp_frm);
if (disp_frm == VIDC_720P_NOTCODED)
VIDC_IO_IN(REG_347105, free_luma_dpb);
}
void vidc_720p_decode_skip_frm_details(u32 *p_free_luma_dpb)
{
u32 n_disp_frm_type;
VIDC_IO_IN(REG_697961, &n_disp_frm_type);
if (n_disp_frm_type == VIDC_720P_NOTCODED)
VIDC_IO_IN(REG_347105, p_free_luma_dpb);
}
void vidc_720p_get_interrupt_status(u32 *interrupt_status,
u32 *cmd_err_status, u32 *disp_pic_err_status, u32 *op_failed)
{
u32 err_status;
VIDC_IO_IN(REG_512143, interrupt_status);
VIDC_IO_IN(REG_300310, &err_status);
*cmd_err_status = err_status & 0xffff;
*disp_pic_err_status = (err_status & 0xffff0000) >> 16;
VIDC_IO_INF(REG_724381, OPERATION_FAILED, \
op_failed);
}
void vidc_720p_enc_frame_info(struct vidc_720p_enc_frame_info
*enc_frame_info)
{
VIDC_IO_IN(REG_782249, &enc_frame_info->enc_size);
VIDC_IO_IN(REG_441270, &enc_frame_info->frame);
enc_frame_info->frame &= 0x03;
VIDC_IO_IN(REG_613254,
&enc_frame_info->metadata_exists);
}
void vidc_720p_enc_frame_info(struct vidc_720p_enc_frame_info_type
*p_enc_frame_info)
{
VIDC_IO_IN(REG_782249, &p_enc_frame_info->n_enc_size);
VIDC_IO_IN(REG_441270, &p_enc_frame_info->n_frame_type);
p_enc_frame_info->n_frame_type &= 0x03;
VIDC_IO_IN(REG_613254,
&p_enc_frame_info->n_metadata_exists);
}
u32 vidc_720p_cpu_start()
{
u32 fw_status = 0x0;
VIDC_IO_IN(REG_381535, &fw_status);
if (fw_status != 0x02)
return false;
return true;
}
u32 vidc_720p_cpu_start()
{
u32 fw_status = 0x0;
VIDC_IO_IN(REG_381535, &fw_status);
if (fw_status != 0x02)
return FALSE;
return TRUE;
}
void vidc_720p_submit_command(u32 ch_id, u32 cmd_id)
{
u32 fw_status;
VIDC_IO_OUT(REG_97293, ch_id);
VIDC_IO_OUT(REG_62325, cmd_id);
VIDC_DEBUG_REGISTER_LOG;
VIDC_IO_IN(REG_381535, &fw_status);
VIDC_IO_OUT(REG_926519, fw_status);
}
u32 vidc_720p_engine_reset(u32 ch_id,
enum vidc_720p_endian dma_endian,
enum vidc_720p_interrupt_level_selection interrupt_sel,
u32 interrupt_mask
)
{
u32 op_done = 0;
u32 counter = 0;
VIDC_LOGERR_STRING("ENG-RESET!!");
/* issue the engine reset command */
vidc_720p_submit_command(ch_id, VIDC_720P_CMD_MFC_ENGINE_RESET);
do {
VIDC_BUSY_WAIT(20);
VIDC_IO_IN(REG_982553, &op_done);
counter++;
} while (!op_done && counter < 10);
if (!op_done) {
/* Reset fails */
return false ;
}
/* write invalid channel id */
VIDC_IO_OUT(REG_97293, 4);
/* Set INT_PULSE_SEL */
if (interrupt_sel == VIDC_720P_INTERRUPT_LEVEL_SEL)
VIDC_IO_OUT(REG_491082, 0);
else
VIDC_IO_OUT(REG_491082, 1);
if (!interrupt_mask) {
/* Disable interrupt */
VIDC_IO_OUT(REG_609676, 1);
} else {
/* Enable interrupt */
VIDC_IO_OUT(REG_609676, 0);
}
/* Clear any pending interrupt */
VIDC_IO_OUT(REG_614776, 1);
/* Set INT_ENABLE_REG */
VIDC_IO_OUT(REG_418173, interrupt_mask);
/*Sets the DMA endianness */
VIDC_IO_OUT(REG_736316, dma_endian);
/*Restore ARM endianness */
VIDC_IO_OUT(REG_215724, 0);
/* retun engine reset success */
return true ;
}
void vidc_720p_decode_get_seq_hdr_info(struct vidc_720p_seq_hdr_info
*seq_hdr_info)
{
u32 display_status;
VIDC_IO_IN(REG_999267, &seq_hdr_info->img_size_x);
VIDC_IO_IN(REG_345712, &seq_hdr_info->img_size_y);
VIDC_IO_IN(REG_257463, &seq_hdr_info->min_num_dpb);
VIDC_IO_IN(REG_854281, &seq_hdr_info->min_dpb_size);
VIDC_IO_IN(REG_580603, &seq_hdr_info->dec_frm_size);
VIDC_IO_INF(REG_606447, DISP_PIC_PROFILE,
&seq_hdr_info->profile);
VIDC_IO_INF(REG_606447, DIS_PIC_LEVEL,
&seq_hdr_info->level);
VIDC_IO_INF(REG_612715, DISPLAY_STATUS,
&display_status);
seq_hdr_info->progressive =
((display_status & 0x4) >> 2);
/* bit 3 is for crop existence */
seq_hdr_info->crop_exists = ((display_status & 0x8) >> 3);
if (seq_hdr_info->crop_exists) {
/* read the cropping information */
VIDC_IO_INF(REG_881638, CROP_RIGHT_OFFSET, \
&seq_hdr_info->crop_right_offset);
VIDC_IO_INF(REG_881638, CROP_LEFT_OFFSET, \
&seq_hdr_info->crop_left_offset);
VIDC_IO_INF(REG_161486, CROP_BOTTOM_OFFSET, \
&seq_hdr_info->crop_bottom_offset);
VIDC_IO_INF(REG_161486, CROP_TOP_OFFSET, \
&seq_hdr_info->crop_top_offset);
}
/* Read the MPEG4 data partitioning indication */
VIDC_IO_INF(REG_441270, DATA_PARTITIONED, \
&seq_hdr_info->data_partitioned);
}
u32 vidc_720p_reset_is_success()
{
u32 stagecounter = 0;
VIDC_IO_IN(REG_352831, &stagecounter);
stagecounter &= 0xff;
if (stagecounter != 0xe5) {
DBG("\n VIDC-CPU_RESET-FAILS!");
VIDC_IO_OUT(REG_224135, 0);
msleep(10);
return false;
}
return true;
}
u32 vidc_720p_reset_is_success()
{
u32 n_stagecounter = 0;
VIDC_IO_IN(REG_352831, &n_stagecounter);
n_stagecounter &= 0xff;
if (n_stagecounter != 0xe5) {
DBG("\n VIDC-CPU_RESET-FAILS!");
VIDC_IO_OUT(REG_224135, 0);
msleep(10);
return FALSE;
}
return TRUE;
}
u32 vidc_720p_do_sw_reset(void)
{
u32 fw_start = 0;
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_224135, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_193553, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_141269, 1);
VIDC_BUSY_WAIT(15);
VIDC_IO_OUT(REG_141269, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_IN(REG_193553, &fw_start);
if (!fw_start) {
DBG("\n VIDC-SW-RESET-FAILS!");
return false;
}
return true;
}
u32 vidc_720p_do_sw_reset(void)
{
u32 n_fw_start = 0;
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_224135, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_193553, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_141269, 1);
VIDC_BUSY_WAIT(15);
VIDC_IO_OUT(REG_141269, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_IN(REG_193553, &n_fw_start);
if (!n_fw_start) {
DBG("\n VIDC-SW-RESET-FAILS!");
return FALSE;
}
return TRUE;
}
void vidc_720p_decode_display_info(struct vidc_720p_dec_disp_info
*disp_info)
{
u32 display_status = 0;
VIDC_IO_INF(REG_612715, DISPLAY_STATUS, &display_status);
disp_info->disp_status =
(enum vidc_720p_display_status)((display_status & 0x3));
disp_info->disp_is_interlace = ((display_status & 0x4) >> 2);
disp_info->crop_exists = ((display_status & 0x8) >> 3);
disp_info->resl_change = ((display_status & 0x30) >> 4);
VIDC_IO_INF(REG_724381, RESOLUTION_CHANGE,
&disp_info->reconfig_flush_done);
VIDC_IO_IN(REG_999267, &disp_info->img_size_x);
VIDC_IO_IN(REG_345712, &disp_info->img_size_y);
VIDC_IO_IN(REG_151345, &disp_info->y_addr);
VIDC_IO_IN(REG_293983, &disp_info->c_addr);
VIDC_IO_IN(REG_370409, &disp_info->tag_top);
VIDC_IO_IN(REG_438677, &disp_info->tag_bottom);
VIDC_IO_IN(REG_679165, &disp_info->pic_time_top);
VIDC_IO_IN(REG_374150, &disp_info->pic_time_bottom);
if (disp_info->crop_exists) {
VIDC_IO_INF(REG_881638, CROP_RIGHT_OFFSET,
&disp_info->crop_right_offset);
VIDC_IO_INF(REG_881638, CROP_LEFT_OFFSET,
&disp_info->crop_left_offset);
VIDC_IO_INF(REG_161486, CROP_BOTTOM_OFFSET,
&disp_info->crop_bottom_offset);
VIDC_IO_INF(REG_161486, CROP_TOP_OFFSET,
&disp_info->crop_top_offset);
}
VIDC_IO_IN(REG_613254, &disp_info->metadata_exists);
VIDC_IO_IN(REG_580603,
&disp_info->input_bytes_consumed);
VIDC_IO_IN(REG_757835, &disp_info->input_frame_num);
VIDC_IO_INF(REG_441270, FRAME_TYPE,
&disp_info->input_frame);
disp_info->input_is_interlace =
((disp_info->input_frame & 0x4) >> 2);
disp_info->input_frame &= 0x3;
}
void vidc_720p_encode_get_header(u32 *pi_enc_header_size)
{
VIDC_IO_IN(REG_114286, pi_enc_header_size);
}
