/*!
* \brief
* set VID mode
* \retval 0 if success
*/
int wmt_vid_set_mode(int width, int height)
{
TRACE("Enter\n");
VID_REG_SET32( REG_VID_WIDTH, width ); /* VID output width */
VID_REG_SET32( REG_VID_LINE_WIDTH, ALIGN64(width) );
VID_REG_SET32( REG_VID_HEIGHT, height ); /* VID output height */
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_set_mode() */
/*!
* \brief
* set VID source address for Y and C
* \retval 0 if success
*/
int wmt_vid_set_addr(unsigned int y_addr, unsigned int c_addr)
{
TRACE("Enter\n");
cur_y_addr = REG32_VAL(REG_VID_Y0_SA);
cur_c_addr = REG32_VAL(REG_VID_C0_SA);
if( (y_addr != cur_y_addr) || (c_addr != cur_c_addr)) {
VID_REG_SET32( REG_VID_Y0_SA, y_addr ); /* VID Y FB address */
VID_REG_SET32( REG_VID_C0_SA, c_addr ); /* VID C FB address */
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_set_addr() */
/*!
* \brief
* release CMOS module
* \retval 0 if success
*/
int wmt_vid_close(vid_mode mode)
{
TRACE("Enter\n");
auto_pll_divisor(DEV_VID, CLK_DISABLE, 0, 0);
GPIO_PIN_SHARING_SEL_4BYTE_VAL &= ~BIT11;// 1, 24MHZ output 0 , SPISS 0
GPIO_CTRL_GP31_PWM_BYTE_VAL |= BIT0;
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
}
else {
int value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_close() */
/*!
* \brief
* release CMOS module
* \retval 0 if success
*/
int wmt_vid_close(vid_mode mode)
{
TRACE("Enter\n");
auto_pll_divisor(DEV_VID, CLK_DISABLE, 0, 0);
GPIO_CTRL_GP31_BYTE_VAL |= BIT4;//24Mhz off , set to GPIO
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
}
else {
int value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_close() */
int wmt_vid_open(vid_mode mode, cmos_uboot_env_t *uboot_env)
{
int value, int_ctrl;
TRACE("Enter\n");
vid_i2c_gpio_en = uboot_env->i2c_gpio_en;
printk(" vid_i2c_gpio_en 0x%08x \n",vid_i2c_gpio_en);
if ((vid_i2c_gpio_en) && (uboot_env != NULL))
{
memset(&vid_i2c0_scl, 0, sizeof(vid_i2c0_scl));
memset(&vid_i2c0_sda, 0, sizeof(vid_i2c0_sda));
vid_i2c0_scl.bit_mask = 1 << uboot_env->i2c_gpio_scl_binum;
vid_i2c0_scl.pull_en_bit_mask = 1 << uboot_env->reg_i2c_gpio_scl_gpio_pe_bitnum;
vid_i2c0_scl.data_in = uboot_env->reg_i2c_gpio_scl_gpio_in ;
vid_i2c0_scl.gpio_en = uboot_env->reg_i2c_gpio_scl_gpio_en ;
vid_i2c0_scl.out_en = uboot_env->reg_i2c_gpio_scl_gpio_od ;
vid_i2c0_scl.data_out = uboot_env->reg_i2c_gpio_scl_gpio_oc ;
vid_i2c0_scl.pull_en = uboot_env->reg_i2c_gpio_scl_gpio_pe ;
vid_i2c0_sda.bit_mask = 1 << uboot_env->i2c_gpio_sda_binum;
vid_i2c0_sda.pull_en_bit_mask = 1 << uboot_env->reg_i2c_gpio_sda_gpio_pe_bitnum;
vid_i2c0_sda.data_in = uboot_env->reg_i2c_gpio_sda_gpio_in ;
vid_i2c0_sda.gpio_en = uboot_env->reg_i2c_gpio_sda_gpio_en ;
vid_i2c0_sda.out_en = uboot_env->reg_i2c_gpio_sda_gpio_od ;
vid_i2c0_sda.data_out = uboot_env->reg_i2c_gpio_sda_gpio_oc ;
vid_i2c0_sda.pull_en = uboot_env->reg_i2c_gpio_sda_gpio_pe ;
if (vid_i2c0_scl.data_in & 0x1)
{
vid_i2c0_scl.bit_mask <<= 8;
vid_i2c0_scl.pull_en_bit_mask <<= 8;
vid_i2c0_scl.data_in -= 1;
vid_i2c0_scl.gpio_en -= 1;
vid_i2c0_scl.out_en -= 1;
vid_i2c0_scl.data_out -= 1;
vid_i2c0_scl.pull_en -= 1;
}
if (vid_i2c0_sda.data_in & 0x1)
{
vid_i2c0_sda.bit_mask <<= 8;
vid_i2c0_sda.pull_en_bit_mask <<= 8;
vid_i2c0_sda.data_in -= 1;
vid_i2c0_sda.gpio_en -= 1;
vid_i2c0_sda.out_en -= 1;
vid_i2c0_sda.data_out -= 1;
vid_i2c0_sda.pull_en -= 1;
}
vid_swi2c.scl_reg = &vid_i2c0_scl;
vid_swi2c.sda_reg = &vid_i2c0_sda;
printk("SCL 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",vid_i2c0_scl.bit_mask,vid_i2c0_scl.pull_en_bit_mask,vid_i2c0_scl.data_in,vid_i2c0_scl.gpio_en,vid_i2c0_scl.out_en,vid_i2c0_scl.data_out, vid_i2c0_scl.pull_en);
printk("SDA 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",vid_i2c0_sda.bit_mask,vid_i2c0_sda.pull_en_bit_mask,vid_i2c0_sda.data_in,vid_i2c0_sda.gpio_en,vid_i2c0_sda.out_en,vid_i2c0_sda.data_out, vid_i2c0_sda.pull_en );
}
/*--------------------------------------------------------------------------
Step 1: Init GPIO for CMOS or TVDEC mode
--------------------------------------------------------------------------*/
vid_gpio_init(mode);
/*--------------------------------------------------------------------------
Step 2: Init CMOS or TVDEC module
--------------------------------------------------------------------------*/
value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_MEMIF_EN, 0x1 );
VID_REG_SET32( REG_VID_OUTPUT_FORMAT, 0x0 ); // 0: 422 1: 444
int_ctrl = 0x00;
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
VID_REG_SET32( REG_VID_CMOS_PIXEL_SWAP, 0x2); /* 0x2 for YUYV */
#ifdef VID_INT_MODE
int_ctrl = 0x0808;
#endif
VID_REG_SET32( REG_VID_INT_CTRL, int_ctrl );
// VID_REG_SET32( REG_VID_CMOS_EN, 0x1); /* enable CMOS */
}
else {
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value | 0x1) ); /* enable TV decoder */
#ifdef VID_INT_MODE
int_ctrl = 0x0404;
#endif
VID_REG_SET32( REG_VID_INT_CTRL, int_ctrl );
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
wmt_vid_set_common_mode(VID_NTSC);
}
cur_y_addr = 0;
cur_c_addr = 0;
_cur_fb = 0;
_prev_fb = 0;
spin_lock_init(&vid_lock);
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_open() */
void wmt_vid_set_common_mode(vid_tvsys_e tvsys)
{
TRACE("wmt_vid_set_common_mode() \n");
printk("wmt_vid_set_common_mode() \n");
if (tvsys == VID_NTSC)
vid_set_ntsc_656();
else
vid_set_pal_656();
//VID_REG_SET32( REG_BASE_VID+0x60, vid_fb_y_addr[0] ); // Y0 SA
//VID_REG_SET32( REG_BASE_VID+0x64, vid_fb_c_addr[0] ); // C0 SA
VID_REG_SET32( REG_BASE_VID+0x04, 0x100 ); // TMODE[0],REG_UPDATE[8]
if (tvsys==VID_NTSC)
{
VID_REG_SET32( REG_BASE_VID+0x14, 0x10a0004 ); // VSBB[25:16]:VSBT[9:0]; 139/1=PAL 10A/4=NTSC
VID_REG_SET32( REG_BASE_VID+0x1c, 0x1370018 ); // PAL_TACTEND[25:16], PAL_TACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x20, 0x26f0151 ); // PAL_BACTEND[25:16], PAL_BACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x68, 720 ); // WIDTH[7:0];
VID_REG_SET32( REG_BASE_VID+0x6C, 768 ); // LN_WIDTH[7:0]
VID_REG_SET32( REG_BASE_VID+0x70, 480 ); // VID_HEIGHT[9:0]
}else{
VID_REG_SET32( REG_BASE_VID+0x14, 0x1390001 ); // VSBB[25:16]:VSBT[9:0]; 139/1=PAL 10A/4=NTSC
VID_REG_SET32( REG_BASE_VID+0x1c, 0x1360017 ); // PAL_TACTEND[25:16], PAL_TACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x20, 0x26f0150 ); // PAL_BACTEND[25:16], PAL_BACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x68, 720 ); // WIDTH[7:0];
VID_REG_SET32( REG_BASE_VID+0x6C, 768 ); // LN_WIDTH[7:0]
VID_REG_SET32( REG_BASE_VID+0x70, 576 ); // VID_HEIGHT[9:0]
}
VID_REG_SET32( REG_BASE_VID+0x10, 0x20001 ); // HSB[9:0];HSW[9:0];HSP[28]
VID_REG_SET32( REG_BASE_VID+0x18, 0x3f0002 ); // HVDLY @[25:16];VSW @[9:0];VSP[28]
VID_REG_SET32( REG_BASE_VID+0x24, 0x1060017 ); // NTSC_TACTEND[25:16],NTSC_TACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x28, 0x20d011e ); // NTSC_BACTEND[25:16],NTSC_BACTBEG[9:0]
VID_REG_SET32( REG_BASE_VID+0x78, 0 ); // REG_OUTPUT444_EN,( 0:422 format, 1:444 format )
VID_REG_SET32( REG_BASE_VID+0x7C, 0 ); // REG_HSCALE_MODE(0:bypass , 1: horizontal scale 1/2)
VID_REG_SET32( REG_BASE_VID+0x74, 0x1 ); // VID Memory write Enable
VID_REG_SET32( REG_BASE_VID+0xfc, 0x1 ); // BIT SWAP
//VID_REG_SET32( REG_BASE_VID+0x00, 0x1 ); // VID Enable
}
void vid_set_pal_656(void)
{
VID_REG_SET32( REG_BASE_VID+0x08, 0x0 );
VID_REG_SET32( REG_BASE_VID+0x34, 0x000006c0 ); // P_LN_LENGTH : 133m: d1728(6c0h) , 166m: d1727(6bf)
}
/*!
* \Init gpio setting
*
* \retval none
*/
static void vid_gpio_init(vid_mode mode)
{
#ifdef __KERNEL__
auto_pll_divisor(DEV_VID, CLK_ENABLE, 0, 0);
GPIO_CTRL_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_PULL_EN_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_CTRL_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PULL_EN_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= BIT12;// 0 , not invert 1 , invert
GPIO_CTRL_GP31_PWM_BYTE_VAL &= ~BIT0;
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= BIT11;// 1, 24MHZ output 0 , SPISS 0
#else
pGpio_Reg->CTRL_GP8_VDIN_byte = 0x0;
pGpio_Reg->PULL_EN_GP8_VDIN_byte = 0x0;
pGpio_Reg->CTRL_GP9_VSYNC_byte &= ~(BIT0|BIT1|BIT2);
pGpio_Reg->PULL_EN_GP9_VSYNC_byte &= ~ (BIT0|BIT1|BIT2);
pGpio_Reg->PIN_SHARING_SEL_4byte |= BIT31;//DVO disable
pGpio_Reg->PIN_SHARING_SEL_4byte &= ~BIT23;
#endif
return;
} /* End of vid_gpio_init()*/
void vid_set_ntsc_656(void)
{
VID_REG_SET32( REG_BASE_VID+0x08, 0x0 );
VID_REG_SET32( REG_BASE_VID+0x30, 0x000006b4); // N_LN_LENGTH : 133m: d1716(6b4h) , 166m: d1715(6b3)
}
/*!
* \brief
* set VID mode
* \retval 0 if success
*/
int wmt_vid_set_mode(int width, int height, unsigned int pix_format)
{
TRACE("Enter\n");
VID_REG_SET32( REG_VID_WIDTH, width ); /* VID output width */
VID_REG_SET32( REG_VID_LINE_WIDTH, (width) );
VID_REG_SET32( REG_VID_HEIGHT, height ); /* VID output height */
if (pix_format == V4L2_PIX_FMT_YUYV) // YUV422
{
DBG_INFO("V4L2_PIX_FMT_YUYV \n");
VID_REG_SET32( REG_BASE_VID+0x90, 0x0 ); //CMOS Sensor Input mode, set to YUV
VID_REG_SET32( REG_BASE_VID+0x98, 0x0 ); //CMOS RGB Output Mode, only RGB565 need set to '1'
VID_REG_SET32( REG_BASE_VID+0x78, 0x0 ); //REG_OUTPUT444_EN, set to YUV 422
} else if (pix_format == V4L2_PIX_FMT_YUV444) {
DBG_INFO("V4L2_PIX_FMT_YUYV \n");
VID_REG_SET32( REG_BASE_VID+0x90, 0x0 ); //CMOS Sensor Input mode, set to YUV
VID_REG_SET32( REG_BASE_VID+0x98, 0x0 ); //CMOS RGB Output Mode, only RGB565 need set to '1'
VID_REG_SET32( REG_BASE_VID+0x78, 0x1 ); //REG_OUTPUT444_EN, set to YUV 444
} else if (pix_format == V4L2_PIX_FMT_RGB565) {
DBG_INFO("V4L2_PIX_FMT_RGB565 \n");
VID_REG_SET32( REG_BASE_VID+0x90, 0x1 ); //CMOS Sensor Input mode, Set to RGB
VID_REG_SET32( REG_BASE_VID+0x98, 0x1 ); //CMOS RGB Output Mode, only RGB565 need set to '1'
} else if (pix_format == V4L2_PIX_FMT_RGB32) {
DBG_INFO("V4L2_PIX_FMT_RGB888 \n");
VID_REG_SET32( REG_BASE_VID+0x90, 0x1 ); //CMOS Sensor Input mode, Set to RGB
VID_REG_SET32( REG_BASE_VID+0x98, 0x0 ); //CMOS RGB Output Mode , only RGB565 need set to '1'
} else {
pix_format = V4L2_PIX_FMT_YUYV;
DBG_INFO("V4L2_PIX_unknow , set to V4L2_PIX_FMT_YUYV \n");
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_set_mode() */
