/**Function*************************************************************
Synopsis [Computes supports of the partitions.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Llb_ImgSupports( Aig_Man_t * p, Vec_Ptr_t * vDdMans, Vec_Int_t * vStart, Vec_Int_t * vStop, int fAddPis, int fVerbose )
{
Vec_Ptr_t * vSupps;
Vec_Int_t * vOne;
Aig_Obj_t * pObj;
DdManager * dd;
DdNode * bSupp, * bTemp;
int i, Entry, nSize;
nSize = Cudd_ReadSize( (DdManager *)Vec_PtrEntry( vDdMans, 0 ) );
vSupps = Vec_PtrAlloc( 100 );
// create initial
vOne = Vec_IntStart( nSize );
Vec_IntForEachEntry( vStart, Entry, i )
Vec_IntWriteEntry( vOne, Entry, 1 );
Vec_PtrPush( vSupps, vOne );
// create intermediate
Vec_PtrForEachEntry( DdManager *, vDdMans, dd, i )
{
vOne = Vec_IntStart( nSize );
bSupp = Cudd_Support( dd, dd->bFunc ); Cudd_Ref( bSupp );
for ( bTemp = bSupp; bTemp != Cudd_ReadOne(dd); bTemp = cuddT(bTemp) )
Vec_IntWriteEntry( vOne, bTemp->index, 1 );
Cudd_RecursiveDeref( dd, bSupp );
Vec_PtrPush( vSupps, vOne );
}
/**Function*************************************************************
Synopsis [Returns the probability of POs being 1 under rand seq sim.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ssw_ManProfileConstraints( Aig_Man_t * p, int nWords, int nFrames, int fVerbose )
{
Vec_Ptr_t * vInfo;
Vec_Int_t * vProbs, * vProbs2;
Aig_Obj_t * pObj, * pObjLi;
unsigned * pInfo, * pInfo0, * pInfo1, * pInfoMask, * pInfoMask2;
int i, w, f, RetValue = 1, clk = clock();
if ( fVerbose )
printf( "Simulating %d nodes and %d flops for %d frames with %d words... ",
Aig_ManNodeNum(p), Aig_ManRegNum(p), nFrames, nWords );
Aig_ManRandom( 1 );
vInfo = Vec_PtrAllocSimInfo( Aig_ManObjNumMax(p)+2, nWords );
Vec_PtrCleanSimInfo( vInfo, 0, nWords );
vProbs = Vec_IntStart( Saig_ManPoNum(p) );
vProbs2 = Vec_IntStart( Saig_ManPoNum(p) );
// start the constant
pInfo = (unsigned *)Vec_PtrEntry( vInfo, Aig_ObjId(Aig_ManConst1(p)) );
for ( w = 0; w < nWords; w++ )
pInfo[w] = ~0;
// start the flop inputs
Saig_ManForEachLi( p, pObj, i )
{
pInfo = (unsigned *)Vec_PtrEntry( vInfo, Aig_ObjId(pObj) );
for ( w = 0; w < nWords; w++ )
pInfo[w] = 0;
}
/**Function*************************************************************
Synopsis [Transforms edge assignment.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManEdgeFromArray( Gia_Man_t * p, Vec_Int_t * vArray )
{
int i, iObj1, iObj2, Count = 0;
Vec_IntFreeP( &p->vEdge1 );
Vec_IntFreeP( &p->vEdge2 );
p->vEdge1 = Vec_IntStart( Gia_ManObjNum(p) );
p->vEdge2 = Vec_IntStart( Gia_ManObjNum(p) );
Vec_IntForEachEntryDouble( vArray, iObj1, iObj2, i )
{
assert( iObj1 < iObj2 );
Count += Gia_ObjEdgeAdd( iObj1, iObj2, p->vEdge1, p->vEdge2 );
Count += Gia_ObjEdgeAdd( iObj2, iObj1, p->vEdge1, p->vEdge2 );
}
/**Function*************************************************************
Synopsis [Computes equivalence classes of objects in pNtk1 and pNtk2.]
Description [Internal procedure.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NtkDressMapIds( Aig_Man_t * pMiter, Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2 )
{
Vec_Ptr_t * vRes;
Vec_Int_t * vId2Lit1, * vId2Lit2, * vCounts0, * vCounts1, * vClassC, * vClass2Num;
int i, Class;
// start the classes
vRes = Vec_PtrAlloc( 1000 );
// set polarity of the nodes
Abc_NtkDressMapSetPolarity( pNtk1 );
Abc_NtkDressMapSetPolarity( pNtk2 );
// create mapping of node IDs of pNtk1/pNtk2 into the IDs of equiv classes of pMiter
vId2Lit1 = Abc_NtkDressMapClasses( pMiter, pNtk1 );
vId2Lit2 = Abc_NtkDressMapClasses( pMiter, pNtk2 );
// count the number of nodes in each equivalence class
vCounts0 = Vec_IntStart( Aig_ManObjNumMax(pMiter) );
Vec_IntForEachEntry( vId2Lit1, Class, i )
if ( Class >= 0 )
Vec_IntAddToEntry( vCounts0, Class, 1 );
vCounts1 = Vec_IntStart( Aig_ManObjNumMax(pMiter) );
Vec_IntForEachEntry( vId2Lit2, Class, i )
if ( Class >= 0 )
Vec_IntAddToEntry( vCounts1, Class, 1 );
// get the costant class
vClassC = Vec_IntAlloc( 100 );
Vec_IntForEachEntry( vId2Lit1, Class, i )
if ( Class == 0 )
Vec_IntPush( vClassC, Abc_ObjDressMakeId(pNtk1, i, 0) );
Vec_IntForEachEntry( vId2Lit2, Class, i )
if ( Class == 0 )
Vec_IntPush( vClassC, Abc_ObjDressMakeId(pNtk2, i, 1) );
Vec_PtrPush( vRes, vClassC );
// map repr node IDs into class numbers
vClass2Num = Vec_IntAlloc( 0 );
Vec_IntFill( vClass2Num, Aig_ManObjNumMax(pMiter), -1 );
// keep classes having at least one element from pNtk1 and one from pNtk2
Vec_IntForEachEntry( vId2Lit1, Class, i )
if ( Class > 0 && Vec_IntEntry(vCounts0, Class) && Vec_IntEntry(vCounts1, Class) )
Vec_IntPush( Abc_ObjDressClass(vRes, vClass2Num, Class), Abc_ObjDressMakeId(pNtk1, i, 0) );
Vec_IntForEachEntry( vId2Lit2, Class, i )
if ( Class > 0 && Vec_IntEntry(vCounts0, Class) && Vec_IntEntry(vCounts1, Class) )
Vec_IntPush( Abc_ObjDressClass(vRes, vClass2Num, Class), Abc_ObjDressMakeId(pNtk2, i, 1) );
// package them accordingly
Vec_IntFree( vClass2Num );
Vec_IntFree( vCounts0 );
Vec_IntFree( vCounts1 );
Vec_IntFree( vId2Lit1 );
Vec_IntFree( vId2Lit2 );
return vRes;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManMuxProfiling( Gia_Man_t * p )
{
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
Vec_Int_t * vFans;
Vec_Int_t * vCounts;
int i, nRefs, Size, Count, Total = 0, Roots = 0;
pNew = Gia_ManDupMuxes( p );
Gia_ManCreateRefs( pNew );
Gia_ManForEachCo( pNew, pObj, i )
Gia_ObjRefFanin0Inc( pNew, pObj );
vFans = Gia_ManFirstFanouts( pNew );
vCounts = Vec_IntStart( 100 );
Gia_ManForEachMux( pNew, pObj, i )
{
Total++;
nRefs = Gia_ObjRefNumId(pNew, i);
assert( nRefs > 0 );
if ( nRefs > 1 || !Gia_ObjIsMuxId(pNew, Vec_IntEntry(vFans, i)) )
{
Roots++;
Size = Gia_MuxMffcSize(pNew, i);
Vec_IntAddToEntry( vCounts, Abc_MinInt(Size, 99), 1 );
if ( Size > 3 )
{
printf( "%d ", Size );
Gia_MuxStructPrint( pNew, i );
}
}
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Allocates sequential AIG manager.]
Description [The manager contains all the data structures needed to
represent sequential AIG and compute stand-alone retiming as well as
the integrated mapping/retiming of the sequential AIG.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Seq_t * Seq_Create( Abc_Ntk_t * pNtk )
{
Abc_Seq_t * p;
// start the manager
p = ALLOC( Abc_Seq_t, 1 );
memset( p, 0, sizeof(Abc_Seq_t) );
p->pNtk = pNtk;
p->nSize = 1000;
p->nMaxIters = 15;
p->pMmInits = Extra_MmFixedStart( sizeof(Seq_Lat_t) );
p->fEpsilon = (float)0.001;
// create internal data structures
p->vNums = Vec_IntStart( 2 * p->nSize );
p->vInits = Vec_PtrStart( 2 * p->nSize );
p->vLValues = Vec_IntStart( p->nSize );
p->vLags = Vec_StrStart( p->nSize );
p->vLValuesN = Vec_IntStart( p->nSize );
p->vAFlows = Vec_IntStart( p->nSize );
p->vLagsN = Vec_StrStart( p->nSize );
p->vUses = Vec_StrStart( p->nSize );
return p;
}
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ALLOC( unsigned, p->nSimWords );
p->uPatCol = ALLOC( unsigned, p->nSimWords );
p->uPatRow = ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)v );
return p;
}
/**Function*************************************************************
Synopsis [Partitioning using levelized order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Aig_ManPartitionLevelized( Aig_Man_t * p, int nPartSize )
{
Vec_Int_t * vId2Part;
Vec_Vec_t * vNodes;
Aig_Obj_t * pObj;
int i, k, Counter = 0;
vNodes = Aig_ManLevelize( p );
vId2Part = Vec_IntStart( Aig_ManObjNumMax(p) );
Vec_VecForEachEntryReverseReverse( Aig_Obj_t *, vNodes, pObj, i, k )
Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize );
Vec_VecFree( vNodes );
return vId2Part;
}
/**Function*************************************************************
Synopsis [Partitioning using DFS order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Aig_ManPartitionDfs( Aig_Man_t * p, int nPartSize, int fPreorder )
{
Vec_Int_t * vId2Part;
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj;
int i, Counter = 0;
vId2Part = Vec_IntStart( Aig_ManObjNumMax(p) );
if ( fPreorder )
{
vNodes = Aig_ManDfsPreorder( p, 1 );
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
Vec_IntWriteEntry( vId2Part, Aig_ObjId(pObj), Counter++/nPartSize );
}
else
{
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
// driver issue:arises when creating
// - driver ref-counter array
// - Ns2Glo maps
// - final partition
// - change-phase cube
// LI variable is used when
// - driver drives more than one LI
// - driver is a PI
// - driver is a constant
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Returns the array of times each flop driver is referenced.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Llb_DriverCountRefs( Aig_Man_t * p )
{
Vec_Int_t * vCounts;
Aig_Obj_t * pObj;
int i;
vCounts = Vec_IntStart( Aig_ManObjNumMax(p) );
Saig_ManForEachLi( p, pObj, i )
Vec_IntAddToEntry( vCounts, Aig_ObjFaninId0(pObj), 1 );
return vCounts;
}
void Wlc_WriteTables( FILE * pFile, Wlc_Ntk_t * p )
{
Vec_Int_t * vNodes;
Wlc_Obj_t * pObj, * pFanin;
word * pTable;
int i;
if ( p->vTables == NULL || Vec_PtrSize(p->vTables) == 0 )
return;
// map tables into their nodes
vNodes = Vec_IntStart( Vec_PtrSize(p->vTables) );
Wlc_NtkForEachObj( p, pObj, i )
if ( pObj->Type == WLC_OBJ_TABLE )
Vec_IntWriteEntry( vNodes, Wlc_ObjTableId(pObj), i );
// write tables
Vec_PtrForEachEntry( word *, p->vTables, pTable, i )
{
pObj = Wlc_NtkObj( p, Vec_IntEntry(vNodes, i) );
assert( pObj->Type == WLC_OBJ_TABLE );
pFanin = Wlc_ObjFanin0( p, pObj );
Wlc_WriteTableOne( pFile, Wlc_ObjRange(pFanin), Wlc_ObjRange(pObj), pTable, i );
}
Vec_IntFree( vNodes );
}
/**Function*************************************************************
Synopsis [For each cut, returns PIs that can be quantified.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Llb_ManCutMap( Aig_Man_t * p, Vec_Ptr_t * vResult, Vec_Ptr_t * vSupps )
{
int fShowMatrix = 1;
Vec_Ptr_t * vMaps, * vOne;
Vec_Int_t * vMap, * vPrev, * vNext;
Aig_Obj_t * pObj;
int * piFirst, * piLast;
int i, k, CounterPlus, CounterMinus, Counter;
vMaps = Vec_PtrAlloc( 100 );
Vec_PtrForEachEntry( Vec_Ptr_t *, vResult, vOne, i )
{
vMap = Vec_IntStart( Aig_ManObjNumMax(p) );
Vec_PtrForEachEntry( Aig_Obj_t *, vOne, pObj, k )
{
if ( !Saig_ObjIsPi(p, pObj) )
Vec_IntWriteEntry( vMap, pObj->Id, 1 );
// else
//printf( "*" );
//printf( "%d ", pObj->Id );
}
Vec_PtrPush( vMaps, vMap );
//printf( "\n" );
}
vOne = Vec_IntStart( nSize );
Vec_IntForEachEntry( vStart, Entry, i )
Vec_IntWriteEntry( vOne, Entry, 1 );
Vec_PtrPush( vSupps, vOne );
// create intermediate
Vec_PtrForEachEntry( DdManager *, vDdMans, dd, i )
{
vOne = Vec_IntStart( nSize );
bSupp = Cudd_Support( dd, dd->bFunc ); Cudd_Ref( bSupp );
for ( bTemp = bSupp; bTemp != Cudd_ReadOne(dd); bTemp = cuddT(bTemp) )
Vec_IntWriteEntry( vOne, bTemp->index, 1 );
Cudd_RecursiveDeref( dd, bSupp );
Vec_PtrPush( vSupps, vOne );
}
// create final
vOne = Vec_IntStart( nSize );
Vec_IntForEachEntry( vStop, Entry, i )
Vec_IntWriteEntry( vOne, Entry, 1 );
if ( fAddPis )
Saig_ManForEachPi( p, pObj, i )
Vec_IntWriteEntry( vOne, Aig_ObjId(pObj), 1 );
Vec_PtrPush( vSupps, vOne );
// print supports
assert( nSize == Aig_ManObjNumMax(p) );
if ( !fVerbose )
return vSupps;
Aig_ManForEachObj( p, pObj, i )
{
int k, Counter = 0;
Vec_PtrForEachEntry( Vec_Int_t *, vSupps, vOne, k )
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
/*
Vec_Int_t * Gia_WriteDotAigMarks( Gia_Man_t * p, Vec_Int_t * vFadds, Vec_Int_t * vHadds )
{
int i;
Vec_Int_t * vMarks = Vec_IntStart( Gia_ManObjNum(p) );
for ( i = 0; i < Vec_IntSize(vHadds)/2; i++ )
{
Vec_IntWriteEntry( vMarks, Vec_IntEntry(vHadds, 2*i+0), Abc_Var2Lit(i+1, 0) );
Vec_IntWriteEntry( vMarks, Vec_IntEntry(vHadds, 2*i+1), Abc_Var2Lit(i+1, 0) );
}
for ( i = 0; i < Vec_IntSize(vFadds)/5; i++ )
{
Vec_IntWriteEntry( vMarks, Vec_IntEntry(vFadds, 5*i+3), Abc_Var2Lit(i+1, 1) );
Vec_IntWriteEntry( vMarks, Vec_IntEntry(vFadds, 5*i+4), Abc_Var2Lit(i+1, 1) );
}
return vMarks;
}
int Gia_WriteDotAigLevel_rec( Gia_Man_t * p, Vec_Int_t * vMarks, Vec_Int_t * vFadds, Vec_Int_t * vHadds, int Id, Vec_Int_t * vLevel )
{
int Level = Vec_IntEntry(vLevel, Id), Mark = Vec_IntEntry(vMarks, Id);
if ( Level || Mark == -1 )
return Level;
if ( Mark == 0 )
{
Gia_Obj_t * pObj = Gia_ManObj( p, Id );
int Level0 = Gia_WriteDotAigLevel_rec( p, vMarks, vFadds, vHadds, Gia_ObjFaninId0(pObj, Id), vLevel );
int Level1 = Gia_WriteDotAigLevel_rec( p, vMarks, vFadds, vHadds, Gia_ObjFaninId1(pObj, Id), vLevel );
Level = Abc_MaxInt(Level0, Level1) + 1;
Vec_IntWriteEntry( vLevel, Id, Level );
Vec_IntWriteEntry( vMarks, Id, -1 );
}
else if ( Abc_LitIsCompl(Mark) ) // FA
{
int i, * pFanins = Vec_IntEntryP( vFadds, 5*(Abc_Lit2Var(Mark)-1) );
assert( pFanins[3] == Id || pFanins[4] == Id );
for ( i = 0; i < 3; i++ )
Level = Abc_MaxInt( Level, Gia_WriteDotAigLevel_rec( p, vMarks, vFadds, vHadds, pFanins[i], vLevel ) );
Vec_IntWriteEntry( vLevel, pFanins[3], Level+1 );
Vec_IntWriteEntry( vLevel, pFanins[4], Level+1 );
}
else // HA
{
int * pFanins = Vec_IntEntryP( vHadds, 2*(Abc_Lit2Var(Mark)-1) );
Gia_Obj_t * pObj = Gia_ManObj( p, pFanins[1] );
int Level0 = Gia_WriteDotAigLevel_rec( p, vMarks, vFadds, vHadds, Gia_ObjFaninId0(pObj, Id), vLevel );
int Level1 = Gia_WriteDotAigLevel_rec( p, vMarks, vFadds, vHadds, Gia_ObjFaninId1(pObj, Id), vLevel );
assert( pFanins[0] == Id || pFanins[1] == Id );
Level = Abc_MaxInt(Level0, Level1) + 1;
Vec_IntWriteEntry( vLevel, pFanins[0], Level );
Vec_IntWriteEntry( vLevel, pFanins[1], Level );
}
return Level;
}
int Gia_WriteDotAigLevel( Gia_Man_t * p, Vec_Int_t * vFadds, Vec_Int_t * vHadds, Vec_Int_t ** pvMarks, Vec_Int_t ** pvLevel )
{
Vec_Int_t * vMarks = Gia_WriteDotAigMarks( p, vFadds, vHadds );
Vec_Int_t * vLevel = Vec_IntStart( Gia_ManObjNum(p) );
int i, Id, Level = 0;
Vec_IntWriteEntry( vMarks, 0, -1 );
Gia_ManForEachCiId( p, Id, i )
Vec_IntWriteEntry( vMarks, Id, -1 );
Gia_ManForEachCoDriverId( p, Id, i )
Level = Abc_MaxInt( Level, Gia_WriteDotAigLevel_rec(p, vMarks, vFadds, vHadds, Id, vLevel) );
Gia_ManForEachCoId( p, Id, i )
Vec_IntWriteEntry( vMarks, Id, -1 );
*pvMarks = vMarks;
*pvLevel = vLevel;
return Level;
}
*/
int Gia_WriteDotAigLevel( Gia_Man_t * p, Vec_Int_t * vFadds, Vec_Int_t * vHadds, Vec_Int_t * vRecord, Vec_Int_t ** pvLevel, Vec_Int_t ** pvMarks, Vec_Int_t ** pvRemap )
{
Vec_Int_t * vLevel = Vec_IntStart( Gia_ManObjNum(p) );
Vec_Int_t * vMarks = Vec_IntStart( Gia_ManObjNum(p) );
Vec_Int_t * vRemap = Vec_IntStartNatural( Gia_ManObjNum(p) );
int i, k, Id, Entry, LevelMax = 0;
Vec_IntWriteEntry( vMarks, 0, -1 );
Gia_ManForEachCiId( p, Id, i )
Vec_IntWriteEntry( vMarks, Id, -1 );
Gia_ManForEachCoId( p, Id, i )
Vec_IntWriteEntry( vMarks, Id, -1 );
Vec_IntForEachEntry( vRecord, Entry, i )
{
int Level = 0;
int Node = Abc_Lit2Var2(Entry);
int Attr = Abc_Lit2Att2(Entry);
if ( Attr == 2 )
{
int * pFanins = Vec_IntEntryP( vFadds, 5*Node );
for ( k = 0; k < 3; k++ )
Level = Abc_MaxInt( Level, Vec_IntEntry(vLevel, pFanins[k]) );
Vec_IntWriteEntry( vLevel, pFanins[3], Level+1 );
Vec_IntWriteEntry( vLevel, pFanins[4], Level+1 );
Vec_IntWriteEntry( vMarks, pFanins[4], Entry );
Vec_IntWriteEntry( vRemap, pFanins[3], pFanins[4] );
//printf( "Making FA output %d.\n", pFanins[4] );
}
else if ( Attr == 1 )
{
int * pFanins = Vec_IntEntryP( vHadds, 2*Node );
Gia_Obj_t * pObj = Gia_ManObj( p, pFanins[1] );
int pFaninsIn[2] = { Gia_ObjFaninId0(pObj, pFanins[1]), Gia_ObjFaninId1(pObj, pFanins[1]) };
for ( k = 0; k < 2; k++ )
Level = Abc_MaxInt( Level, Vec_IntEntry(vLevel, pFaninsIn[k]) );
Vec_IntWriteEntry( vLevel, pFanins[0], Level+1 );
Vec_IntWriteEntry( vLevel, pFanins[1], Level+1 );
Vec_IntWriteEntry( vMarks, pFanins[1], Entry );
Vec_IntWriteEntry( vRemap, pFanins[0], pFanins[1] );
//printf( "Making HA output %d.\n", pFanins[1] );
}
else // if ( Attr == 3 || Attr == 0 )
{
Gia_Obj_t * pObj = Gia_ManObj( p, Node );
int pFaninsIn[2] = { Gia_ObjFaninId0(pObj, Node), Gia_ObjFaninId1(pObj, Node) };
for ( k = 0; k < 2; k++ )
Level = Abc_MaxInt( Level, Vec_IntEntry(vLevel, pFaninsIn[k]) );
Vec_IntWriteEntry( vLevel, Node, Level+1 );
Vec_IntWriteEntry( vMarks, Node, -1 );
//printf( "Making node %d.\n", Node );
}
LevelMax = Abc_MaxInt( LevelMax, Level+1 );
}
/**Function*************************************************************
Synopsis [No partitioning.]
Description [The partitioner ]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Aig_ManPartitionMonolithic( Aig_Man_t * p )
{
Vec_Int_t * vId2Part;
vId2Part = Vec_IntStart( Aig_ManObjNumMax(p) );
return vId2Part;
}
/**Function*************************************************************
Synopsis [Performs structural hashing on the LUT functions.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void * Dsm_ManDeriveGia( void * pGia, int fUseMuxes )
{
Gia_Man_t * p = (Gia_Man_t *)pGia;
Gia_Man_t * pNew, * pTemp;
Vec_Int_t * vCover, * vLeaves;
Gia_Obj_t * pObj;
int k, i, iLut, iVar;
word * pTruth;
assert( Gia_ManHasMapping(p) );
// create new manager
pNew = Gia_ManStart( 6*Gia_ManObjNum(p)/5 + 100 );
pNew->pName = Abc_UtilStrsav( p->pName );
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
pNew->vLevels = Vec_IntStart( 6*Gia_ManObjNum(p)/5 + 100 );
if ( fUseMuxes )
pNew->pMuxes = ABC_CALLOC( unsigned, pNew->nObjsAlloc );
// map primary inputs
Gia_ManFillValue(p);
Gia_ManConst0(p)->Value = 0;
Gia_ManForEachCi( p, pObj, i )
pObj->Value = Gia_ManAppendCi(pNew);
// iterate through nodes used in the mapping
vLeaves = Vec_IntAlloc( 16 );
vCover = Vec_IntAlloc( 1 << 16 );
Gia_ManHashStart( pNew );
Gia_ObjComputeTruthTableStart( p, Gia_ManLutSizeMax(p) );
Gia_ManForEachAnd( p, pObj, iLut )
{
if ( Gia_ObjIsBuf(pObj) )
{
pObj->Value = Gia_ManAppendBuf( pNew, Gia_ObjFanin0Copy(pObj) );
continue;
}
if ( !Gia_ObjIsLut(p, iLut) )
continue;
// collect leaves
Vec_IntClear( vLeaves );
Gia_LutForEachFanin( p, iLut, iVar, k )
Vec_IntPush( vLeaves, iVar );
pTruth = Gia_ObjComputeTruthTableCut( p, Gia_ManObj(p, iLut), vLeaves );
// collect incoming literals
Vec_IntClear( vLeaves );
Gia_LutForEachFanin( p, iLut, iVar, k )
Vec_IntPush( vLeaves, Gia_ManObj(p, iVar)->Value );
Gia_ManObj(p, iLut)->Value = Dsm_ManTruthToGia( pNew, pTruth, vLeaves, vCover );
}
Gia_ObjComputeTruthTableStop( p );
Gia_ManForEachCo( p, pObj, i )
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
Gia_ManHashStop( pNew );
Gia_ManSetRegNum( pNew, Gia_ManRegNum(p) );
Vec_IntFree( vLeaves );
Vec_IntFree( vCover );
/*
Gia_ManForEachAnd( pNew, pObj, i )
{
int iLev = Gia_ObjLevelId(pNew, i);
int iLev0 = Gia_ObjLevelId(pNew, Gia_ObjFaninId0(pObj, i));
int iLev1 = Gia_ObjLevelId(pNew, Gia_ObjFaninId1(pObj, i));
assert( iLev == 1 + Abc_MaxInt(iLev0, iLev1) );
}
*/
// perform cleanup
pNew = Gia_ManCleanup( pTemp = pNew );
Gia_ManStop( pTemp );
return pNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ABC_ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatCol = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatRow = ABC_ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)(ABC_PTRUINT_T)v );
return p;
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
If_Man_t * Nwk_ManToIf( Aig_Man_t * p, If_Par_t * pPars, Vec_Ptr_t * vAigToIf )
{
extern Vec_Int_t * Saig_ManComputeSwitchProbs( Aig_Man_t * p, int nFrames, int nPref, int fProbOne );
Vec_Int_t * vSwitching = NULL, * vSwitching2 = NULL;
float * pSwitching = NULL, * pSwitching2 = NULL;
If_Man_t * pIfMan;
If_Obj_t * pIfObj;
Aig_Obj_t * pNode, * pFanin, * pPrev;
int i;
abctime clk = Abc_Clock();
// set the number of registers (switch activity will be combinational)
Aig_ManSetRegNum( p, 0 );
if ( pPars->fPower )
{
vSwitching = Saig_ManComputeSwitchProbs( p, 48, 16, 0 );
if ( pPars->fVerbose )
{
ABC_PRT( "Computing switching activity", Abc_Clock() - clk );
}
pSwitching = (float *)vSwitching->pArray;
vSwitching2 = Vec_IntStart( Aig_ManObjNumMax(p) );
pSwitching2 = (float *)vSwitching2->pArray;
}
// start the mapping manager and set its parameters
pIfMan = If_ManStart( pPars );
pIfMan->vSwitching = vSwitching2;
// load the AIG into the mapper
Aig_ManForEachObj( p, pNode, i )
{
if ( Aig_ObjIsAnd(pNode) )
{
pIfObj = If_ManCreateAnd( pIfMan,
If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ),
If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
// printf( "no%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsCi(pNode) )
{
pIfObj = If_ManCreateCi( pIfMan );
If_ObjSetLevel( pIfObj, Aig_ObjLevel(pNode) );
// printf( "pi%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
if ( pIfMan->nLevelMax < (int)pIfObj->Level )
pIfMan->nLevelMax = (int)pIfObj->Level;
}
else if ( Aig_ObjIsCo(pNode) )
{
pIfObj = If_ManCreateCo( pIfMan, If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
// printf( "po%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsConst1(pNode) )
pIfObj = If_ManConst1( pIfMan );
else // add the node to the mapper
assert( 0 );
// save the result
assert( Vec_PtrEntry(vAigToIf, i) == NULL );
Vec_PtrWriteEntry( vAigToIf, i, pIfObj );
pNode->pData = pIfObj;
if ( vSwitching2 )
pSwitching2[pIfObj->Id] = pSwitching[pNode->Id];
// set up the choice node
if ( Aig_ObjIsChoice( p, pNode ) )
{
for ( pPrev = pNode, pFanin = Aig_ObjEquiv(p, pNode); pFanin; pPrev = pFanin, pFanin = Aig_ObjEquiv(p, pFanin) )
If_ObjSetChoice( (If_Obj_t *)pPrev->pData, (If_Obj_t *)pFanin->pData );
If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pData );
}
// assert( If_ObjLevel(pIfObj) == Aig_ObjLevel(pNode) );
}
if ( vSwitching )
Vec_IntFree( vSwitching );
return pIfMan;
}
assert(Abc_ObjIsBi(pNext));
assert(Abc_ObjFaninNum(pNext) <= 1);
if(Abc_ObjFaninNum(pNext) == 0) // every Bi should have a fanin
Abc_FlowRetime_AddDummyFanin( pNext );
pNext = Abc_ObjFanout0(pObj);
assert(Abc_ObjIsBo(pNext));
assert(Abc_ObjFaninNum(pNext) == 1);
assert(!Abc_ObjFaninC0(pNext));
}
pManMR->nLatches = Abc_NtkLatchNum( pNtk );
pManMR->nNodes = Abc_NtkObjNumMax( pNtk )+1;
// build histogram
pManMR->vSinkDistHist = Vec_IntStart( pManMR->nNodes*2+10 );
// initialize timing
if (maxDelay)
Abc_FlowRetime_InitTiming( pNtk );
// create lag and Flow_Data structure
pManMR->vLags = Vec_IntStart(pManMR->nNodes);
memset(pManMR->vLags->pArray, 0, sizeof(int)*pManMR->nNodes);
pManMR->pDataArray = ALLOC( Flow_Data_t, pManMR->nNodes );
Abc_FlowRetime_ClearFlows( 1 );
// main loop!
pNtk = Abc_FlowRetime_MainLoop();
