int
ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags)
{
struct wdc_command wdc_c;
WDCDEBUG_PRINT(("%s: mode=0x%x, flags=0x%x\n", __func__,
mode, flags), DEBUG_PROBE);
bzero(&wdc_c, sizeof(struct wdc_command));
wdc_c.r_command = SET_FEATURES;
wdc_c.r_st_bmask = 0;
wdc_c.r_st_pmask = 0;
wdc_c.r_precomp = WDSF_SET_MODE;
wdc_c.r_count = mode;
wdc_c.flags = flags;
wdc_c.timeout = 1000; /* 1s */
if (wdc_exec_command(drvp, &wdc_c) != WDC_COMPLETE)
return CMD_AGAIN;
WDCDEBUG_PRINT(("%s: after wdc_exec_command() wdc_c.flags=0x%x\n",
__func__, wdc_c.flags), DEBUG_PROBE);
if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
return CMD_ERR;
}
return CMD_OK;
}
int
wdread(dev_t dev, struct uio *uio, int flags)
{
WDCDEBUG_PRINT(("wdread\n"), DEBUG_XFERS);
return (physio(wdstrategy, dev, B_READ, minphys, uio));
}
int
wdwrite(dev_t dev, struct uio *uio, int flags)
{
WDCDEBUG_PRINT(("wdwrite\n"), DEBUG_XFERS);
return (physio(wdstrategy, dev, B_WRITE, minphys, uio));
}
int
wdclose(dev_t dev, int flag, int fmt, struct proc *p)
{
struct wd_softc *wd;
int part = DISKPART(dev);
wd = wdlookup(DISKUNIT(dev));
if (wd == NULL)
return ENXIO;
WDCDEBUG_PRINT(("wdclose\n"), DEBUG_FUNCS);
disk_lock_nointr(&wd->sc_dk);
disk_closepart(&wd->sc_dk, part, fmt);
if (wd->sc_dk.dk_openmask == 0) {
wd_flushcache(wd, 0);
/* XXXX Must wait for I/O to complete! */
}
disk_unlock(&wd->sc_dk);
device_unref(&wd->sc_dev);
return (0);
}
daddr_t
wdsize(dev_t dev)
{
struct wd_softc *wd;
struct disklabel *lp;
int part, omask;
daddr_t size;
WDCDEBUG_PRINT(("wdsize\n"), DEBUG_FUNCS);
wd = wdlookup(DISKUNIT(dev));
if (wd == NULL)
return (-1);
part = DISKPART(dev);
omask = wd->sc_dk.dk_openmask & (1 << part);
if (omask == 0 && wdopen(dev, 0, S_IFBLK, NULL) != 0) {
size = -1;
goto exit;
}
lp = wd->sc_dk.dk_label;
size = DL_SECTOBLK(lp, DL_GETPSIZE(&lp->d_partitions[part]));
if (omask == 0 && wdclose(dev, 0, S_IFBLK, NULL) != 0)
size = -1;
exit:
device_unref(&wd->sc_dev);
return (size);
}
void
wdgetdefaultlabel(struct wd_softc *wd, struct disklabel *lp)
{
WDCDEBUG_PRINT(("wdgetdefaultlabel\n"), DEBUG_FUNCS);
bzero(lp, sizeof(struct disklabel));
lp->d_secsize = DEV_BSIZE;
DL_SETDSIZE(lp, wd->sc_capacity);
lp->d_ntracks = wd->sc_params.atap_heads;
lp->d_nsectors = wd->sc_params.atap_sectors;
lp->d_secpercyl = lp->d_ntracks * lp->d_nsectors;
lp->d_ncylinders = DL_GETDSIZE(lp) / lp->d_secpercyl;
if (wd->drvp->ata_vers == -1) {
lp->d_type = DTYPE_ST506;
strncpy(lp->d_typename, "ST506/MFM/RLL", sizeof lp->d_typename);
} else {
lp->d_type = DTYPE_ESDI;
strncpy(lp->d_typename, "ESDI/IDE disk", sizeof lp->d_typename);
}
/* XXX - user viscopy() like sd.c */
strncpy(lp->d_packname, wd->sc_params.atap_model, sizeof lp->d_packname);
lp->d_flags = 0;
lp->d_version = 1;
lp->d_magic = DISKMAGIC;
lp->d_magic2 = DISKMAGIC;
lp->d_checksum = dkcksum(lp);
}
void
wddone(void *v)
{
struct wd_softc *wd = v;
struct buf *bp = wd->sc_bp;
char buf[256], *errbuf = buf;
WDCDEBUG_PRINT(("wddone %s\n", wd->sc_dev.dv_xname),
DEBUG_XFERS);
bp->b_resid = wd->sc_wdc_bio.bcount;
errbuf[0] = '\0';
switch (wd->sc_wdc_bio.error) {
case ERR_NODEV:
bp->b_flags |= B_ERROR;
bp->b_error = ENXIO;
break;
case ERR_DMA:
errbuf = "DMA error";
goto retry;
case ERR_DF:
errbuf = "device fault";
goto retry;
case TIMEOUT:
errbuf = "device timeout";
goto retry;
case ERROR:
/* Don't care about media change bits */
if (wd->sc_wdc_bio.r_error != 0 &&
(wd->sc_wdc_bio.r_error & ~(WDCE_MC | WDCE_MCR)) == 0)
goto noerror;
ata_perror(wd->drvp, wd->sc_wdc_bio.r_error, errbuf,
sizeof buf);
retry:
/* Just reset and retry. Can we do more ? */
wdc_reset_channel(wd->drvp, 0);
diskerr(bp, "wd", errbuf, LOG_PRINTF,
wd->sc_wdc_bio.blkdone, wd->sc_dk.dk_label);
if (wd->retries++ < WDIORETRIES) {
printf(", retrying\n");
timeout_add(&wd->sc_restart_timeout, RECOVERYTIME);
return;
}
printf("\n");
bp->b_flags |= B_ERROR;
bp->b_error = EIO;
break;
case NOERROR:
noerror: if ((wd->sc_wdc_bio.flags & ATA_CORR) || wd->retries > 0)
printf("%s: soft error (corrected)\n",
wd->sc_dev.dv_xname);
}
disk_unbusy(&wd->sc_dk, (bp->b_bcount - bp->b_resid),
(bp->b_flags & B_READ));
biodone(bp);
wd->openings++;
wdstart(wd);
}
/*
* Returns 1 if we experienced an ATA-level abort command
* (ABRT bit set but no additional sense)
* 0 if normal command processing
*/
int
atapi_to_scsi_sense(struct scsi_xfer *xfer, u_int8_t flags)
{
struct scsi_sense_data *sense = &xfer->sense;
int ret = 0;
xfer->error = XS_SHORTSENSE;
sense->error_code = SSD_ERRCODE_VALID | SSD_ERRCODE_CURRENT;
sense->flags = (flags >> 4);
WDCDEBUG_PRINT(("Atapi error: %d ", (flags >> 4)), DEBUG_ERRORS);
if ((flags & 4) && (sense->flags == 0)) {
sense->flags = SKEY_ABORTED_COMMAND;
WDCDEBUG_PRINT(("ABRT "), DEBUG_ERRORS);
ret = 1;
}
if (flags & 0x1) {
sense->flags |= SSD_ILI;
WDCDEBUG_PRINT(("ILI "), DEBUG_ERRORS);
}
if (flags & 0x2) {
sense->flags |= SSD_EOM;
WDCDEBUG_PRINT(("EOM "), DEBUG_ERRORS);
}
/* Media change requested */
/* Let's ignore these in version 1 */
if (flags & 0x8) {
WDCDEBUG_PRINT(("MCR "), DEBUG_ERRORS);
if (sense->flags == 0)
xfer->error = XS_NOERROR;
}
WDCDEBUG_PRINT(("\n"), DEBUG_ERRORS);
return (ret);
}
/*
* Read/write routine for a buffer. Validates the arguments and schedules the
* transfer. Does not wait for the transfer to complete.
*/
void
wdstrategy(struct buf *bp)
{
struct wd_softc *wd;
int s;
wd = wdlookup(DISKUNIT(bp->b_dev));
if (wd == NULL) {
bp->b_error = ENXIO;
goto bad;
}
WDCDEBUG_PRINT(("wdstrategy (%s)\n", wd->sc_dev.dv_xname),
DEBUG_XFERS);
/* If device invalidated (e.g. media change, door open), error. */
if ((wd->sc_flags & WDF_LOADED) == 0) {
bp->b_error = EIO;
goto bad;
}
/* Validate the request. */
if (bounds_check_with_label(bp, wd->sc_dk.dk_label) == -1)
goto done;
/* Check that the number of sectors can fit in a byte. */
if ((bp->b_bcount / wd->sc_dk.dk_label->d_secsize) >= (1 << NBBY)) {
bp->b_error = EINVAL;
goto bad;
}
/* Queue transfer on drive, activate drive and controller if idle. */
bufq_queue(&wd->sc_bufq, bp);
s = splbio();
wdstart(wd);
splx(s);
device_unref(&wd->sc_dev);
return;
bad:
bp->b_flags |= B_ERROR;
bp->b_resid = bp->b_bcount;
done:
s = splbio();
biodone(bp);
splx(s);
if (wd != NULL)
device_unref(&wd->sc_dev);
}
static void
via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
int channel;
bus_size_t cmdsize, ctlsize;
if (pciide_chipen(sc, pa) == 0)
return;
if (interface == 0) {
WDCDEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
DEBUG_PROBE);
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
}
aprint_normal("%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
aprint_normal("\n");
if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA |
WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
}
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.UDMA_cap = 6;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
sc->sc_wdcdev.set_modes = sata_setup_channel;
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
}
}
/*
* Fabricate a default disk label, and try to read the correct one.
*/
int
wdgetdisklabel(dev_t dev, struct wd_softc *wd, struct disklabel *lp,
int spoofonly)
{
int error;
WDCDEBUG_PRINT(("wdgetdisklabel\n"), DEBUG_FUNCS);
wdgetdefaultlabel(wd, lp);
if (wd->drvp->state > RECAL)
wd->drvp->drive_flags |= DRIVE_RESET;
error = readdisklabel(DISKLABELDEV(dev), wdstrategy, lp,
spoofonly);
if (wd->drvp->state > RECAL)
wd->drvp->drive_flags |= DRIVE_RESET;
return (error);
}
void
wdrestart(void *v)
{
struct wd_softc *wd = v;
struct buf *bp = wd->sc_bp;
struct channel_softc *chnl;
int s;
WDCDEBUG_PRINT(("wdrestart %s\n", wd->sc_dev.dv_xname),
DEBUG_XFERS);
chnl = (struct channel_softc *)(wd->drvp->chnl_softc);
if (chnl->dying)
return;
s = splbio();
disk_unbusy(&wd->sc_dk, 0, (bp->b_flags & B_READ));
__wdstart(v, bp);
splx(s);
}
void
wdc_atapi_done(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
WDCDEBUG_PRINT(("wdc_atapi_done %s:%d:%d: flags 0x%x error 0x%x\n",
chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
(u_int)xfer->c_flags, sc_xfer->error), DEBUG_XFERS);
WDC_LOG_ATAPI_DONE(chp, xfer->drive, xfer->c_flags, sc_xfer->error);
if (xfer->c_flags & C_POLL)
wdc_enable_intr(chp);
scsi_done(sc_xfer);
xfer->next = NULL;
return;
}
void
wdc_atapi_real_start(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
#ifdef WDCDEBUG
struct scsi_xfer *sc_xfer = xfer->cmd;
#endif
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
/*
* Only set the DMA flag if the transfer is reasonably large.
* At least one older drive failed to complete a 4 byte DMA transfer.
*/
/* Turn off DMA flag on REQUEST SENSE */
if (!(xfer->c_flags & (C_POLL | C_SENSE | C_MEDIA_ACCESS)) &&
(drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) &&
(xfer->c_bcount > 100))
xfer->c_flags |= C_DMA;
else
xfer->c_flags &= ~C_DMA;
wdc_set_drive(chp, xfer->drive);
DELAY(1);
xfer->next = wdc_atapi_real_start_2;
ret->timeout = ATAPI_DELAY;
WDCDEBUG_PRINT(("wdc_atapi_start %s:%d:%d, scsi flags 0x%x, "
"ATA flags 0x%x\n",
chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive,
sc_xfer->flags, xfer->c_flags), DEBUG_XFERS);
return;
}
/*
* Queue a drive for I/O.
*/
void
wdstart(void *arg)
{
struct wd_softc *wd = arg;
struct buf *bp = NULL;
WDCDEBUG_PRINT(("wdstart %s\n", wd->sc_dev.dv_xname),
DEBUG_XFERS);
while (wd->openings > 0) {
/* Is there a buf for us ? */
if ((bp = bufq_dequeue(&wd->sc_bufq)) == NULL)
return;
/*
* Make the command. First lock the device
*/
wd->openings--;
wd->retries = 0;
__wdstart(wd, bp);
}
}
void
wdc_atapi_send_packet(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
/*
* Even with WDCS_ERR, the device should accept a command packet.
* Limit length to what can be stuffed into the cylinder register
* (16 bits). Some CD-ROMs seem to interpret '0' as 65536,
* but not all devices do that and it's not obvious from the
* ATAPI spec that this behaviour should be expected. If more
* data is necessary, multiple data transfer phases will be done.
*/
wdccommand(chp, xfer->drive, ATAPI_PKT_CMD,
xfer->c_bcount <= 0xfffe ? xfer->c_bcount : 0xfffe,
0, 0, 0,
(xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0);
if (xfer->c_flags & C_DMA)
drvp->n_xfers++;
DELAY(1);
xfer->next = wdc_atapi_intr_command;
ret->timeout = sc_xfer->timeout;
if ((drvp->atapi_cap & ATAPI_CFG_DRQ_MASK) == ATAPI_CFG_IRQ_DRQ) {
/* We expect an IRQ to tell us of the next state */
ret->expect_irq = 1;
}
WDCDEBUG_PRINT(("wdc_atapi_send_packet %s:%d:%d command sent\n",
chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive
), DEBUG_XFERS);
return;
}
void
wdc_atapi_reset(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
if (drvp->state == 0) {
xfer->next = wdc_atapi_done;
return;
}
WDCDEBUG_PRINT(("wdc_atapi_reset\n"), DEBUG_XFERS);
wdccommandshort(chp, xfer->drive, ATAPI_SOFT_RESET);
drvp->state = ATAPI_IDENTIFY_STATE;
drvp->n_resets++;
/* Some ATAPI devices need extra time to find their
brains after a reset
*/
xfer->next = wdc_atapi_reset_2;
ret->delay = ATAPI_RESET_DELAY;
ret->timeout = ATAPI_RESET_WAIT;
return;
}
int
wdopen(dev_t dev, int flag, int fmt, struct proc *p)
{
struct wd_softc *wd;
struct channel_softc *chnl;
int unit, part;
int error;
WDCDEBUG_PRINT(("wdopen\n"), DEBUG_FUNCS);
unit = DISKUNIT(dev);
wd = wdlookup(unit);
if (wd == NULL)
return ENXIO;
chnl = (struct channel_softc *)(wd->drvp->chnl_softc);
if (chnl->dying)
return (ENXIO);
/*
* If this is the first open of this device, add a reference
* to the adapter.
*/
if ((error = disk_lock(&wd->sc_dk)) != 0)
goto bad4;
if (wd->sc_dk.dk_openmask != 0) {
/*
* If any partition is open, but the disk has been invalidated,
* disallow further opens.
*/
if ((wd->sc_flags & WDF_LOADED) == 0) {
error = EIO;
goto bad3;
}
} else {
if ((wd->sc_flags & WDF_LOADED) == 0) {
wd->sc_flags |= WDF_LOADED;
/* Load the physical device parameters. */
wd_get_params(wd, AT_WAIT, &wd->sc_params);
/* Load the partition info if not already loaded. */
if (wdgetdisklabel(dev, wd,
wd->sc_dk.dk_label, 0) == EIO) {
error = EIO;
goto bad;
}
}
}
part = DISKPART(dev);
if ((error = disk_openpart(&wd->sc_dk, part, fmt, 1)) != 0)
goto bad;
disk_unlock(&wd->sc_dk);
device_unref(&wd->sc_dev);
return 0;
bad:
if (wd->sc_dk.dk_openmask == 0) {
}
bad3:
disk_unlock(&wd->sc_dk);
bad4:
device_unref(&wd->sc_dev);
return error;
}
void
atapiscsi_attach(struct device *parent, struct device *self, void *aux)
{
struct atapiscsi_softc *as = (struct atapiscsi_softc *)self;
struct ata_atapi_attach *aa_link = aux;
struct scsibus_attach_args saa;
struct ata_drive_datas *drvp = aa_link->aa_drv_data;
struct channel_softc *chp = drvp->chnl_softc;
struct ataparams *id = &drvp->id;
struct device *child;
extern struct scsi_iopool wdc_xfer_iopool;
printf("\n");
/* Initialize shared data. */
scsi_init();
#ifdef WDCDEBUG
if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE)
wdcdebug_atapi_mask |= DEBUG_PROBE;
#endif
as->chp = chp;
as->drive = drvp->drive;
as->sc_adapterlink.adapter_softc = as;
as->sc_adapterlink.adapter_target = 7;
as->sc_adapterlink.adapter_buswidth = 2;
as->sc_adapterlink.adapter = &atapiscsi_switch;
as->sc_adapterlink.luns = 1;
as->sc_adapterlink.openings = 1;
as->sc_adapterlink.flags = SDEV_ATAPI;
as->sc_adapterlink.pool = &wdc_xfer_iopool;
strlcpy(drvp->drive_name, as->sc_dev.dv_xname,
sizeof(drvp->drive_name));
drvp->cf_flags = as->sc_dev.dv_cfdata->cf_flags;
wdc_probe_caps(drvp, id);
WDCDEBUG_PRINT(
("general config %04x capabilities %04x ",
id->atap_config, id->atap_capabilities1),
DEBUG_PROBE);
#if (NERRS_MAX > 2)
drvp->n_dmaerrs = NERRS_MAX - 2;
#else
drvp->n_dmaerrs = 0;
#endif
drvp->drive_flags |= DRIVE_DEVICE_RESET;
/* Tape drives do funny DSC stuff */
if (ATAPI_CFG_TYPE(id->atap_config) ==
ATAPI_CFG_TYPE_SEQUENTIAL)
drvp->atapi_cap |= ACAP_DSC;
if ((id->atap_config & ATAPI_CFG_CMD_MASK) ==
ATAPI_CFG_CMD_16)
drvp->atapi_cap |= ACAP_LEN;
drvp->atapi_cap |=
(id->atap_config & ATAPI_CFG_DRQ_MASK);
WDCDEBUG_PRINT(("driver caps %04x\n", drvp->atapi_cap),
DEBUG_PROBE);
bzero(&saa, sizeof(saa));
saa.saa_sc_link = &as->sc_adapterlink;
child = config_found((struct device *)as, &saa, scsiprint);
if (child != NULL) {
struct scsibus_softc *scsi = (struct scsibus_softc *)child;
struct scsi_link *link = scsi_get_link(scsi, 0, 0);
if (link) {
strlcpy(drvp->drive_name,
((struct device *)(link->device_softc))->dv_xname,
sizeof(drvp->drive_name));
wdc_print_caps(drvp);
}
}
#ifdef WDCDEBUG
if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE)
wdcdebug_atapi_mask &= ~DEBUG_PROBE;
#endif
}
void
wdc_atapi_send_cmd(struct scsi_xfer *sc_xfer)
{
struct atapiscsi_softc *as = sc_xfer->sc_link->adapter_softc;
struct channel_softc *chp = as->chp;
struct ata_drive_datas *drvp = &chp->ch_drive[as->drive];
struct wdc_xfer *xfer;
int s;
int idx;
WDCDEBUG_PRINT(("wdc_atapi_send_cmd %s:%d:%d start\n",
chp->wdc->sc_dev.dv_xname, chp->channel, as->drive), DEBUG_XFERS);
if (sc_xfer->sc_link->target != 0) {
sc_xfer->error = XS_DRIVER_STUFFUP;
scsi_done(sc_xfer);
return;
}
xfer = sc_xfer->io;
wdc_scrub_xfer(xfer);
if (sc_xfer->flags & SCSI_POLL)
xfer->c_flags |= C_POLL;
xfer->drive = as->drive;
xfer->c_flags |= C_ATAPI;
xfer->cmd = sc_xfer;
xfer->databuf = sc_xfer->data;
xfer->c_bcount = sc_xfer->datalen;
xfer->c_start = wdc_atapi_start;
xfer->c_intr = wdc_atapi_intr;
timeout_set(&xfer->atapi_poll_to, wdc_atapi_timer_handler, chp);
WDCDEBUG_PRINT(("wdc_atapi_send_cmd %s:%d:%d ",
chp->wdc->sc_dev.dv_xname, chp->channel, as->drive),
DEBUG_XFERS | DEBUG_ERRORS);
for (idx = 0; idx < sc_xfer->cmdlen; idx++) {
WDCDEBUG_PRINT((" %02x",
((unsigned char *)sc_xfer->cmd)[idx]),
DEBUG_XFERS | DEBUG_ERRORS);
}
WDCDEBUG_PRINT(("\n"), DEBUG_XFERS | DEBUG_ERRORS);
s = splbio();
if (drvp->atapi_cap & ACAP_DSC) {
WDCDEBUG_PRINT(("about to send cmd 0x%x ",
sc_xfer->cmd->opcode), DEBUG_DSC);
switch (sc_xfer->cmd->opcode) {
case READ:
case WRITE:
xfer->c_flags |= C_MEDIA_ACCESS;
/* If we are not in buffer availability mode,
we limit the first request to 0 bytes, which
gets us into buffer availability mode without
holding the bus. */
if (!(drvp->drive_flags & DRIVE_DSCBA)) {
xfer->c_bcount = 0;
xfer->transfer_len =
_3btol(((struct scsi_rw_tape *)
sc_xfer->cmd)->len);
_lto3b(0,
((struct scsi_rw_tape *)
sc_xfer->cmd)->len);
xfer->c_done = wdc_atapi_tape_done;
WDCDEBUG_PRINT(
("R/W in completion mode, do 0 blocks\n"),
DEBUG_DSC);
} else
WDCDEBUG_PRINT(("R/W %d blocks %d bytes\n",
_3btol(((struct scsi_rw_tape *)
sc_xfer->cmd)->len),
sc_xfer->datalen),
DEBUG_DSC);
/* DSC will change to buffer availability mode.
We reflect this in wdc_atapi_intr. */
break;
case ERASE: /* Media access commands */
case LOAD:
case REWIND:
case SPACE:
case WRITE_FILEMARKS:
#if 0
case LOCATE:
case READ_POSITION:
#endif
xfer->c_flags |= C_MEDIA_ACCESS;
break;
default:
WDCDEBUG_PRINT(("no media access\n"), DEBUG_DSC);
}
}
wdc_exec_xfer(chp, xfer);
splx(s);
}
void
wdc_atapi_intr_command(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
struct atapiscsi_softc *as = sc_xfer->sc_link->adapter_softc;
int i;
u_int8_t cmd[16];
struct scsi_sense *cmd_reqsense;
int cmdlen = (drvp->atapi_cap & ACAP_LEN) ? 16 : 12;
int dma_flags = ((sc_xfer->flags & SCSI_DATA_IN) ||
(xfer->c_flags & C_SENSE)) ? WDC_DMA_READ : 0;
wdc_atapi_update_status(chp);
if ((chp->ch_status & WDCS_BSY) || !(chp->ch_status & WDCS_DRQ)) {
if (timeout)
goto timeout;
return;
}
if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
chp->wdc->irqack(chp);
bzero(cmd, sizeof(cmd));
if (xfer->c_flags & C_SENSE) {
cmd_reqsense = (struct scsi_sense *)&cmd[0];
cmd_reqsense->opcode = REQUEST_SENSE;
cmd_reqsense->length = xfer->c_bcount;
} else
bcopy(sc_xfer->cmd, cmd, sc_xfer->cmdlen);
WDC_LOG_ATAPI_CMD(chp, xfer->drive, xfer->c_flags,
cmdlen, cmd);
for (i = 0; i < 12; i++)
WDCDEBUG_PRINT(("%02x ", cmd[i]), DEBUG_INTR);
WDCDEBUG_PRINT((": PHASE_CMDOUT\n"), DEBUG_INTR);
/* Init the DMA channel if necessary */
if (xfer->c_flags & C_DMA) {
if ((*chp->wdc->dma_init)(chp->wdc->dma_arg,
chp->channel, xfer->drive, xfer->databuf,
xfer->c_bcount, dma_flags) != 0) {
sc_xfer->error = XS_DRIVER_STUFFUP;
xfer->next = wdc_atapi_reset;
return;
}
}
wdc_output_bytes(drvp, cmd, cmdlen);
/* Start the DMA channel if necessary */
if (xfer->c_flags & C_DMA) {
(*chp->wdc->dma_start)(chp->wdc->dma_arg,
chp->channel, xfer->drive);
xfer->next = wdc_atapi_intr_complete;
} else {
if (xfer->c_bcount == 0)
as->protocol_phase = as_completed;
else
as->protocol_phase = as_data;
xfer->next = wdc_atapi_pio_intr;
}
ret->expect_irq = 1;
/* If we read/write to a tape we will get into buffer
availability mode. */
if (drvp->atapi_cap & ACAP_DSC) {
if ((sc_xfer->cmd->opcode == READ ||
sc_xfer->cmd->opcode == WRITE)) {
drvp->drive_flags |= DRIVE_DSCBA;
WDCDEBUG_PRINT(("set DSCBA\n"), DEBUG_DSC);
} else if ((xfer->c_flags & C_MEDIA_ACCESS) &&
(drvp->drive_flags & DRIVE_DSCBA)) {
/* Clause 3.2.4 of QIC-157 D.
Any media access command other than read or
write will switch DSC back to completion
mode */
drvp->drive_flags &= ~DRIVE_DSCBA;
WDCDEBUG_PRINT(("clear DCSBA\n"), DEBUG_DSC);
}
}
return;
timeout:
printf ("%s:%d:%d: device timeout waiting to send SCSI packet\n",
chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive);
sc_xfer->error = XS_TIMEOUT;
xfer->next = wdc_atapi_reset;
return;
}
static void
via_setup_channel(struct wdc_channel *chp)
{
u_int32_t udmatim_reg, datatim_reg;
u_int8_t idedma_ctl;
int mode, drive;
struct ata_drive_datas *drvp;
struct pciide_channel *cp = (struct pciide_channel*)chp;
struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
struct wdc_softc *wdc = &sc->sc_wdcdev;
#ifndef PCIIDE_AMD756_ENABLEDMA
int rev = PCI_REVISION(
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
#endif
idedma_ctl = 0;
datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
/* setup DMA if needed */
pciide_channel_dma_setup(cp);
for (drive = 0; drive < 2; drive++) {
drvp = &chp->ch_drive[drive];
/* If no drive, skip */
if ((drvp->drive_flags & DRIVE) == 0)
continue;
/* add timing values, setup DMA if needed */
if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
(drvp->drive_flags & DRIVE_UDMA) == 0)) {
mode = drvp->PIO_mode;
goto pio;
}
if ((wdc->cap & WDC_CAPABILITY_UDMA) &&
(drvp->drive_flags & DRIVE_UDMA)) {
/* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
APO_UDMA_EN_MTH(chp->ch_channel, drive);
switch (PCI_VENDOR(sc->sc_pci_id)) {
case PCI_VENDOR_VIATECH:
if (sc->sc_wdcdev.UDMA_cap == 6) {
/* 8233a */
udmatim_reg |= APO_UDMA_TIME(
chp->ch_channel,
drive,
via_udma133_tim[drvp->UDMA_mode]);
} else if (sc->sc_wdcdev.UDMA_cap == 5) {
/* 686b */
udmatim_reg |= APO_UDMA_TIME(
chp->ch_channel,
drive,
via_udma100_tim[drvp->UDMA_mode]);
} else if (sc->sc_wdcdev.UDMA_cap == 4) {
/* 596b or 686a */
udmatim_reg |= APO_UDMA_CLK66(
chp->ch_channel);
udmatim_reg |= APO_UDMA_TIME(
chp->ch_channel,
drive,
via_udma66_tim[drvp->UDMA_mode]);
} else {
/* 596a or 586b */
udmatim_reg |= APO_UDMA_TIME(
chp->ch_channel,
drive,
via_udma33_tim[drvp->UDMA_mode]);
}
break;
case PCI_VENDOR_AMD:
case PCI_VENDOR_NVIDIA:
udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
drive, amd7x6_udma_tim[drvp->UDMA_mode]);
break;
}
/* can use PIO timings, MW DMA unused */
mode = drvp->PIO_mode;
} else {
/* use Multiword DMA, but only if revision is OK */
drvp->drive_flags &= ~DRIVE_UDMA;
#ifndef PCIIDE_AMD756_ENABLEDMA
/*
* The workaround doesn't seem to be necessary
* with all drives, so it can be disabled by
* PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
* triggered.
*/
if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
sc->sc_pp->ide_product ==
PCI_PRODUCT_AMD_PBC756_IDE &&
AMD756_CHIPREV_DISABLEDMA(rev)) {
aprint_normal(
"%s:%d:%d: multi-word DMA disabled due "
"to chip revision\n",
sc->sc_wdcdev.sc_dev.dv_xname,
chp->ch_channel, drive);
mode = drvp->PIO_mode;
drvp->drive_flags &= ~DRIVE_DMA;
goto pio;
}
#endif
/* mode = min(pio, dma+2) */
if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
mode = drvp->PIO_mode;
else
mode = drvp->DMA_mode + 2;
}
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio: /* setup PIO mode */
if (mode <= 2) {
drvp->DMA_mode = 0;
drvp->PIO_mode = 0;
mode = 0;
} else {
drvp->PIO_mode = mode;
drvp->DMA_mode = mode - 2;
}
datatim_reg |=
APO_DATATIM_PULSE(chp->ch_channel, drive,
apollo_pio_set[mode]) |
APO_DATATIM_RECOV(chp->ch_channel, drive,
apollo_pio_rec[mode]);
}
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
idedma_ctl);
}
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
WDCDEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
}
static void
via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
pcireg_t vendor = PCI_VENDOR(pa->pa_id);
int channel;
u_int32_t ideconf;
bus_size_t cmdsize, ctlsize;
pcireg_t pcib_id, pcib_class;
struct pci_attach_args pcib_pa;
if (pciide_chipen(sc, pa) == 0)
return;
switch (vendor) {
case PCI_VENDOR_VIATECH:
/*
* get a PCI tag for the ISA bridge.
*/
if (pci_enumerate_bus(
(struct pci_softc *)sc->sc_wdcdev.sc_dev.dv_parent,
via_pcib_match, &pcib_pa) == 0)
goto unknown;
pcib_id = pcib_pa.pa_id;
pcib_class = pcib_pa.pa_class;
aprint_normal("%s: VIA Technologies ",
sc->sc_wdcdev.sc_dev.dv_xname);
switch (PCI_PRODUCT(pcib_id)) {
case PCI_PRODUCT_VIATECH_VT82C586_ISA:
aprint_normal("VT82C586 (Apollo VP) ");
if(PCI_REVISION(pcib_class) >= 0x02) {
aprint_normal("ATA33 controller\n");
sc->sc_wdcdev.UDMA_cap = 2;
} else {
aprint_normal("controller\n");
sc->sc_wdcdev.UDMA_cap = 0;
}
break;
case PCI_PRODUCT_VIATECH_VT82C596A:
aprint_normal("VT82C596A (Apollo Pro) ");
if (PCI_REVISION(pcib_class) >= 0x12) {
aprint_normal("ATA66 controller\n");
sc->sc_wdcdev.UDMA_cap = 4;
} else {
aprint_normal("ATA33 controller\n");
sc->sc_wdcdev.UDMA_cap = 2;
}
break;
case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
aprint_normal("VT82C686A (Apollo KX133) ");
if (PCI_REVISION(pcib_class) >= 0x40) {
aprint_normal("ATA100 controller\n");
sc->sc_wdcdev.UDMA_cap = 5;
} else {
aprint_normal("ATA66 controller\n");
sc->sc_wdcdev.UDMA_cap = 4;
}
break;
case PCI_PRODUCT_VIATECH_VT8231:
aprint_normal("VT8231 ATA100 controller\n");
sc->sc_wdcdev.UDMA_cap = 5;
break;
case PCI_PRODUCT_VIATECH_VT8233:
aprint_normal("VT8233 ATA100 controller\n");
sc->sc_wdcdev.UDMA_cap = 5;
break;
case PCI_PRODUCT_VIATECH_VT8233A:
aprint_normal("VT8233A ATA133 controller\n");
sc->sc_wdcdev.UDMA_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8235:
aprint_normal("VT8235 ATA133 controller\n");
sc->sc_wdcdev.UDMA_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8237:
aprint_normal("VT8237 ATA133 controller\n");
sc->sc_wdcdev.UDMA_cap = 6;
break;
default:
unknown:
aprint_normal("unknown VIA ATA controller\n");
sc->sc_wdcdev.UDMA_cap = 0;
}
sc->sc_apo_regbase = APO_VIA_REGBASE;
break;
case PCI_VENDOR_AMD:
switch (sc->sc_pp->ide_product) {
case PCI_PRODUCT_AMD_PBC8111_IDE:
sc->sc_wdcdev.UDMA_cap = 6;
break;
case PCI_PRODUCT_AMD_PBC766_IDE:
case PCI_PRODUCT_AMD_PBC768_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
break;
default:
sc->sc_wdcdev.UDMA_cap = 4;
}
sc->sc_apo_regbase = APO_AMD_REGBASE;
break;
case PCI_VENDOR_NVIDIA:
switch (sc->sc_pp->ide_product) {
case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
sc->sc_wdcdev.UDMA_cap = 5;
break;
case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
sc->sc_wdcdev.UDMA_cap = 6;
break;
}
sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
break;
default:
panic("via_chip_map: unknown vendor");
}
aprint_normal("%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
aprint_normal("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
if (sc->sc_wdcdev.UDMA_cap > 0)
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
}
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = via_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
WDCDEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
"APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
DEBUG_PROBE);
ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
aprint_normal("%s: %s channel ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
cp->wdc_channel.ch_flags |= WDCF_DISABLED;
continue;
}
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
}
}
void
wdc_atapi_intr_data(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
int len, ire;
char *message;
int tohost;
len = (CHP_READ_REG(chp, wdr_cyl_hi) << 8) |
CHP_READ_REG(chp, wdr_cyl_lo);
WDC_LOG_REG(chp, wdr_cyl_lo, len);
ire = CHP_READ_REG(chp, wdr_ireason);
WDC_LOG_REG(chp, wdr_ireason, ire);
if ((message = wdc_atapi_in_data_phase(xfer, len, ire))) {
/* The drive has dropped BSY before setting up the
registers correctly for DATA phase. This drive is
not compliant with ATA/ATAPI-4.
Give the drive 100ms to get its house in order
before we try again. */
WDCDEBUG_PRINT(("wdc_atapi_intr: %s\n", message),
DEBUG_ERRORS);
if (!timeout) {
ret->delay = 100;
return;
}
}
tohost = ((sc_xfer->flags & SCSI_DATA_IN) != 0 ||
(xfer->c_flags & C_SENSE) != 0);
if (xfer->c_bcount >= len) {
WDCDEBUG_PRINT(("wdc_atapi_intr: c_bcount %d len %d "
"st 0x%b err 0x%x "
"ire 0x%x\n", xfer->c_bcount,
len, chp->ch_status, WDCS_BITS, chp->ch_error, ire),
DEBUG_INTR);
/* Common case */
if (!tohost)
wdc_output_bytes(drvp, (u_int8_t *)xfer->databuf +
xfer->c_skip, len);
else
wdc_input_bytes(drvp, (u_int8_t *)xfer->databuf +
xfer->c_skip, len);
xfer->c_skip += len;
xfer->c_bcount -= len;
} else {
/* Exceptional case - drive want to transfer more
data than we have buffer for */
if (!tohost) {
/* Wouldn't it be better to just abort here rather
than to write random stuff to drive? */
printf("wdc_atapi_intr: warning: device requesting "
"%d bytes, only %d left in buffer\n", len, xfer->c_bcount);
wdc_output_bytes(drvp, (u_int8_t *)xfer->databuf +
xfer->c_skip, xfer->c_bcount);
CHP_WRITE_RAW_MULTI_2(chp, NULL,
len - xfer->c_bcount);
} else {
printf("wdc_atapi_intr: warning: reading only "
"%d of %d bytes\n", xfer->c_bcount, len);
wdc_input_bytes(drvp,
(char *)xfer->databuf + xfer->c_skip,
xfer->c_bcount);
wdcbit_bucket(chp, len - xfer->c_bcount);
}
xfer->c_skip += xfer->c_bcount;
xfer->c_bcount = 0;
}
ret->expect_irq = 1;
xfer->next = wdc_atapi_pio_intr;
return;
}
int
wdioctl(dev_t dev, u_long xfer, caddr_t addr, int flag, struct proc *p)
{
struct wd_softc *wd;
struct disklabel *lp;
int error = 0;
WDCDEBUG_PRINT(("wdioctl\n"), DEBUG_FUNCS);
wd = wdlookup(DISKUNIT(dev));
if (wd == NULL)
return ENXIO;
if ((wd->sc_flags & WDF_LOADED) == 0) {
error = EIO;
goto exit;
}
switch (xfer) {
case DIOCRLDINFO:
lp = malloc(sizeof(*lp), M_TEMP, M_WAITOK);
wdgetdisklabel(dev, wd, lp, 0);
bcopy(lp, wd->sc_dk.dk_label, sizeof(*lp));
free(lp, M_TEMP, 0);
goto exit;
case DIOCGPDINFO:
wdgetdisklabel(dev, wd, (struct disklabel *)addr, 1);
goto exit;
case DIOCGDINFO:
*(struct disklabel *)addr = *(wd->sc_dk.dk_label);
goto exit;
case DIOCGPART:
((struct partinfo *)addr)->disklab = wd->sc_dk.dk_label;
((struct partinfo *)addr)->part =
&wd->sc_dk.dk_label->d_partitions[DISKPART(dev)];
goto exit;
case DIOCWDINFO:
case DIOCSDINFO:
if ((flag & FWRITE) == 0) {
error = EBADF;
goto exit;
}
if ((error = disk_lock(&wd->sc_dk)) != 0)
goto exit;
error = setdisklabel(wd->sc_dk.dk_label,
(struct disklabel *)addr, wd->sc_dk.dk_openmask);
if (error == 0) {
if (wd->drvp->state > RECAL)
wd->drvp->drive_flags |= DRIVE_RESET;
if (xfer == DIOCWDINFO)
error = writedisklabel(DISKLABELDEV(dev),
wdstrategy, wd->sc_dk.dk_label);
}
disk_unlock(&wd->sc_dk);
goto exit;
#ifdef notyet
case DIOCWFORMAT:
if ((flag & FWRITE) == 0)
return EBADF;
{
struct format_op *fop;
struct iovec aiov;
struct uio auio;
fop = (struct format_op *)addr;
aiov.iov_base = fop->df_buf;
aiov.iov_len = fop->df_count;
auio.uio_iov = &aiov;
auio.uio_iovcnt = 1;
auio.uio_resid = fop->df_count;
auio.uio_segflg = 0;
auio.uio_offset =
fop->df_startblk * wd->sc_dk.dk_label->d_secsize;
auio.uio_procp = p;
error = physio(wdformat, dev, B_WRITE, minphys, &auio);
fop->df_count -= auio.uio_resid;
fop->df_reg[0] = wdc->sc_status;
fop->df_reg[1] = wdc->sc_error;
goto exit;
}
#endif
default:
error = wdc_ioctl(wd->drvp, xfer, addr, flag, p);
goto exit;
}
#ifdef DIAGNOSTIC
panic("wdioctl: impossible");
#endif
exit:
device_unref(&wd->sc_dev);
return (error);
}
static void
cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
int channel;
pcireg_t rev = PCI_REVISION(pa->pa_class);
/*
* For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
* and base addresses registers can be disabled at
* hardware level. In this case, the device is wired
* in compat mode and its first channel is always enabled,
* but we can't rely on PCI_COMMAND_IO_ENABLE.
* In fact, it seems that the first channel of the CMD PCI0640
* can't be disabled.
*/
#ifdef PCIIDE_CMD064x_DISABLE
if (pciide_chipen(sc, pa) == 0)
return;
#endif
aprint_normal("%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
aprint_normal("\n");
sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
switch (sc->sc_pp->ide_product) {
case PCI_PRODUCT_CMDTECH_649:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 5;
sc->sc_wdcdev.irqack = cmd646_9_irqack;
break;
case PCI_PRODUCT_CMDTECH_648:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 4;
sc->sc_wdcdev.irqack = cmd646_9_irqack;
break;
case PCI_PRODUCT_CMDTECH_646:
if (rev >= CMD0646U2_REV) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 2;
} else if (rev >= CMD0646U_REV) {
/*
* Linux's driver claims that the 646U is broken
* with UDMA. Only enable it if we know what we're
* doing
*/
#ifdef PCIIDE_CMD0646U_ENABLEUDMA
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc->sc_wdcdev.UDMA_cap = 2;
#endif
/* explicitly disable UDMA */
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(0), 0);
pciide_pci_write(sc->sc_pc, sc->sc_tag,
CMD_UDMATIM(1), 0);
}
sc->sc_wdcdev.irqack = cmd646_9_irqack;
break;
default:
sc->sc_wdcdev.irqack = pciide_irqack;
}
}
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel;
WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
DEBUG_PROBE);
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++)
cmd_channel_map(pa, sc, channel);
/*
* note - this also makes sure we clear the irq disable and reset
* bits
*/
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
DEBUG_PROBE);
}
static void
piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
struct pciide_channel *cp;
int channel;
u_int32_t idetim;
bus_size_t cmdsize, ctlsize;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_normal("%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
aprint_normal("\n");
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82371AB_IDE:
case PCI_PRODUCT_INTEL_82440MX_IDE:
case PCI_PRODUCT_INTEL_82801AA_IDE:
case PCI_PRODUCT_INTEL_82801AB_IDE:
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
}
}
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82801AA_IDE:
sc->sc_wdcdev.UDMA_cap = 4;
break;
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
break;
default:
sc->sc_wdcdev.UDMA_cap = 2;
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
sc->sc_wdcdev.set_modes = piix_setup_channel;
else
sc->sc_wdcdev.set_modes = piix3_4_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
WDCDEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
WDCDEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
/* PIIX is compat-only */
if (pciide_chansetup(sc, channel, 0) == 0)
continue;
idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
if ((PIIX_IDETIM_READ(idetim, channel) &
PIIX_IDETIM_IDE) == 0) {
#if 1
aprint_normal("%s: %s channel ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
cp->wdc_channel.ch_flags |= WDCF_DISABLED;
continue;
#else
pcireg_t interface;
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
channel);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
idetim);
interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
sc->sc_tag, PCI_CLASS_REG));
aprint_normal("channel %d idetim=%08x interface=%02x\n",
channel, idetim, interface);
#endif
}
/* PIIX are compat-only pciide devices */
pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr);
}
WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
WDCDEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
WDCDEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
}
void
wdattach(struct device *parent, struct device *self, void *aux)
{
struct wd_softc *wd = (void *)self;
struct ata_atapi_attach *aa_link= aux;
struct wdc_command wdc_c;
int i, blank;
char buf[41], c, *p, *q;
WDCDEBUG_PRINT(("wdattach\n"), DEBUG_FUNCS | DEBUG_PROBE);
wd->openings = aa_link->aa_openings;
wd->drvp = aa_link->aa_drv_data;
strlcpy(wd->drvp->drive_name, wd->sc_dev.dv_xname,
sizeof(wd->drvp->drive_name));
wd->drvp->cf_flags = wd->sc_dev.dv_cfdata->cf_flags;
if ((NERRS_MAX - 2) > 0)
wd->drvp->n_dmaerrs = NERRS_MAX - 2;
else
wd->drvp->n_dmaerrs = 0;
/* read our drive info */
if (wd_get_params(wd, at_poll, &wd->sc_params) != 0) {
printf("%s: IDENTIFY failed\n", wd->sc_dev.dv_xname);
return;
}
for (blank = 0, p = wd->sc_params.atap_model, q = buf, i = 0;
i < sizeof(wd->sc_params.atap_model); i++) {
c = *p++;
if (c == '\0')
break;
if (c != ' ') {
if (blank) {
*q++ = ' ';
blank = 0;
}
*q++ = c;
} else
blank = 1;
}
*q++ = '\0';
printf(": <%s>\n", buf);
wdc_probe_caps(wd->drvp, &wd->sc_params);
wdc_print_caps(wd->drvp);
if ((wd->sc_params.atap_multi & 0xff) > 1) {
wd->sc_multi = wd->sc_params.atap_multi & 0xff;
} else {
wd->sc_multi = 1;
}
printf("%s: %d-sector PIO,", wd->sc_dev.dv_xname, wd->sc_multi);
/* use 48-bit LBA if enabled */
/* XXX: shall we use it if drive capacity < 137Gb? */
if ((wd->sc_params.atap_cmd2_en & ATAPI_CMD2_48AD) != 0)
wd->sc_flags |= WDF_LBA48;
/* Prior to ATA-4, LBA was optional. */
if ((wd->sc_params.atap_capabilities1 & WDC_CAP_LBA) != 0)
wd->sc_flags |= WDF_LBA;
#if 0
/* ATA-4 requires LBA. */
if (wd->sc_params.atap_ataversion != 0xffff &&
wd->sc_params.atap_ataversion >= WDC_VER_ATA4)
wd->sc_flags |= WDF_LBA;
#endif
if ((wd->sc_flags & WDF_LBA48) != 0) {
wd->sc_capacity =
(((u_int64_t)wd->sc_params.atap_max_lba[3] << 48) |
((u_int64_t)wd->sc_params.atap_max_lba[2] << 32) |
((u_int64_t)wd->sc_params.atap_max_lba[1] << 16) |
(u_int64_t)wd->sc_params.atap_max_lba[0]);
printf(" LBA48, %lluMB, %llu sectors\n",
wd->sc_capacity / (1048576 / DEV_BSIZE),
wd->sc_capacity);
} else if ((wd->sc_flags & WDF_LBA) != 0) {
wd->sc_capacity =
(wd->sc_params.atap_capacity[1] << 16) |
wd->sc_params.atap_capacity[0];
printf(" LBA, %lluMB, %llu sectors\n",
wd->sc_capacity / (1048576 / DEV_BSIZE),
wd->sc_capacity);
} else {
wd->sc_capacity =
wd->sc_params.atap_cylinders *
wd->sc_params.atap_heads *
wd->sc_params.atap_sectors;
printf(" CHS, %lluMB, %d cyl, %d head, %d sec, %llu sectors\n",
wd->sc_capacity / (1048576 / DEV_BSIZE),
wd->sc_params.atap_cylinders,
wd->sc_params.atap_heads,
wd->sc_params.atap_sectors,
wd->sc_capacity);
}
WDCDEBUG_PRINT(("%s: atap_dmatiming_mimi=%d, atap_dmatiming_recom=%d\n",
self->dv_xname, wd->sc_params.atap_dmatiming_mimi,
wd->sc_params.atap_dmatiming_recom), DEBUG_PROBE);
/* use read look ahead if supported */
if (wd->sc_params.atap_cmd_set1 & WDC_CMD1_AHEAD) {
bzero(&wdc_c, sizeof(struct wdc_command));
wdc_c.r_command = SET_FEATURES;
wdc_c.r_precomp = WDSF_READAHEAD_EN;
wdc_c.timeout = 1000;
wdc_c.flags = at_poll;
if (wdc_exec_command(wd->drvp, &wdc_c) != WDC_COMPLETE) {
printf("%s: enable look ahead command didn't "
"complete\n", wd->sc_dev.dv_xname);
}
}
/* use write cache if supported */
if (wd->sc_params.atap_cmd_set1 & WDC_CMD1_CACHE) {
bzero(&wdc_c, sizeof(struct wdc_command));
wdc_c.r_command = SET_FEATURES;
wdc_c.r_precomp = WDSF_EN_WR_CACHE;
wdc_c.timeout = 1000;
wdc_c.flags = at_poll;
if (wdc_exec_command(wd->drvp, &wdc_c) != WDC_COMPLETE) {
printf("%s: enable write cache command didn't "
"complete\n", wd->sc_dev.dv_xname);
}
}
/*
* FREEZE LOCK the drive so malicous users can't lock it on us.
* As there is no harm in issuing this to drives that don't
* support the security feature set we just send it, and don't
* bother checking if the drive sends a command abort to tell us it
* doesn't support it.
*/
bzero(&wdc_c, sizeof(struct wdc_command));
wdc_c.r_command = WDCC_SEC_FREEZE_LOCK;
wdc_c.timeout = 1000;
wdc_c.flags = at_poll;
if (wdc_exec_command(wd->drvp, &wdc_c) != WDC_COMPLETE) {
printf("%s: freeze lock command didn't complete\n",
wd->sc_dev.dv_xname);
}
/*
* Initialize disk structures.
*/
wd->sc_dk.dk_name = wd->sc_dev.dv_xname;
bufq_init(&wd->sc_bufq, BUFQ_DEFAULT);
timeout_set(&wd->sc_restart_timeout, wdrestart, wd);
/* Attach disk. */
disk_attach(&wd->sc_dev, &wd->sc_dk);
wd->sc_wdc_bio.lp = wd->sc_dk.dk_label;
}
/* Get the disk's parameters */
int
ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags,
struct ataparams *prms)
{
char tb[ATAPARAMS_SIZE];
struct wdc_command wdc_c;
int i;
u_int16_t *p;
int ret;
WDCDEBUG_PRINT(("ata_get_parms\n"), DEBUG_FUNCS);
bzero(tb, sizeof(tb));
bzero(&wdc_c, sizeof(struct wdc_command));
if (drvp->drive_flags & DRIVE_ATA) {
wdc_c.r_command = WDCC_IDENTIFY;
wdc_c.r_st_bmask = WDCS_DRDY;
wdc_c.r_st_pmask = 0;
wdc_c.timeout = 3000; /* 3s */
} else if (drvp->drive_flags & DRIVE_ATAPI) {
wdc_c.r_command = ATAPI_IDENTIFY_DEVICE;
wdc_c.r_st_bmask = 0;
wdc_c.r_st_pmask = 0;
wdc_c.timeout = 10000; /* 10s */
} else {
WDCDEBUG_PRINT(("wdc_ata_get_parms: no disks\n"),
DEBUG_FUNCS|DEBUG_PROBE);
return CMD_ERR;
}
wdc_c.flags = AT_READ | flags;
wdc_c.data = tb;
wdc_c.bcount = ATAPARAMS_SIZE;
if ((ret = wdc_exec_command(drvp, &wdc_c)) != WDC_COMPLETE) {
WDCDEBUG_PRINT(("%s: wdc_exec_command failed: %d\n",
__func__, ret), DEBUG_PROBE);
return CMD_AGAIN;
}
if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
WDCDEBUG_PRINT(("%s: IDENTIFY failed: 0x%x\n", __func__,
wdc_c.flags), DEBUG_PROBE);
return CMD_ERR;
} else {
#if BYTE_ORDER == BIG_ENDIAN
/* All the fields in the params structure are 16-bit
integers except for the ID strings which are char
strings. The 16-bit integers are currently in
memory in little-endian, regardless of architecture.
So, they need to be swapped on big-endian architectures
before they are accessed through the ataparams structure.
The swaps below avoid touching the char strings.
*/
swap16_multi((u_int16_t *)tb, 10);
swap16_multi((u_int16_t *)tb + 20, 3);
swap16_multi((u_int16_t *)tb + 47, ATAPARAMS_SIZE / 2 - 47);
#endif
/* Read in parameter block. */
bcopy(tb, prms, sizeof(struct ataparams));
/*
* Shuffle string byte order.
* ATAPI Mitsumi and NEC drives don't need this.
*/
if ((prms->atap_config & WDC_CFG_ATAPI_MASK) ==
WDC_CFG_ATAPI &&
((prms->atap_model[0] == 'N' &&
prms->atap_model[1] == 'E') ||
(prms->atap_model[0] == 'F' &&
prms->atap_model[1] == 'X')))
return CMD_OK;
for (i = 0; i < sizeof(prms->atap_model); i += 2) {
p = (u_short *)(prms->atap_model + i);
*p = swap16(*p);
}
for (i = 0; i < sizeof(prms->atap_serial); i += 2) {
p = (u_short *)(prms->atap_serial + i);
*p = swap16(*p);
}
for (i = 0; i < sizeof(prms->atap_revision); i += 2) {
p = (u_short *)(prms->atap_revision + i);
*p = swap16(*p);
}
return CMD_OK;
}
}
void
wdc_atapi_ctrl(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
char *errstring = NULL;
wdc_atapi_update_status(chp);
if (!timeout) {
switch (drvp->state) {
case ATAPI_IDENTIFY_WAIT_STATE:
if (chp->ch_status & WDCS_BSY)
return;
break;
default:
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
return;
break;
}
}
if (!wdc_atapi_drive_selected(chp, xfer->drive))
{
wdc_set_drive(chp, xfer->drive);
delay (1);
}
if (timeout) {
int trigger_timeout = 1;
switch (drvp->state) {
case ATAPI_DEVICE_RESET_WAIT_STATE:
errstring = "Device Reset Wait";
drvp->drive_flags &= ~DRIVE_DEVICE_RESET;
break;
case ATAPI_IDENTIFY_WAIT_STATE:
errstring = "Identify";
if (!(chp->ch_status & WDCS_BSY) &&
(chp->ch_status & (WDCS_DRQ | WDCS_ERR)))
trigger_timeout = 0;
break;
case ATAPI_PIOMODE_STATE:
errstring = "Post-Identify";
if (!(chp->ch_status & (WDCS_BSY | WDCS_DRQ)))
trigger_timeout = 0;
break;
case ATAPI_PIOMODE_WAIT_STATE:
errstring = "PIOMODE";
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
drvp->drive_flags &= ~DRIVE_MODE;
else
trigger_timeout = 0;
break;
case ATAPI_DMAMODE_WAIT_STATE:
errstring = "dmamode";
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
else
trigger_timeout = 0;
break;
default:
errstring = "unknown state";
break;
}
if (trigger_timeout)
goto timeout;
}
WDCDEBUG_PRINT(("wdc_atapi_ctrl %s:%d:%d state %d\n",
chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive, drvp->state),
DEBUG_INTR | DEBUG_FUNCS);
switch (drvp->state) {
/* My ATAPI slave device likes to assert DASP-/PDIAG- until
it is DEVICE RESET. This causes the LED to stay on.
There is a trade-off here. This drive will cause any
play-back or seeks happening to be interrupted.
Note that the bus reset that triggered this state
(which may have been caused by the other drive on
the chain) need not interrupt this playback. It happens
to on my Smart & Friendly CD burner.
- csapuntz@
*/
case ATAPI_RESET_BASE_STATE:
if ((drvp->drive_flags & DRIVE_DEVICE_RESET) == 0) {
drvp->state = ATAPI_IDENTIFY_STATE;
break;
}
wdccommandshort(chp, drvp->drive, ATAPI_DEVICE_RESET);
drvp->state = ATAPI_DEVICE_RESET_WAIT_STATE;
ret->delay = ATAPI_RESET_DELAY;
ret->timeout = ATAPI_RESET_WAIT;
break;
case ATAPI_DEVICE_RESET_WAIT_STATE:
/* FALLTHROUGH */
case ATAPI_IDENTIFY_STATE:
wdccommandshort(chp, drvp->drive, ATAPI_IDENTIFY_DEVICE);
drvp->state = ATAPI_IDENTIFY_WAIT_STATE;
ret->delay = 10;
ret->timeout = ATAPI_RESET_WAIT;
break;
case ATAPI_IDENTIFY_WAIT_STATE: {
int idx = 0;
while ((chp->ch_status & WDCS_DRQ) &&
idx++ < 20) {
wdcbit_bucket(chp, 512);
DELAY(1);
wdc_atapi_update_status(chp);
}
drvp->state = ATAPI_PIOMODE_STATE;
/*
* Note, we can't go directly to set PIO mode
* because the drive is free to assert BSY
* after the transfer
*/
break;
}
case ATAPI_PIOMODE_STATE:
/* Don't try to set mode if controller can't be adjusted */
if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0)
goto ready;
/* Also don't try if the drive didn't report its mode */
if ((drvp->drive_flags & DRIVE_MODE) == 0)
goto ready;
/* SET FEATURES 0x08 is only for PIO mode > 2 */
if (drvp->PIO_mode <= 2)
goto ready;
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x08 | drvp->PIO_mode, WDSF_SET_MODE);
drvp->state = ATAPI_PIOMODE_WAIT_STATE;
ret->timeout = ATAPI_CTRL_WAIT;
ret->expect_irq = 1;
break;
case ATAPI_PIOMODE_WAIT_STATE:
if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
chp->wdc->irqack(chp);
if (chp->ch_status & WDCS_ERR) {
/* Downgrade straight to PIO mode 3 */
drvp->PIO_mode = 3;
chp->wdc->set_modes(chp);
}
/* FALLTHROUGH */
case ATAPI_DMAMODE_STATE:
if (drvp->drive_flags & DRIVE_UDMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
} else if (drvp->drive_flags & DRIVE_DMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x20 | drvp->DMA_mode, WDSF_SET_MODE);
} else {
goto ready;
}
drvp->state = ATAPI_DMAMODE_WAIT_STATE;
ret->timeout = ATAPI_CTRL_WAIT;
ret->expect_irq = 1;
break;
case ATAPI_DMAMODE_WAIT_STATE:
if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
chp->wdc->irqack(chp);
if (chp->ch_status & WDCS_ERR)
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
/* FALLTHROUGH */
case ATAPI_READY_STATE:
ready:
drvp->state = ATAPI_READY_STATE;
xfer->next = wdc_atapi_real_start;
break;
}
return;
timeout:
printf("%s:%d:%d: %s timed out\n",
chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring);
sc_xfer->error = XS_TIMEOUT;
xfer->next = wdc_atapi_reset;
return;
}
