/* MT6306 GPIO7 is GPIO_GPS_LNA_EN, for K2 common phone pin modification	*/
static INT32 wmt_plat_gps_lna_ctrl(ENUM_PIN_STATE state)
{
#ifdef GPIO_GPS_LNA_PIN
	switch (state) {
	case PIN_STA_INIT:
	case PIN_STA_DEINIT:
		WMT_PLAT_ERR_FUNC("Gps LNA pin ctrl %d!\n", state);
		mt6306_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
		mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
		break;
	case PIN_STA_OUT_H:
		WMT_PLAT_ERR_FUNC("Gps LNA pin output high!\n");
		mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
		break;
	case PIN_STA_OUT_L:
		WMT_PLAT_ERR_FUNC("Gps LNA pin output low!\n");
		mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
		break;
	default:
		WMT_PLAT_WARN_FUNC("%d mode not defined for  gps lna pin !!!\n", state);
		break;
	}
	return 0;
#else
	WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
	    return 0;
#endif
}
UINT32 wmt_plat_force_trigger_assert(ENUM_FORCE_TRG_ASSERT_T type)
{
	UINT8 * p_virtual_addr = NULL;
	
	switch(type){
		case STP_FORCE_TRG_ASSERT_EMI:

			WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi -->\n");
    		p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_OUTBAND_ASSERT_W1);
    		if(!p_virtual_addr)
    		{
    			WMT_PLAT_ERR_FUNC("get virtual address fail\n");
    			return -1;
    		}

    		CONSYS_REG_WRITE(p_virtual_addr, EXP_APMEM_HOST_OUTBAND_ASSERT_MAGIC_W1);
        	WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi <--\n");
		break;
		case STP_FORCE_TRG_ASSERT_DEBUG_PIN:

			CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_WAKEUP_BIT);
			WMT_PLAT_INFO_FUNC("enable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
			usleep_range(64, 96);
			CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_WAKEUP_BIT);
			WMT_PLAT_INFO_FUNC("disable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));

		break;
		default:
			WMT_PLAT_ERR_FUNC("unknow force trigger assert type\n");
		break;
	}

	return 0;
}
INT32 mtk_wcn_consys_hw_vcn28_ctrl(UINT32 enable)
{
	if (enable) {
		/*in co-clock mode,need to turn on vcn28 when fm on */
#if CONSYS_PMIC_CTRL_ENABLE
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
		if (reg_VCN28) {
			regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
			if (regulator_enable(reg_VCN28))
				WMT_PLAT_ERR_FUNC("WMT do VCN28 PMIC on fail!\n");
		}
#endif
#endif
		WMT_PLAT_INFO_FUNC("turn on vcn28 for fm/gps usage in co-clock mode\n");
	} else {
		/*in co-clock mode,need to turn off vcn28 when fm off */
#if CONSYS_PMIC_CTRL_ENABLE
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
		if (reg_VCN28)
			regulator_disable(reg_VCN28);
#endif
#endif
		WMT_PLAT_INFO_FUNC("turn off vcn28 for fm/gps usage in co-clock mode\n");
	}
	return 0;
}
INT32 mtk_wcn_consys_hw_restore(struct device *device)
{
	UINT32 addrPhy = 0;

	if (gConEmiPhyBase) {

#if CONSYS_EMI_MPU_SETTING
		/*set MPU for EMI share Memory */
		WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");

#if defined(CONFIG_ARCH_MT6735)
		emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
							gConEmiPhyBase + SZ_1M - 1,
							13,
							SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
							FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));

#elif defined(CONFIG_ARCH_MT6735M)
		emi_mpu_set_region_protection(gConEmiPhyBase,
							gConEmiPhyBase + SZ_1M - 1,
							6,
							SET_ACCESS_PERMISSON(FORBIDDEN, NO_PROTECTION, FORBIDDEN,
							NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6753)
		emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
							gConEmiPhyBase + SZ_1M - 1,
							13,
							SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN,
							FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));

#else
		WMT_PLAT_WARN_FUNC("not define platform config\n");
#endif

#endif
		/*consys to ap emi remapping register:10000320, cal remapping address */
		addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;

		/*enable consys to ap emi remapping bit12 */
		addrPhy = addrPhy | 0x1000;

		CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET,
				 CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET) | addrPhy);

		WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump in restore cb(0x%08x)\n",
				   CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET));

#if 1
		pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + SZ_1M / 2, CONSYS_EMI_MEM_SIZE);
#else
		pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE, CONSYS_EMI_MEM_SIZE);
#endif
		if (pEmibaseaddr) {
			WMT_PLAT_WARN_FUNC("EMI mapping OK(0x%p)\n", pEmibaseaddr);
			memset_io(pEmibaseaddr, 0, CONSYS_EMI_MEM_SIZE);
		} else {
			WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
		}
	} else {
/*!
 * \brief audio control callback function for CMB_STUB on ALPS
 *
 * A platform function required for dynamic binding with CMB_STUB on ALPS.
 *
 * \param state desired audio interface state to use
 * \param flag audio interface control options
 *
 * \retval 0 operation success
 * \retval -1 invalid parameters
 * \retval < 0 error for operation fail
 */
INT32 wmt_plat_audio_ctrl(CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl)
{
	INT32 iRet = 0;

	/* input sanity check */
	if ((CMB_STUB_AIF_MAX <= state)
	    || (CMB_STUB_AIF_CTRL_MAX <= ctrl)) {
		return -1;
	}

	iRet = 0;

	/* set host side first */
	switch (state) {
	case CMB_STUB_AIF_0:
		/* BT_PCM_OFF & FM line in/out */
		iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
		break;

	case CMB_STUB_AIF_1:
		iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
		break;

	case CMB_STUB_AIF_2:
		iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
		break;

	case CMB_STUB_AIF_3:
		iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
		break;

	default:
		/* FIXME: move to cust folder? */
		WMT_PLAT_ERR_FUNC("invalid state [%d]\n", state);
		iRet = -1;
		break;
	}

	if (CMB_STUB_AIF_CTRL_EN == ctrl) {
		WMT_PLAT_INFO_FUNC("call chip aif setting\n");
		/* need to control chip side GPIO */
		if (NULL != wmt_plat_audio_if_cb) {
			iRet += (*wmt_plat_audio_if_cb) (state, MTK_WCN_BOOL_FALSE);
		} else {
			WMT_PLAT_WARN_FUNC("wmt_plat_audio_if_cb is not registered\n");
			iRet -= 1;
		}

	} else {
		WMT_PLAT_INFO_FUNC("skip chip aif setting\n");
	}

	return iRet;

}
VOID __init mtk_wcn_consys_memory_reserve(VOID)
{
	gConEmiPhyBase = arm_memblock_steal(SZ_1M,SZ_1M);

	if(gConEmiPhyBase)
	{
		WMT_PLAT_INFO_FUNC("memblock done: 0x%x\n",gConEmiPhyBase);
	}else
	{
		WMT_PLAT_ERR_FUNC("memblock fail\n");
	}
}
INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
	static INT32 counter;
	INT32 status;
	INT32 ret = 0;

	ret = mutex_lock_killable(&gOsSLock);
	if (ret) {
		WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
		return ret;
	}

	if (WL_OP_GET == opId)
		++counter;
	else if (WL_OP_PUT == opId)
		--counter;

	mutex_unlock(&gOsSLock);
	if (WL_OP_GET == opId && counter == 1) {
		#ifdef CONFIG_PM_WAKELOCKS
		__pm_stay_awake(&wmtWakeLock);
		status = wmtWakeLock.active;
		#else
		wake_lock(&wmtWakeLock);
		status = wake_lock_active(&wmtWakeLock);
		#endif
		WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", status, counter);

	} else if (WL_OP_PUT == opId && counter == 0) {
		#ifdef CONFIG_PM_WAKELOCKS
		__pm_relax(&wmtWakeLock);
		status = wmtWakeLock.active;
		#else
		wake_unlock(&wmtWakeLock);
		status = wake_lock_active(&wmtWakeLock);
		#endif
		WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", status, counter);
	} else {
		#ifdef CONFIG_PM_WAKELOCKS
		status = wmtWakeLock.active;
		#else
		status = wake_lock_active(&wmtWakeLock);
		#endif
		WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", status, counter);
	}
	return 0;
#else
	WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.\n");
	return 0;

#endif
}
INT32 wmt_plat_get_dump_info(UINT32 offset)
{
	PUINT8 p_virtual_addr = NULL;

	p_virtual_addr = wmt_plat_get_emi_virt_add(offset);
	if (!p_virtual_addr) {
		WMT_PLAT_ERR_FUNC("get virtual address fail\n");
		return -1;
	}
	WMT_PLAT_WARN_FUNC("connsys_reg_read (0x%x), (0x%p), (0x%x)\n", CONSYS_REG_READ(p_virtual_addr), p_virtual_addr,
			   offset);
	return CONSYS_REG_READ(p_virtual_addr);
}
INT32 wmt_plat_get_dump_info(UINT32 offset)
{
	UINT8 * p_virtual_addr = NULL;

	p_virtual_addr = wmt_plat_get_emi_virt_add(offset);
	if(!p_virtual_addr)
	{
		WMT_PLAT_ERR_FUNC("get virtual address fail\n");
		return -1;
	}

	return CONSYS_REG_READ(p_virtual_addr);
}
UINT8  *mtk_wcn_consys_emi_virt_addr_get(UINT32 ctrl_state_offset)
{
	UINT8 *p_virtual_addr = NULL;

	if(!pEmibaseaddr)
	{
		WMT_PLAT_ERR_FUNC("EMI base address is NULL\n");
		return NULL;
	}
	WMT_PLAT_DBG_FUNC("ctrl_state_offset(%08x)\n",ctrl_state_offset);
	p_virtual_addr = pEmibaseaddr + ctrl_state_offset;

	return p_virtual_addr;
}
INT32 wmt_plat_set_host_dump_state(ENUM_HOST_DUMP_STATE state)
{
	PUINT8 p_virtual_addr = NULL;

	p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_SYNC_STATE);
	if (!p_virtual_addr) {
		WMT_PLAT_ERR_FUNC("get virtual address fail\n");
		return -1;
	}

	CONSYS_REG_WRITE(p_virtual_addr, state);

	return 0;
}
INT32 wmt_plat_update_host_sync_num(VOID)
{
	PUINT8 p_virtual_addr = NULL;
	UINT32 sync_num = 0;

	p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_SYNC_NUM);
	if (!p_virtual_addr) {
		WMT_PLAT_ERR_FUNC("get virtual address fail\n");
		return -1;
	}

	sync_num = CONSYS_REG_READ(p_virtual_addr);
	CONSYS_REG_WRITE(p_virtual_addr, sync_num + 1);

	return 0;
}
INT32 wmt_plat_i2s_ctrl(ENUM_PIN_STATE state)
{
	/* TODO: [NewFeature][GeorgeKuo]: GPIO_I2Sx is changed according to different project. */
	/* TODO: provide a translation table in board_custom.h for different ALPS project customization. */
#if defined(CONFIG_MTK_GPIO_LEGACY)

#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#if defined(GPIO_COMBO_I2S_CK_PIN)
	switch (state) {
	case PIN_STA_INIT:
	case PIN_STA_MUX:
		mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_I2S0_CK);
		mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_I2S0_WS);
		mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_I2S0_DAT);
		WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S init (I2S0 system)\n");
		break;
	case PIN_STA_IN_L:
	case PIN_STA_DEINIT:
		mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_GPIO);
		mt_set_gpio_dir(GPIO_COMBO_I2S_CK_PIN, GPIO_DIR_OUT);
		mt_set_gpio_out(GPIO_COMBO_I2S_CK_PIN, GPIO_OUT_ZERO);

		mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_GPIO);
		mt_set_gpio_dir(GPIO_COMBO_I2S_WS_PIN, GPIO_DIR_OUT);
		mt_set_gpio_out(GPIO_COMBO_I2S_WS_PIN, GPIO_OUT_ZERO);

		mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_GPIO);
		mt_set_gpio_dir(GPIO_COMBO_I2S_DAT_PIN, GPIO_DIR_OUT);
		mt_set_gpio_out(GPIO_COMBO_I2S_DAT_PIN, GPIO_OUT_ZERO);
		WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S deinit (out 0)\n");
		break;
	default:
		WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on I2S Group\n", state);
		break;
	}
#else
	WMT_PLAT_ERR_FUNC("[MT6620]Error:FM digital mode set, but no I2S GPIOs defined\n");
#endif
#else
	WMT_PLAT_INFO_FUNC
	    ("[MT6620]warnning:FM digital mode is not set, no I2S GPIO settings should be modified by combo driver\n");
#endif

#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
	return 0;
}
INT32 mtk_wcn_regulator_get(void)
{
	INT32 iRet = -1;
	if(!(IS_ERR(wmt_dev))){
		reg_V18 = regulator_get(wmt_dev,"VCN_1V8");
		if(reg_V18)
			WMT_PLAT_INFO_FUNC("Regulator_get VCN_1V8 sucess\n");
		reg_V33_BT = regulator_get(wmt_dev,"VCN33_BT");
		if(reg_V33_BT)
			WMT_PLAT_INFO_FUNC("Regulator_get VCN33_BT sucess\n");
		reg_V33_WIFI = regulator_get(wmt_dev,"VCN33_WIFI");
		if(reg_V33_WIFI)
			WMT_PLAT_INFO_FUNC("Regulator_get VCN33_WIFI sucess\n");
		iRet = 0;
	}else
		WMT_PLAT_ERR_FUNC("wmt_dev device pointer error, cannot do VCN18 power on!\n");
	return iRet;
}
INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
    static INT32 counter = 0;
    INT32 ret = 0;
    
    
    ret = mutex_lock_killable( &gOsSLock);
    if (ret) {
        WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
        return ret;
    }
    
    if (WL_OP_GET == opId)
    {
        ++counter;
    }else if (WL_OP_PUT == opId)
    {
        --counter;
    }
    mutex_unlock( &gOsSLock);
    if (WL_OP_GET == opId && counter == 1)
    {
        wake_lock(&wmtWakeLock);
        WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);    
        
    }
    else if (WL_OP_PUT == opId && counter == 0)
    {
        wake_unlock(&wmtWakeLock);
        WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter); 
    }
    else
    {
        WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter); 
    }
    return 0;
#else
    WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.");
    return 0;

#endif
}
static INT32 mtk_wmt_probe(struct platform_device *pdev)
{
#if !defined(CONFIG_MTK_CLKMGR)
	clk_scp_conn_main = devm_clk_get(&pdev->dev, "conn");
	if (IS_ERR(clk_scp_conn_main)) {
		WMT_PLAT_ERR_FUNC("[CCF]cannot get clk_scp_conn_main clock.\n");
		return PTR_ERR(clk_scp_conn_main);
	}
	WMT_PLAT_DBG_FUNC("[CCF]clk_scp_conn_main=%p\n", clk_scp_conn_main);

	clk_infra_conn_main = devm_clk_get(&pdev->dev, "bus");
	if (IS_ERR(clk_infra_conn_main)) {
		WMT_PLAT_ERR_FUNC("[CCF]cannot get clk_infra_conn_main clock.\n");
		return PTR_ERR(clk_infra_conn_main);
	}
	WMT_PLAT_DBG_FUNC("[CCF]clk_infra_conn_main=%p\n", clk_infra_conn_main);
#endif /* !defined(CONFIG_MTK_CLKMGR) */

#if CONSYS_PMIC_CTRL_ENABLE
#if !defined(CONFIG_MTK_PMIC_LEGACY)
	reg_VCN18 = regulator_get(&pdev->dev, "vcn18");
	if (!reg_VCN18)
		WMT_PLAT_ERR_FUNC("Regulator_get VCN_1V8 fail\n");
	reg_VCN28 = regulator_get(&pdev->dev, "vcn28");
	if (!reg_VCN28)
		WMT_PLAT_ERR_FUNC("Regulator_get VCN_2V8 fail\n");
	reg_VCN33_BT = regulator_get(&pdev->dev, "vcn33_bt");
	if (!reg_VCN33_BT)
		WMT_PLAT_ERR_FUNC("Regulator_get VCN33_BT fail\n");
	reg_VCN33_WIFI = regulator_get(&pdev->dev, "vcn33_wifi");
	if (!reg_VCN33_WIFI)
		WMT_PLAT_ERR_FUNC("Regulator_get VCN33_WIFI fail\n");
#endif
#endif

#if !defined(CONFIG_MTK_GPIO_LEGACY)
	consys_pinctrl = devm_pinctrl_get(&pdev->dev);
	if (IS_ERR(consys_pinctrl)) {
		WMT_PLAT_ERR_FUNC("cannot find consys pinctrl.\n");
		return PTR_ERR(consys_pinctrl);
	}
#endif /* !defined(CONFIG_MTK_GPIO_LEGACY) */

	return 0;
}
INT32 mtk_wcn_consys_hw_init()
{
	INT32 iRet = -1;
	UINT32 addrPhy = 0;

	/*set MPU for EMI share Memory*/
	WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
	emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M/2,
		gConEmiPhyBase + SZ_1M,
		5,
		SET_ACCESS_PERMISSON(FORBIDDEN,NO_PROTECTION,FORBIDDEN,NO_PROTECTION));
	WMT_PLAT_INFO_FUNC("get consys start phy address(0x%x)\n",gConEmiPhyBase);

	/*consys to ap emi remapping register:10001310, cal remapping address*/
	addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;

	/*enable consys to ap emi remapping bit12*/
	addrPhy = addrPhy | 0x1000;

	CONSYS_REG_WRITE(CONSYS_EMI_MAPPING,CONSYS_REG_READ(CONSYS_EMI_MAPPING) | addrPhy);

	WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
#if 1
	pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + CONSYS_EMI_AP_PHY_OFFSET,CONSYS_EMI_MEM_SIZE);
#else
	pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE,CONSYS_EMI_MEM_SIZE);
#endif
	//pEmibaseaddr = ioremap_nocache(0x80090400,270*KBYTE);
	if(pEmibaseaddr)
	{
		WMT_PLAT_INFO_FUNC("EMI mapping OK(0x%p)\n",pEmibaseaddr);
		memset(pEmibaseaddr,0,CONSYS_EMI_MEM_SIZE);
		iRet = 0;
	}else{
		WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
	}
	WMT_PLAT_INFO_FUNC("register connsys restore cb for complying with IPOH function\n");
	register_swsusp_restore_noirq_func(ID_M_CONNSYS,mtk_wcn_consys_hw_restore,NULL);

	return iRet;
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{

	if (enable) {
		/*do BT PMIC on,depenency PMIC API ready */
		/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1 */
#if CONSYS_PMIC_CTRL_ENABLE
		/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600 */
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerOn(MT6328_POWER_LDO_VCN33_BT, VOL_3300, "wcn_drv");
#else
		if (reg_VCN33_BT) {
			regulator_set_voltage(reg_VCN33_BT, VOL_3300, VOL_3300);
			if (regulator_enable(reg_VCN33_BT))
				WMT_PLAT_ERR_FUNC("WMT do BT PMIC on fail!\n");
		}
#endif
		pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 1);

#endif
		WMT_PLAT_INFO_FUNC("WMT do BT PMIC on\n");
	} else {
		/*do BT PMIC off */
		/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0 */
#if CONSYS_PMIC_CTRL_ENABLE
		pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerDown(MT6328_POWER_LDO_VCN33_BT, "wcn_drv");
#else
		if (reg_VCN33_BT)
			regulator_disable(reg_VCN33_BT);
#endif
#endif
		WMT_PLAT_INFO_FUNC("WMT do BT PMIC off\n");
	}

	return 0;

}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{

#if PWR_ON_OFF_API_AVALIABLE
	INT32 iRet = -1;
#endif

	UINT32 retry = 10;
	UINT32 consysHwChipId = 0;
	
	WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
	WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));

	if(on)
	{
#if CONSYS_PMIC_CTRL_ENABLE 
		/*need PMIC driver provide new API protocol */
	    /*1.AP power on MT6325 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8	"0x0512[1] "1'b0   0x0512[14]"	1'b1"*/
		mt6325_upmu_set_rg_vcn18_on_ctrl(0);
		/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800, VOL_2500, VOL_2800, VOL_3000, VOL_3300*/
		hwPowerOn(MT6325_POWER_LDO_VCN18, VOL_1800, "wcn_drv"); 

		udelay(150);
		
		if(co_clock_en)
		{
			/*if co-clock mode:*/
			/*2.set VCN28 to SW control mode (with PMIC_WRAP API) VCN28_ON_CTRL 	0x041C[14]	1'b0*/
			/*turn on VCN28 LDO only when FMSYS is activated"  */
			mt6325_upmu_set_rg_vcn28_on_ctrl(0);
		}
		else
		{
			/*if NOT co-clock:*/
			/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) VCN28_ON_CTRL  0x041C[14] 1'b1*/
			mt6325_upmu_set_rg_vcn28_on_ctrl(1);
			/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)"  RG_VCN28_EN"	 0x041C[12] 1'b1	*/
			hwPowerOn(MT6325_POWER_LDO_VCN28, VOL_2800, "wcn_drv"); 
		}
#endif

		/*3.assert CONNSYS CPU SW reset  0x10007018	"[12]=1'b1  [31:24]=8'h88 (key)"*/
		CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG, (CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY));
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
		/*turn on top clock gating enable	TOP_CLKCG_CLR	0x10000084[26]	1'b1	*/
		CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
		/*turn on SPM clock gating enable	PWRON_CONFG_EN	0x10006000	32'h0b160001	*/
		CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);		

#if PWR_ON_OFF_API_AVALIABLE
		iRet = conn_power_on(); //consult clkmgr owner
		if(iRet)
		{
			WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
		}else
		{
			WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
		}
#else
		/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr)	conn_spm_pwr_on 0x10006280 [2]	1'b1		*/			
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
		/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr)	pwr_conn_ack	0x1000660C [1]			*/		
		while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)));
		/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr)	sram_conn_pd	0x10006280 [8]	1'b1	*/		
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SRAM_CONN_PD_BIT);
		/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr)	conn_spm_pwr_on_s	0x10006280 [3]	1'b1	*/					
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
		/*6.write conn_clk_dis=0, enable connsys clock	(MT6572 with the same addr) conn_clk_dis	0x10006280 [4]	1'b0				*/		
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
		/*7.wait 1us	*/	
		udelay(1);
		/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr)	pwr_conn_ack_s	0x10006610 [1]	*/						
		while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)));
		/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso	0x10006280 [1]	1'b0		*/				
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
		/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0]	1'b1	*/					
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
#endif

		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
		/*11.26M is ready now, delay 10us for mem_pd de-assert*/
		udelay(10);
		/*enable AP bus clock : connmcu_bus_pd  API: enable_clock() ++??*/
		
		/*12.poll CONNSYS CHIP ID until 6580 is returned		0x18070008	32'h6752 */
		while (retry-- > 0)
		{
			WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
			consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
			if(consysHwChipId == 0x6580)
			{
				WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
				break;
			}
			msleep(20);
		}

		/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed		0x18070114	"[3:0] ROM DELSEL [7:$] RAM4Kx32 DELSEL"	??*/
		
		/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1")	ACR	0x18070110[18]	1'b1*/
		/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
		/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
		CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG, CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);

		/*update ANA_WBG(AFE) CR. AFE setting file:  MT6752_AFE_SW_patch_REG_xxxx.xlsx ??"		AP Offset = 0x180B2000	??*/

#if 0
		/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
		update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
		CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
		/*16.deassert CONNSYS CPU SW reset (need to check MT6580)		 0x10007018	"[12]=1'b0 [31:24] =8'h88 (key)"*/
		CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
			(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);

		msleep(5);

	}else{

#if PWR_ON_OFF_API_AVALIABLE

		WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
		/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off()	*/
		iRet = conn_power_off();//consult clkmgr owner 
		WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
		if(iRet)
		{
			WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
		}else
		{
			WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
		}
#else
		/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr)		0x10006280[0]	1'b0		*/		
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
		/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr)	0x10006280 [1]	1'b1	*/
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
		/*DA_WBG_EN_XBUF=0		*/										
		/*wait 1us	*/
		udelay(1);
		/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr)		0x10006280 [8]	1'b0	  */	
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SRAM_CONN_PD_BIT);
		/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 	0x10006280 [3:2]	2'b00 */	
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
		/*write conn_clk_dis=1, disable connsys clock  (MT6572 with the same addr)	conn_clk_dis	0x10006280 [4]	1'b1	*/
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) |CONSYS_CLK_CTRL_BIT);
#endif

#if CONSYS_PMIC_CTRL_ENABLE

		/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
		mt6325_upmu_set_rg_vcn28_on_ctrl(0);
		/*turn off VCN28 LDO (with PMIC_WRAP API)"	 2. RG_VCN28_EN"  0x041C[12]" 1'b0*/
		hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");

		/*AP power off MT6625L VCN_1V8 LDO (with PMIC_WRAP API)  "0x0512[1]1'b0  0x0512[14]" 1'b0*/
		mt6325_upmu_set_rg_vcn18_mode_set(0);
		hwPowerDown(MT6325_POWER_LDO_VCN18, "wcn_drv"); 

#endif

	}
	WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
	return 0;
}
INT32 wmt_plat_eirq_ctrl(ENUM_PIN_ID id, ENUM_PIN_STATE state)
{
#ifdef CONFIG_OF
	struct device_node *node;
	unsigned int irq_info[3] = { 0, 0, 0 };
#endif
	INT32 iret = -EINVAL;
	static INT32 bgf_irq_num = -1;
	static UINT32 bgf_irq_flag;
	/* TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls */

	if ((PIN_STA_INIT != state)
	    && (PIN_STA_DEINIT != state)
	    && (PIN_STA_EINT_EN != state)
	    && (PIN_STA_EINT_DIS != state)) {
		WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
		return -1;
	}

	switch (id) {
	case PIN_BGF_EINT:

		if (PIN_STA_INIT == state) {
#ifdef CONFIG_OF
			node = of_find_compatible_node(NULL, NULL, "mediatek,mt6735-consys");
			if (node) {
				bgf_irq_num = irq_of_parse_and_map(node, 0);
				/* get the interrupt line behaviour */
				if (of_property_read_u32_array(node, "interrupts", irq_info, ARRAY_SIZE(irq_info))) {
					WMT_PLAT_ERR_FUNC("get irq flags from DTS fail!!\n");
					return iret;
				}
				bgf_irq_flag = irq_info[2];
				WMT_PLAT_INFO_FUNC("get irq id(%d) and irq trigger flag(%d) from DT\n", bgf_irq_num,
						   bgf_irq_flag);
			} else {
				WMT_PLAT_ERR_FUNC("[%s] can't find CONSYS compatible node\n", __func__);
				return iret;
			}
#else
			bgf_irq_num = MT_CONN2AP_BTIF_WAKEUP_IRQ_ID;
			bgf_irq_flag = IRQF_TRIGGER_LOW;
#endif
			iret = request_irq(bgf_irq_num, wmt_plat_bgf_irq_isr, bgf_irq_flag, "BTIF_WAKEUP_IRQ", NULL);
			if (iret) {
				WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n", bgf_irq_num, iret);
				return iret;
			}
			gbgfIrqBle.counter = 1;

		} else if (PIN_STA_EINT_EN == state) {

			spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
			if (gbgfIrqBle.counter) {
				WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n", gbgfIrqBle.counter);
			} else {
				enable_irq(bgf_irq_num);
				gbgfIrqBle.counter++;
			}
			WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en)\n");
			spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
		} else if (PIN_STA_EINT_DIS == state) {
			spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
			if (!gbgfIrqBle.counter) {
				WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n", gbgfIrqBle.counter);
			} else {
				disable_irq_nosync(bgf_irq_num);
				gbgfIrqBle.counter--;
			}
			WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis)\n");
			spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
		} else {
			free_irq(bgf_irq_num, NULL);
			/* de-init: nothing to do in ALPS, such as un-registration... */
		}
		iret = 0;
		break;

	default:
		WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
		iret = -1;
		break;
	}

	return iret;
}
static INT32 wmt_plat_gps_lna_ctrl(ENUM_PIN_STATE state)
{
#if !defined(CONFIG_MTK_GPIO_LEGACY)
	static struct pinctrl_state *gps_lna_init;
	static struct pinctrl_state *gps_lna_oh;
	static struct pinctrl_state *gps_lna_ol;
	static struct pinctrl *consys_pinctrl;

	WMT_PLAT_DBG_FUNC("ENTER++\n");
	consys_pinctrl = mtk_wcn_consys_get_pinctrl();
	if (NULL == consys_pinctrl) {
		WMT_PLAT_ERR_FUNC("get consys pinctrl fail\n");
		return -1;
	}

	gps_lna_init = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_init");
	if (NULL == gps_lna_init) {
		WMT_PLAT_ERR_FUNC("Cannot find gps lna pin init state!\n");
		return -2;
	}

	gps_lna_oh = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_oh");
	if (NULL == gps_lna_oh) {
		WMT_PLAT_ERR_FUNC("Cannot find gps lna pin oh state!\n");
		return -3;
	}

	gps_lna_ol = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_ol");
	if (NULL == gps_lna_ol) {
		WMT_PLAT_ERR_FUNC("Cannot find gps lna pin ol state!\n");
		return -4;
	}

	switch (state) {
	case PIN_STA_INIT:
	case PIN_STA_DEINIT:
		pinctrl_select_state(consys_pinctrl, gps_lna_init);
		WMT_PLAT_INFO_FUNC("set gps lna to init\n");
		break;
	case PIN_STA_OUT_H:
		pinctrl_select_state(consys_pinctrl, gps_lna_oh);
		WMT_PLAT_INFO_FUNC("set gps lna to oh\n");
		break;
	case PIN_STA_OUT_L:
		pinctrl_select_state(consys_pinctrl, gps_lna_ol);
		WMT_PLAT_INFO_FUNC("set gps lna to ol\n");
		break;

	default:
		WMT_PLAT_WARN_FUNC("%d mode not defined for  gps lna pin !!!\n", state);
		break;
	}
	return 0;
#else
#ifdef GPIO_GPS_LNA_PIN
	switch (state) {
	case PIN_STA_INIT:
	case PIN_STA_DEINIT:
		mt_set_gpio_pull_enable(GPIO_GPS_LNA_PIN, GPIO_PULL_DISABLE);
		mt_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
		mt_set_gpio_mode(GPIO_GPS_LNA_PIN, GPIO_GPS_LNA_PIN_M_GPIO);
		mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
		break;
	case PIN_STA_OUT_H:
		mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
		break;
	case PIN_STA_OUT_L:
		mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
		break;

	default:
		WMT_PLAT_WARN_FUNC("%d mode not defined for  gps lna pin !!!\n", state);
		break;
	}
	return 0;
#else
	WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
	    return 0;
#endif
#endif /* !defined(CONFIG_MTK_GPIO_LEGACY) */
}
INT32
wmt_plat_eirq_ctrl (
    ENUM_PIN_ID id,
    ENUM_PIN_STATE state
    )
{
    INT32 iret;

    // TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls

    if ( (PIN_STA_INIT != state )
        && (PIN_STA_DEINIT != state )
        && (PIN_STA_EINT_EN != state )
        && (PIN_STA_EINT_DIS != state ) ) {
        WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
        return -1;
    }

    iret = -2;
    switch (id) {
    case PIN_BGF_EINT:
#if 1
    if (PIN_STA_INIT == state) {
		iret = request_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,
			(irq_handler_t)wmt_plat_bgf_irq_isr,
			IRQF_TRIGGER_LOW,
			"BTIF_WAKEUP_IRQ",
			NULL);
		if(iret)
		{
			WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n",MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,iret);
			return iret;
		}
		gbgfIrqBle.counter = 1;
    }
    else if (PIN_STA_EINT_EN == state) {

		spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
		if(gbgfIrqBle.counter)
		{
			WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n",gbgfIrqBle.counter);;
		}
		else
		{
        	enable_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
			gbgfIrqBle.counter++;
		}
        WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en) \n");
		spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
    }
    else if (PIN_STA_EINT_DIS == state) {

		spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
		if(!gbgfIrqBle.counter)
		{
			WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n",gbgfIrqBle.counter);;
		}
		else
		{
        	disable_irq_nosync(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
			gbgfIrqBle.counter--;
		}
        WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis) \n");
		spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
    }
    else {
        free_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,NULL);
        /* de-init: nothing to do in ALPS, such as un-registration... */
    }
#else
        WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n", state);
#endif

        iret = 0;
        break;

    default:
        WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
        iret = -1;
        break;
    }

    return iret;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
	UINT32 retry = 10;
	UINT32 consysHwChipId = 0;

#if PWR_ON_OFF_API_AVALIABLE
	INT32 iRet = -1;
#endif
	WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
	WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));

	if(on)
	{
#if CONSYS_PMIC_CTRL_ENABLE
		if(mtk_wcn_regulator_get()){
			WMT_PLAT_ERR_FUNC("regulator_get fail\n");
			return -1;
		}
		/*need PMIC driver provide new API protocol */
	    /*1.AP power on MT6350 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8	0x0510[1] "1'b0   0x0512[14]"	1'b1"*/
		pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
		if(reg_V18){
			regulator_enable(reg_V18);
			WMT_PLAT_INFO_FUNC("wmt_dev enable VCN_1V8\n");
		}
		udelay(300);
		
		if(co_clock_en)
		{
			/*if co-clock mode:*/
			/*2.set RF XO BUF source from CellularRF  DA_XOBUF_SEL	0x1000513C[7:6]	2'b10*/
			CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) & ~(0x1 << 6) );
			CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | (0x1 << 7) );
			WMT_PLAT_INFO_FUNC("co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
		}
		else
		{
			/*if NOT co-clock:*/
			/*2.1 switch VCN28 to HW control mode (with PMIC_WRAP API) RG_VCN28_ON_CTRL 0x041C[14]  1'b1*/
			pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
			/*2.2 turn on VCN28 LDO (with PMIC_WRAP API) DA_XOBUF_SEL  0x1000513C[7:6]"	"  2'b11"*/
			CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | ((0x1 << 7) |(0x1 << 6)));
			WMT_PLAT_INFO_FUNC("NOT co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
			udelay(300);
		}
#endif
		/*3.assert CONNSYS CPU SW reset		0x10007018	"[12]=1'b1 [31:24]=8'h88 (key)"*/
		CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET), CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
		/*turn on top clock gating enable	TOP_CLKCG_CLR	0x10000084[26]	1'b1	*/
//		CONSYS_REG_WRITE((conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET), CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET) | CONSYS_TOP_CLKCG_BIT);
		/*turn on SPM clock gating enable PWRON_CONFG_EN	0x10006000	32'h0b160001 */
		CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);		

#if PWR_ON_OFF_API_AVALIABLE
		iRet = conn_power_on(); //consult clkmgr owner. 
		if(iRet)
		{
			WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
		}else
		{
			WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
		}

#else
		/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr)	conn_spm_pwr_on 0x10006280 [2]	1'b1		*/			
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_BIT);
		/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr)	pwr_conn_ack	0x1000660C [1]			*/		
		while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)));
		/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr)	sram_conn_pd	0x10006280 [3]	1'b1	*/		
		//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SRAM_CONN_PD_BIT);
		/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr)	conn_spm_pwr_on_s	0x10006280 [3]	1'b1	*/					
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_S_BIT);
		/*6.write conn_clk_dis=0, enable connsys clock	(MT6572 with the same addr) conn_clk_dis	0x10006280 [4]	1'b0				*/		
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_CLK_CTRL_BIT);
		/*7.wait 1us	*/	
		udelay(1);
		/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr)	pwr_conn_ack_s	0x10006610 [1]	*/						
		while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)));
		/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso	0x10006280 [1]	1'b0		*/				
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_ISO_S_BIT);
		/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b	0x10006280[0]	1'b1	*/					
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_RST_BIT);
		/*Disable AXI bus protect 0x10001220[8]  0x10001220[9]  1'b0 1'b0*/
		CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) & ~CONSYS_PROT_MASK);
       // while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) {
       // }

#endif
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
		WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
		/*11.26M is ready now, delay 10us for mem_pd de-assert*/
		udelay(10);
		/*enable AP bus clock : connmcu_bus_pd  API: enable_clock() ++??*/
		
		/*12.poll CONNSYS CHIP ID until 6580 is returned		0x18070008	32'h6580 */
		while (retry-- > 0)
		{
			consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
			if(consysHwChipId == 0x6580) {
				WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
				break;
			} else {
				WMT_PLAT_INFO_FUNC("Read CONSYS chipId(0x%08x)",consysHwChipId); 
			}
			msleep(20);
		}

		/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed		0x18070114	"[3:0] ROM DELSEL  [7:4] RAM4Kx32 DELSEL"  ??*/
		
		/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1")	ACR	0x18070110[18]	1'b1*/
		/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
		/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
		CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET, CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) | CONSYS_MCU_CFG_ACR_MBIST_BIT);

		/*"update ANA_WBG(AFE) CR. AFE setting file:  MT6752_AFE_SW_patch_REG_xxxx.xlsx"		AP Offset = 0x180B2000"		AP Offset = 0x180B2000*/

#if 0
		/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
		update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
		CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
		/*16.deassert CONNSYS CPU SW reset (need to check MT6752)		0x10007018	"[12]=1'b0 [31:24]=8'h88 (key)"*/
		CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
			(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);

		msleep(5);

	}else{

#if PWR_ON_OFF_API_AVALIABLE
		WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
		/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off()	*/
		iRet = conn_power_off();//consult clkmgr owner
		WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
		if(iRet)
		{
			WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
		}else
		{
			WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
		}
#else
		{	
			INT32 count = 0;
			CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) | CONSYS_PROT_MASK);
			//while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
			//	count++;
			//	if(count>1000)	
			//		break;	
			//}
		}
		/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 	0x10006280 [1]	1'b1	*/
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ISO_S_BIT);

		/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr)		0x10006280[0]	1'b0		*/		
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_RST_BIT);

		/*write conn_clk_dis=1, disable connsys clock  (MT6572 with the same addr)	conn_clk_dis	0x10006280 [4]	1'b1 	*/
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |CONSYS_CLK_CTRL_BIT);

		/*DA_WBG_EN_XBUF=0		*/										
		/*wait 1us	*/
		udelay(1);
		/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr)		0x10006280 [8]	1'b0	  */	
		//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SRAM_CONN_PD_BIT);
		/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr)		0x10006280 [3:2]	2'b00 */	
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));


#endif

#if CONSYS_PMIC_CTRL_ENABLE

		/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
		//mt6325_upmu_set_rg_vcn28_on_ctrl(0);
		/*turn off VCN28 LDO (with PMIC_WRAP API)"	 2. RG_VCN28_EN"  0x041C[12]" 1'b0*/
		//hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");

		/*AP power off MT6323 VCN_1V8 LDO (with PMIC_WRAP API) RG_VCN18_ON_CTRL "0x0510[1] 	"1'b0   RG_VCN18_EN"	0x0512[14]" 1'b0"*/
		pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
		if(reg_V18){
			regulator_disable(reg_V18);
			WMT_PLAT_INFO_FUNC("wmt_dev disable VCN_1V8\n");
		}

#endif

	}
	WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
	return 0;
}
static INT32 mtk_wcn_consys_jtag_set_for_mcu(VOID)
{
#if 0
	int iRet = -1;

	WMT_PLAT_INFO_FUNC("WCN jtag_set_for_mcu start...\n");
	jtag_addr1 = ioremap(JTAG_ADDR1_BASE, 0x5000);
	if (jtag_addr1 == 0) {
		WMT_PLAT_ERR_FUNC("remap jtag_addr1 fail!\n");
		return iRet;
	}
	WMT_PLAT_INFO_FUNC("jtag_addr1 = 0x%p\n", jtag_addr1);

	JTAG1_REG_WRITE(0x100053c4, 0x11111100);
	JTAG1_REG_WRITE(0x100053d4, 0x00111111);

	/*Enable IES of all pins */
	JTAG1_REG_WRITE(0x10002014, 0x00000003);
	JTAG1_REG_WRITE(0x10005334, 0x55000000);
	JTAG1_REG_WRITE(0x10005344, 0x00555555);
	JTAG1_REG_WRITE(0x10005008, 0xc0000000);
	JTAG1_REG_WRITE(0x10005018, 0x0000000d);
	JTAG1_REG_WRITE(0x10005014, 0x00000032);
	JTAG1_REG_WRITE(0x100020a4, 0x000000ff);
	JTAG1_REG_WRITE(0x100020d4, 0x000000b4);
	JTAG1_REG_WRITE(0x100020d8, 0x0000004b);

	WMT_PLAT_INFO_FUNC("WCN jtag set for mcu start...\n");
	kal_int32 iRet = 0;
	kal_uint32 tmp = 0;
	kal_int32 addr = 0;
	kal_int32 remap_addr1 = 0;
	kal_int32 remap_addr2 = 0;

	remap_addr1 = ioremap(JTAG_ADDR1_BASE, 0x1000);
	if (remap_addr1 == 0) {
		WMT_PLAT_ERR_FUNC("remap jtag_addr1 fail!\n");
		return -1;
	}

	remap_addr2 = ioremap(JTAG_ADDR2_BASE, 0x100);
	if (remap_addr2 == 0) {
		WMT_PLAT_ERR_FUNC("remap jtag_addr2 fail!\n");
		return -1;
	}

	/*Pinmux setting for MT6625 I/F */
	addr = remap_addr1 + 0x03C0;
	tmp = DRV_Reg32(addr);
	tmp = tmp & 0xff;
	tmp = tmp | 0x11111100;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	addr = remap_addr1 + 0x03D0;
	tmp = DRV_Reg32(addr);
	tmp = tmp & 0xff000000;
	tmp = tmp | 0x00111111;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/*AP GPIO Setting 1 <default use> */
	/*Enable IES */
	/* addr = 0x10002014; */
	addr = remap_addr2 + 0x0014;
	tmp = 0x00000003;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));
	/*GPIO mode setting */
	/* addr = 0x10005334; */
	addr = remap_addr1 + 0x0334;
	tmp = 0x55000000;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/* addr = 0x10005344; */
	addr = remap_addr1 + 0x0344;
	tmp = 0x00555555;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));
	/*GPIO direction control */
	/* addr = 0x10005008; */
	addr = remap_addr1 + 0x0008;
	tmp = 0xc0000000;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/* addr = 0x10005018; */
	addr = remap_addr1 + 0x0018;
	tmp = 0x0000000d;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/* addr = 0x10005014; */
	addr = remap_addr1 + 0x0014;
	tmp = 0x00000032;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/*PULL Enable */
	/* addr = 0x100020a4; */
	addr = remap_addr2 + 0x00a4;
	tmp = 0x000000ff;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/*PULL select enable */
	/* addr = 0x100020d4; */
	addr = remap_addr2 + 0x00d4;
	tmp = 0x000000b4;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));

	/* addr = 0x100020d8; */
	addr = remap_addr2 + 0x00d8;
	tmp = 0x0000004b;
	DRV_WriteReg32(addr, tmp);
	WMT_PLAT_INFO_FUNC("(RegAddr, RegVal):(0x%08x, 0x%08x)", addr, DRV_Reg32(addr));
#endif

	return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
	INT32 iRet = -1;
	UINT32 retry = 10;
	UINT32 consysHwChipId = 0;

	WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);

	if (on) {
		WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
		/*need PMIC driver provide new API protocol */
		/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8  */
		pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
		/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
		if (reg_VCN18) {
			regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
			if (regulator_enable(reg_VCN18))
				WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
			else
				WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
		}
#endif
		udelay(150);

		if (co_clock_type) {
			/*step0,clk buf ctrl */
			WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
			clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
			/*if co-clock mode: */
			/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
			/*turn on VCN28 LDO only when FMSYS is activated"  */
			pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
		} else {
			/*if NOT co-clock: */
			/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
			pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
			/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
			/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
			hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
			if (reg_VCN28) {
				regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
				if (regulator_enable(reg_VCN28))
					WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
				else
					WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
			}
#endif
		}
#endif

/*step2.MTCMOS ctrl*/

#ifdef CONFIG_OF		/*use DT */
		/*3.assert CONNSYS CPU SW reset  0x10007018 "[12]=1'b1  [31:24]=8'h88 (key)" */
		CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
				 CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
				 CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
		/*turn on SPM clock gating enable PWRON_CONFG_EN  0x10006000  32'h0b160001 */
		CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);

#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
		iRet = conn_power_on();	/* consult clkmgr owner. */
		if (iRet)
			WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
		iRet = clk_prepare_enable(clk_scp_conn_main);
		if (iRet)
			WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
		/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2]  1'b1 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
				 CONSYS_SPM_PWR_ON_BIT);
		/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
		while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
			NULL;
		/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3]  1'b1 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
				 CONSYS_SPM_PWR_ON_S_BIT);
		/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4]  1'b0 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
				 ~CONSYS_CLK_CTRL_BIT);
		/*7.wait 1us    */
		udelay(1);
		/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
		while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
			CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
			NULL;
		/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1]  1'b0 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
				 ~CONSYS_SPM_PWR_ISO_S_BIT);
		/*10.release SW reset of connsys, conn_ap_sw_rst_b=1  0x10006280[0]   1'b1 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
				 CONSYS_SPM_PWR_RST_BIT);
		/*disable AXI BUS protect */
		CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
				 CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
				 ~CONSYS_PROT_MASK);
		while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
			NULL;
#endif
		/*11.26M is ready now, delay 10us for mem_pd de-assert */
		udelay(10);
		/*enable AP bus clock : connmcu_bus_pd  API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
		enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
		WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
		iRet = clk_prepare_enable(clk_infra_conn_main);
		if (iRet)
			WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
		/*12.poll CONNSYS CHIP ID until chipid is returned  0x18070008 */
		while (retry-- > 0) {
			consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
			if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
				WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
				break;
			}
			WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
			msleep(20);
		}

		if ((0 == retry) || (0 == consysHwChipId)) {
			WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
			WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
				  CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
			WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
				   CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
			WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
				   CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
			WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
				   CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
		}

		/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */

		/*
		 *14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
		 *(default write "1") ACR 0x18070110[18] 1'b1
		 *if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
		 *if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
		 *inclulding low CPU frequence
		 */
		CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
				 CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
				 CONSYS_MCU_CFG_ACR_MBIST_BIT);

#if 0
		/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
		CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
		/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
		CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
				 (CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
				 ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);

#else /*use HADRCODE, maybe no use.. */
		/*3.assert CONNSYS CPU SW reset  0x10007018  "[12]=1'b1  [31:24]=8'h88 (key)" */
		CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
				 (CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
				  CONSYS_CPU_SW_RST_CTRL_KEY));
		/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
		CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);

#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
		iRet = conn_power_on();	/* consult clkmgr owner */
		if (iRet)
			WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
		iRet = clk_prepare_enable(clk_scp_conn_main);
		if (iRet)
			WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
		/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2]  1'b1 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
		/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
		while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
			NULL;
		/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3]  1'b1 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
		/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4]  1'b0 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
		/*7.wait 1us    */
		udelay(1);
		/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1]  */
		while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
			NULL;
		/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1]  1'b0 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
		/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
		/*disable AXI BUS protect */
		CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
		while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
			NULL;
#endif
		/*11.26M is ready now, delay 10us for mem_pd de-assert */
		udelay(10);
		/*enable AP bus clock : connmcu_bus_pd  API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
		enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
		WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
		iRet = clk_prepare_enable(clk_infra_conn_main);
		if (iRet)
			WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
		/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
		while (retry-- > 0) {
			WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
			consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
			if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
				WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
				break;
			}
			msleep(20);
		}

		if ((0 == retry) || (0 == consysHwChipId)) {
			WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
			WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
					   CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
			WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
					   CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
			WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
					   CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
			WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
					   CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
		}

		/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114  */

		/*
		 *14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
		 *(default write "1") ACR 0x18070110[18] 1'b1
		 *if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
		 *if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
		 *inclulding low CPU frequence
		 */
		CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
				 CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);

		/*update ANA_WBG(AFE) CR. AFE setting file:  AP Offset = 0x180B2000   */

#if 0
		/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
		CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
		CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
		/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
		CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
				 (CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
				 CONSYS_CPU_SW_RST_CTRL_KEY);

#endif
		msleep(20);	/* msleep < 20ms can sleep for up to 20ms */

	} else {

#ifdef CONFIG_OF

#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
		disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
		clk_disable_unprepare(clk_infra_conn_main);
		WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif

#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
		/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
		iRet = conn_power_off();	/* consult clkmgr owner */
		if (iRet)
			WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
		clk_disable_unprepare(clk_scp_conn_main);
		WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
		{
			INT32 count = 0;

			CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
					 CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
					 CONSYS_PROT_MASK);
			while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
				CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
				count++;
				if (count > 1000)
					break;
			}
		}
		/*release connsys ISO, conn_top1_iso_en=1  0x10006280 [1]  1'b1 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
				 CONSYS_SPM_PWR_ISO_S_BIT);
		/*assert SW reset of connsys, conn_ap_sw_rst_b=0  0x10006280[0] 1'b0 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
				 ~CONSYS_SPM_PWR_RST_BIT);
		/*write conn_clk_dis=1, disable connsys clock  0x10006280 [4]  1'b1 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
				 CONSYS_CLK_CTRL_BIT);
		/*wait 1us      */
		udelay(1);
		/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
		CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
				 CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
				 ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));

#endif

#else

#if CONSYS_PWR_ON_OFF_API_AVAILABLE

#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
		disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
		clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif

#if defined(CONFIG_MTK_CLKMGR)
		/*power off connsys by API: conn_power_off() */
		iRet = conn_power_off();	/* consult clkmgr owner */
		if (iRet)
			WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
		WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
		clk_disable_unprepare(clk_scp_conn_main);
		WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
		{
			INT32 count = 0;

			CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
					 CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
			while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
				count++;
				if (count > 1000)
					break;
			}

		}
		/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1]  1'b1 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
		/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0  */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
		/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4]  1'b1 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
				 CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
		/*wait 1us      */
		udelay(1);
		/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
		CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
		~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif

#endif

#if CONSYS_PMIC_CTRL_ENABLE
		if (co_clock_type) {
			/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
			clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
		} else {
			pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
			/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
			hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
			if (reg_VCN28) {
				if (regulator_disable(reg_VCN28))
					WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
				else
					WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
			}
#endif
		}

		/*AP power off MT6625L VCN_1V8 LDO */
		pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
		hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
		if (reg_VCN18) {
			if (regulator_disable(reg_VCN18))
				WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
			else
				WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
		}
#endif

#endif

	}
	WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
	return 0;
}