void WriteIndexedRegister (byte PageNum, byte Offset, byte Data) { EXIT_ON_CABLE_DISCONNECTION_V; WriteByteTPI(TPI_INDEXED_PAGE_REG, PageNum); // Indexed page WriteByteTPI(TPI_INDEXED_OFFSET_REG, Offset); // Indexed register WriteByteTPI(TPI_INDEXED_VALUE_REG, Data); // Write value }
byte ReadIndexedRegister (byte PageNum, byte Offset) { EXIT_ON_CABLE_DISCONNECTION; WriteByteTPI(TPI_INDEXED_PAGE_REG, PageNum); // Indexed page WriteByteTPI(TPI_INDEXED_OFFSET_REG, Offset); // Indexed register return ReadByteTPI(TPI_INDEXED_VALUE_REG); // Return read value }
void tpi_clear_pending_event(void) { int retry = 100; while (retry--) { WriteByteTPI(0x3c, 1); WriteByteTPI(0x3d, 1); if (ReadByteTPI(0x3d) & 0x01) DelayMS(1); else break; } if (retry < 19) TPI_DEBUG_PRINT(("%s: retry=%d\n", __func__, 19 - retry)); }
static void OnMHDCableConnected(void) { TPI_DEBUG_PRINT(("[SIMG] MHD Connected\n")); if (txPowerState == TX_POWER_STATE_D3) { /* start tpi */ WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to start HW TPI mode */ /* enable interrupts */ WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01); TxPowerStateD0(); } mobileHdCableConnected = TRUE; WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); TPI_DEBUG_PRINT(("[SIMG] Setting DDC Burst Mode\n")); /* Increase DDC translation layer timer (burst mode) */ WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); WriteByteCBUS(0x47, 0x03); WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */ }
static void InitForceUsbIdSwitchOpen (void) { I2C_WriteByte(0x72, 0x90, 0x26); // Disable CBUS discovery ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open WriteByteTPI(0x92, 0x46); // Force MHD mode }
static bool StartTPI(void) { WriteByteTPI(TPI_ENABLE, 0x00); DelayMS(100); bInTpiMode = true; return true; }
static void WriteInitialRegisterValues(void) { I2C_WriteByte(TPI_SLAVE_ADDR, 0x08, 0x37); I2C_WriteByte(TPI_SLAVE_ADDR, 0xA0, 0xD0); I2C_WriteByte(TPI_SLAVE_ADDR, 0xA1, 0xFC); I2C_WriteByte(TPI_SLAVE_ADDR, 0xA3, 0xC0); I2C_WriteByte(TPI_SLAVE_ADDR, 0xA6, 0x0C); I2C_WriteByte(TPI_SLAVE_ADDR, 0x2B, 0x01); ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_2); I2C_WriteByte(TPI_SLAVE_ADDR, 0x91, 0xA5); I2C_WriteByte(TPI_SLAVE_ADDR, 0x94, 0x75); I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); I2C_WriteByte(TPI_SLAVE_ADDR, 0xA5, 0xA0); TPI_DEBUG_PRINT(("1x Mode\n")); I2C_WriteByte(TPI_SLAVE_ADDR, 0x95, 0x31); I2C_WriteByte(TPI_SLAVE_ADDR, 0x96, 0x20); ReadModifyWriteTPI(0x97, BIT_1, 0); ReadModifyWriteTPI(0x95, BIT_6, BIT_6); WriteByteTPI(0x92, 0x86); WriteByteTPI(0x93, 0xCC); if (txPowerState != TX_POWER_STATE_D3) { ReadModifyWriteTPI(0x79, BIT_5 | BIT_4, BIT_4); } DelayMS(25); ReadModifyWriteTPI(0x95, BIT_6, 0x00); ReadModifyWriteTPI(0x78, BIT_5, 0); I2C_WriteByte(TPI_SLAVE_ADDR, 0x90, 0x27); I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x08); DelayMS(2); I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x00); InitCBusRegs(); I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, ASR_VALUE); }
void ReadModifyWriteIndexedRegister (u8 PageNum, u8 Offset, u8 Mask, u8 Data) { u8 Temp; Temp = ReadIndexedRegister (PageNum, Offset); // Read the current value of the register. Temp &= ~Mask; // Clear the bits that are set in Mask. Temp |= (Data & Mask); // OR in new value. Apply Mask to Value for safety. WriteByteTPI(TPI_INDEXED_VALUE_REG, Temp); // Write new value back to register. }
void ReadModifyWriteTPI(u8 Offset, u8 Mask, u8 Data) { u8 Temp; Temp = ReadByteTPI(Offset); // Read the current value of the register. Temp &= ~Mask; // Clear the bits that are set in Mask. Temp |= (Data & Mask); // OR in new value. Apply Mask to Value for safety. WriteByteTPI(Offset, Temp); // Write new value back to register. }
void MHD_INT_clear(void) { byte Int_state; Int_state= ReadByteTPI(TPI_INTERRUPT_STATUS_REG); WriteByteTPI (TPI_INTERRUPT_STATUS_REG, Int_state); // Clear this interrupt. }
void ReadModifyWriteIndexedRegister (byte PageNum, byte Offset, byte Mask, byte Data) { byte Temp; EXIT_ON_CABLE_DISCONNECTION_V; Temp = ReadIndexedRegister (PageNum, Offset); // Read the current value of the register. Temp &= ~Mask; // Clear the bits that are set in Mask. Temp |= (Data & Mask); // OR in new value. Apply Mask to Value for safety. WriteByteTPI(TPI_INDEXED_VALUE_REG, Temp); // Write new value back to register. }
void ReadModifyWriteTPI(byte Offset, byte Mask, byte Data) { byte Temp; EXIT_ON_CABLE_DISCONNECTION_V; Temp = ReadByteTPI(Offset); // Read the current value of the register. Temp &= ~Mask; // Clear the bits that are set in Mask. Temp |= (Data & Mask); // OR in new value. Apply Mask to Value for safety. WriteByteTPI(Offset, Temp); // Write new value back to register. }
void MHD_INT_clear(void) { byte Int_state; #if 0 Int_state= ReadByteTPI(TPI_INTERRUPT_STATUS_REG); WriteByteTPI (TPI_INTERRUPT_STATUS_REG, Int_state); // Clear this interrupt. WriteByteTPI(TPI_INTERRUPT_ENABLE_REG, 0x00); WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01); // Enable #endif Int_state = ReadIndexedRegister(INDEXED_PAGE_0,0x74); WriteIndexedRegister(INDEXED_PAGE_0,0x74,Int_state); }
static void ReadModifyWriteIndexedRegister(byte PageNum, byte Offset, byte Mask, byte Data) { byte Temp; /* Read the current value of the register. */ Temp = ReadIndexedRegister(PageNum, Offset); /* Clear the bits that are set in Mask. */ Temp &= ~Mask; /* OR in new value. Apply Mask to Value for safety. */ Temp |= (Data & Mask); /* Write new value back to register. */ WriteByteTPI(TPI_INDEXED_VALUE_REG, Temp); }
void ReadModifyWriteTPI(byte Offset, byte Mask, byte Data) { byte Temp; Temp = ReadByteTPI(Offset); /* Read the current value of the register.*/ Temp &= ~Mask; /*Clear the bits that are set in Mask.*/ Temp |= (Data & Mask); /*OR in new value. Apply Mask to Value for safety.*/ WriteByteTPI(Offset, Temp); /*Write new value back to register.*/ }
void sii9234_tpi_init(void) { MHD_HW_Reset(); //sii9234_initial_registers_set(); //previous setting printk("[HDMI]9234 init ++ \n"); #if 0 /* disable interrupts */ ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, RECEIVER_SENSE_EVENT_MASK, 0x00); //MHD_INT_clear(); #endif sii9234_register_init(); /* start tpi */ WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to start HW TPI mode */ /* enable interrupts */ WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01); /* mhd rx connected */ WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); /* TX termination enable */ WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); /* Increase DDC translation layer timer (burst mode) */ WriteByteCBUS(0x47, 0x03); WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */ /* enable mhd tx */ ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); /* set mhd power active mode */ ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG, TX_POWER_STATE_MASK, 0x00); mhd_tx_fifo_stable(); //fifo clear printk("[HDMI]9234 init -- \n"); }
void sii9234_tpi_init(void) { MHD_HW_Reset(); pr_info("[HDMI]9234 init ++\n"); sii9234_register_init(); /* start tpi */ WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to start HW TPI mode */ /* enable interrupts */ WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01); /* mhd rx connected */ WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); /* TX termination enable */ WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); /* Increase DDC translation layer timer (burst mode) */ WriteByteCBUS(0x47, 0x03); WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */ /* enable mhd tx */ ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); /* set mhd power active mode */ ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG, TX_POWER_STATE_MASK, 0x00); mhd_tx_fifo_stable(); /*fifo clear*/ #ifdef CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE mhl_hpd_handler(true); #endif pr_info("[HDMI]9234 init --\n"); }
void sii9234_register_init(void) { // Power Up I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core I2C_WriteByte(0x92, 0x00, 0x00); // SIMG: correcting HW default I2C_WriteByte(0x92, 0x13, 0x60); // SIMG: Set termination value I2C_WriteByte(0x92, 0x14, 0xF0); // SIMG: Change CKDT level I2C_WriteByte(0x92, 0x4B, 0x06); // SIMG: Correcting HW default // Analog PLL Control I2C_WriteByte(0x92, 0x17, 0x07); // SIMG: PLL Calrefsel I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal I2C_WriteByte(0x92, 0x22, 0xE0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x23, 0xC0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x24, 0xA0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x25, 0x80); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x26, 0x60); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x27, 0x40); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x28, 0x20); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x29, 0x00); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x4D, 0x02); // SIMG: PLL Mode Value (order is important) I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value I2C_WriteByte(0x92, 0x31, 0x0B); // SIMG: Rx PLL BW value from I2C BW ~ 4MHz I2C_WriteByte(0x92, 0x45, 0x06); // SIMG: DPLL Mode I2C_WriteByte(0x72, 0xA0, 0xD0); // SIMG: Term mode I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver I2C_WriteByte(0x72, 0xA3, 0xF9); // SIMG: Output Swing default EB I2C_WriteByte(0x72, 0xA6, 0x0C); // SIMG: Swing Offset I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround // CBUS & Discovery ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3); // CBUS discovery cycle time for each drive and float = 150us I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold //set bit 2 and 3, which is Initiator Timeout I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); // original 3x config I2C_WriteByte(0x72, 0xA5, 0x80); // SIMG: RGND Hysterisis, 3x mode for Beast I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking) I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open WriteByteTPI(0x92, 0x46); // Force MHD mode WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0); //daniel test...MHL_INT delay_ms(25); ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery InitCBusRegs(); I2C_WriteByte(0x72, 0x05, ASR_VALUE); // Enable Auto soft reset on SCDT = 0 I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable }
void sii9234_start_tpi(void) { WriteByteTPI(TPI_ENABLE, 0x00); // Write "0" to 72:C7 to start HW TPI mode }
void sii9234_initial_registers_set(void) { pr_info("==[SIMG] sii9234_initial_registers_set Start ==\n"); /* Power Up */ I2C_WriteByte(0x7A, 0x3D, 0x3F); /* Power up CVCC 1.2V core */ I2C_WriteByte(0x92, 0x11, 0x01); /* Enable TxPLL Clock */ I2C_WriteByte(0x92, 0x12, 0x15); /* Enable Tx Clock Path & Equalizer */ I2C_WriteByte(0x72, 0x08, 0x35); /* Power Up TMDS Tx Core */ I2C_WriteByte(0x92, 0x00, 0x00); /* SIMG: correcting HW default */ I2C_WriteByte(0x92, 0x13, 0x60); /* SIMG: Set termination value */ I2C_WriteByte(0x92, 0x14, 0xF0); /* SIMG: Change CKDT level */ I2C_WriteByte(0x92, 0x4B, 0x06); /* SIMG: Correcting HW default */ /* Analog PLL Control */ I2C_WriteByte(0x92, 0x17, 0x07); /* SIMG: PLL Calrefsel */ I2C_WriteByte(0x92, 0x1A, 0x20); /* VCO Cal */ I2C_WriteByte(0x92, 0x22, 0xE0); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x23, 0xC0); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x24, 0xA0); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x25, 0x80); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x26, 0x60); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x27, 0x40); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x28, 0x20); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x29, 0x00); /* SIMG: Auto EQ */ I2C_WriteByte(0x92, 0x4D, 0x02); /* SIMG: PLL Mode Value (order is important) */ I2C_WriteByte(0x92, 0x4C, 0xA0); /* Manual zone control */ I2C_WriteByte(0x72, 0x80, 0x14); /* Enable Rx PLL Clock Value */ I2C_WriteByte(0x92, 0x31, 0x0B); /* SIMG: Rx PLL BW value from I2C BW ~ 4MHz */ I2C_WriteByte(0x92, 0x45, 0x06); /* SIMG: DPLL Mode */ I2C_WriteByte(0x72, 0xA0, 0x10); /* SIMG: Term mode */ I2C_WriteByte(0x72, 0xA1, 0xFC); /* Disable internal Mobile HD driver */ I2C_WriteByte(0x72, 0xA3, 0xEB); /* SIMG: Output Swing */ I2C_WriteByte(0x72, 0xA6, 0x0C); /* SIMG: Swing Offset */ I2C_WriteByte(0x72, 0x2B, 0x01); /* Enable HDCP Compliance workaround */ // CBUS & Discovery #if 0 ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); /* CBUS discovery cycle time for each drive and float = 150us */ #endif I2C_WriteByte(0x72, 0x91, 0xE5); /* Skip RGND detection */ I2C_WriteByte(0x72, 0x94, 0x66); /* 1.8V CBUS VTH & GND threshold */ #if 0 /* set bit 2 and 3, which is Initiator Timeout */ I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); #endif I2C_WriteByte(0x72, 0xA5, 0x80); /* SIMG: RGND Hysterisis, 3x mode for Beast */ I2C_WriteByte(0x72, 0x95, 0x31); /* RGND & single discovery attempt (RGND blocking) */ I2C_WriteByte(0x72, 0x96, 0x22); /* use 1K and 2K setting */ ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); /* Force USB ID switch open */ #if 0 WriteByteTPI(0x92, 0x46); /* Force MHD mode */ WriteByteTPI(0x93, 0xDC); /* Disable CBUS pull-up during RGND measurement */ #else /*old cable */ WriteByteTPI(0x92, 0x86); /* Force MHD mode */ WriteByteTPI(0x93, 0xCC); /* Disable CBUS pull-up during RGND measurement */ #endif mdelay(25); ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); /* Release USB ID switch */ I2C_WriteByte(0x72, 0x90, 0x27); /* Enable CBUS discovery */ I2C_WriteByte(0x72, 0x05, 0x04); /* Enable Auto soft reset on SCDT = 0 */ I2C_WriteByte(0x72, 0x0D, 0x1C); /* HDMI Transcode mode enable */ WriteByteTPI(TPI_ENABLE, 0x00); mdelay(100); WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); /* Increase DDC translation layer timer (burst mode) */ WriteByteCBUS(0x47, 0x03); WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */ mdelay(100); ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); printk ("==[SIMG] sii9234_initial_registers_set END ==\n"); }
void sii9234_initial_registers_set(void) { printk ("==[SIMG] sii9234_initial_registers_set Start ==\n"); #if 0 //old cable // Power Up I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core // Analog PLL Control I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver I2C_WriteByte(0x72, 0xA3, 0xFF); //AMP I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis. I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery //I2C_WriteByte(0x72, 0x05, ASR_VALUE); // Enable Auto soft reset on SCDT = 0 I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable WriteByteTPI(TPI_ENABLE, 0x00); delay_ms(100); WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); delay_ms(100); ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); #endif #if 0 //test pattern generate WriteByteTPI(0xBC, 0x81); I2C_WriteByte(0x72, 0xBD, 0x01); // Enable Auto soft reset on SCDT = 0 I2C_WriteByte(0x72, 0xBB, 0x1D); #endif #if 0 //new MHL cable // Power Up I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core //I2C_WriteByte(0x7A, 0x3D, 0x37); // Power up CVCC 1.2V core I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core //I2C_WriteByte(0x72, 0x08, 0x37); // Power Up TMDS Tx Core // Analog PLL Control I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control //I2C_WriteByte(0x92, 0x1C, 0x11); //daniel RX0_offset test //I2C_WriteByte(0x92, 0x1D, 0x11); //daniel RX1_offset test //I2C_WriteByte(0x92, 0x1E, 0x11); //daniel RX2_offset test I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value //I2C_WriteByte(0x72, 0x80, 0x24); // Enable Rx PLL Clock Value //I2C_WriteByte(0x72, 0x80, 0x34); // Enable Rx PLL Clock Value I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz I2C_WriteByte(0x72, 0xA0, 0xD0); I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver I2C_WriteByte(0x72, 0xA3, 0xFF); I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround // CBUS & Discovery //ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold //set bit 2 and 3, which is Initiator Timeout //I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis. I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking) I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open WriteByteTPI(0x92, 0x46); // Force MHD mode WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement //old cable //WriteByteTPI(0x92, 0x86); // Force MHD mode //WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement delay_ms(25); ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery //InitCBusRegs(); I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0 I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable WriteByteTPI(TPI_ENABLE, 0x00); delay_ms(100); WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); //WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode) //WriteByteCBUS(0x47, 0x03); //WriteByteCBUS(0x21, 0x01); // Heartbeat Disable delay_ms(100); ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); #endif #if 1 //0607 update // Power Up I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core I2C_WriteByte(0x92, 0x00, 0x00); // SIMG: correcting HW default I2C_WriteByte(0x92, 0x13, 0x60); // SIMG: Set termination value I2C_WriteByte(0x92, 0x14, 0xF0); // SIMG: Change CKDT level I2C_WriteByte(0x92, 0x4B, 0x06); // SIMG: Correcting HW default // Analog PLL Control I2C_WriteByte(0x92, 0x17, 0x07); // SIMG: PLL Calrefsel I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal I2C_WriteByte(0x92, 0x22, 0xE0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x23, 0xC0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x24, 0xA0); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x25, 0x80); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x26, 0x60); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x27, 0x40); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x28, 0x20); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x29, 0x00); // SIMG: Auto EQ I2C_WriteByte(0x92, 0x4D, 0x02); // SIMG: PLL Mode Value (order is important) I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value I2C_WriteByte(0x92, 0x31, 0x0B); // SIMG: Rx PLL BW value from I2C BW ~ 4MHz I2C_WriteByte(0x92, 0x45, 0x06); // SIMG: DPLL Mode I2C_WriteByte(0x72, 0xA0, 0x10); // SIMG: Term mode I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver I2C_WriteByte(0x72, 0xA3, 0xEB); // SIMG: Output Swing I2C_WriteByte(0x72, 0xA6, 0x0C); // SIMG: Swing Offset I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround // CBUS & Discovery //ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold //set bit 2 and 3, which is Initiator Timeout //I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); I2C_WriteByte(0x72, 0xA5, 0x80); // SIMG: RGND Hysterisis, 3x mode for Beast I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking) I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open //WriteByteTPI(0x92, 0x46); // Force MHD mode //WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement //old cable WriteByteTPI(0x92, 0x86); // Force MHD mode WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement delay_ms(25); ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery //InitCBusRegs(); I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0 I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable WriteByteTPI(TPI_ENABLE, 0x00); delay_ms(100); WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10); WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode) WriteByteCBUS(0x47, 0x03); WriteByteCBUS(0x21, 0x01); // Heartbeat Disable delay_ms(100); ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE); #endif printk ("==[SIMG] sii9234_initial_registers_set END ==\n"); }
void WriteIndexedRegister (byte PageNum, byte Offset, byte Data) { WriteByteTPI(TPI_INDEXED_PAGE_REG, PageNum); // Indexed page WriteByteTPI(TPI_INDEXED_OFFSET_REG, Offset); // Indexed register WriteByteTPI(TPI_INDEXED_VALUE_REG, Data); // Write value }
static void sii9234_register_init(void) { /*Power Up*/ I2C_WriteByte(0x7A, 0x3D, 0x3F); /* Power up CVCC 1.2V core */ I2C_WriteByte(0x92, 0x11, 0x01); /* Enable TxPLL Clock*/ I2C_WriteByte(0x92, 0x12, 0x15); /* Enable Tx Clock Path & Equalizer*/ I2C_WriteByte(0x72, 0x08, 0x35); /* Power Up TMDS Tx Core*/ I2C_WriteByte(0x92, 0x00, 0x00); /* SIMG: correcting HW default*/ I2C_WriteByte(0x92, 0x13, 0x60); /* SIMG: Set termination value*/ I2C_WriteByte(0x92, 0x14, 0xF0); /* SIMG: Change CKDT level*/ I2C_WriteByte(0x92, 0x4B, 0x06); /* SIMG: Correcting HW default*/ /*Analog PLL Control*/ I2C_WriteByte(0x92, 0x17, 0x07); /* SIMG: PLL Calrefsel*/ I2C_WriteByte(0x92, 0x1A, 0x20); /* VCO Cal*/ I2C_WriteByte(0x92, 0x22, 0xE0); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x23, 0xC0); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x24, 0xA0); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x25, 0x80); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x26, 0x60); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x27, 0x40); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x28, 0x20); /* SIMG: Auto EQ*/ I2C_WriteByte(0x92, 0x29, 0x00); /* SIMG: Auto EQ*/ /*I2C_WriteByte(0x92, 0x10, 0xF1);*/ I2C_WriteByte(0x92, 0x4D, 0x02); /* SIMG: PLL Mode Value (order is important)*/ /*I2C_WriteByte(0x92, 0x4D, 0x00);*/ I2C_WriteByte(0x92, 0x4C, 0xA0); /* Manual zone control*/ /*I2C_WriteByte(0x72, 0x80, 0x14);*/ /* Enable Rx PLL Clock Value*/ I2C_WriteByte(0x72, 0x80, 0x34); I2C_WriteByte(0x92, 0x31, 0x0B); /* SIMG: Rx PLL BW value from I2C BW ~ 4MHz*/ I2C_WriteByte(0x92, 0x45, 0x06); /* SIMG: DPLL Mode*/ I2C_WriteByte(0x72, 0xA0, 0xD0); /* SIMG: Term mode*/ I2C_WriteByte(0x72, 0xA1, 0xFC); /* Disable internal Mobile HD driver*/ I2C_WriteByte(0x72, 0xA3, 0xEB); /* SIMG: Output Swing default EB*/ I2C_WriteByte(0x72, 0xA6, 0x00); /* SIMG: Swing Offset*/ I2C_WriteByte(0x72, 0x2B, 0x01); /* Enable HDCP Compliance workaround*/ /*CBUS & Discovery*/ ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3);/* CBUS discovery cycle time for each drive and float = 150us*/ I2C_WriteByte(0x72, 0x91, 0xE5); /* Skip RGND detection*/ I2C_WriteByte(0x72, 0x94, 0x66); /* 1.8V CBUS VTH & GND threshold*/ /*set bit 2 and 3, which is Initiator Timeout*/ I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c); /*original 3x config*/ I2C_WriteByte(0x72, 0xA5, 0x80); /* SIMG: RGND Hysterisis, 3x mode for Beast*/ I2C_WriteByte(0x72, 0x95, 0x31); /* RGND & single discovery attempt (RGND blocking)*/ I2C_WriteByte(0x72, 0x96, 0x22); /* use 1K and 2K setting*/ ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); /* Force USB ID switch to open*/ WriteByteTPI(0x92, 0x46); /* Force MHD mode*/ WriteByteTPI(0x93, 0xDC); /* Disable CBUS pull-up during RGND measurement*/ ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0); /*daniel test...MHL_INT*/ mdelay(25); ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); /* Release USB ID switch*/ I2C_WriteByte(0x72, 0x90, 0x27); /* Enable CBUS discovery*/ InitCBusRegs(); I2C_WriteByte(0x72, 0x05, ASR_VALUE); /* Enable Auto soft reset on SCDT = 0*/ I2C_WriteByte(0x72, 0x0D, 0x1C); /* HDMI Transcode mode enable*/ }
static byte ReadIndexedRegister(byte PageNum, byte Offset) { WriteByteTPI(TPI_INDEXED_PAGE_REG, PageNum); /* Indexed page */ WriteByteTPI(TPI_INDEXED_OFFSET_REG, Offset); /* Indexed register */ return ReadByteTPI(TPI_INDEXED_VALUE_REG); /* Return read value */ }
u8 ReadIndexedRegister (u8 PageNum, u8 Offset) { WriteByteTPI(TPI_INDEXED_PAGE_REG, PageNum); // Indexed page WriteByteTPI(TPI_INDEXED_OFFSET_REG, Offset); // Indexed register return ReadByteTPI(TPI_INDEXED_VALUE_REG); // Return read value }
void startTPI(void) { WriteByteTPI(TPI_ENABLE, 0x00); // Write "0" to 72:C7 to start HW TPI mode mdelay(100); }
void tpi_clear_interrupt(uint8_t pattern) { WriteByteTPI(0x3D, pattern); }