/**
* @brief Set a PCLK mode.
* @param[in] mode Specifies a PCLK mode to change.
* @return None.
* @remark MPEGTSIF doesn't support NX_PCLKMODE_DYNAMIC. If you call this
* function with NX_PCLKMODE_DYNAMIC, it makes that PCLK doesn't
* provide to the MPEGTSIF module and MPEGTSIF module doesn't operate
* correctly. You have to set a PCLK mode as NX_PCLKMODE_ALWAYS
* to operate and control the MPEGTSIF module. But you can set a PCLK
* mode as NX_PCLKMODE_DYNAMIC to slightly reduce a power
* cunsumption if you don't want to use the MPEGTSIF module.\n
* \b IMPORTANT : \n
* Since changing a clock controller register of the MPEGTSIF module
* causes a reset of controller register of the MPEGTSIF module,
* you have to reconfigure all settings of the MPEGTSIF module
* after calling this function.
* @see NX_PCLKMODE, NX_MPEGTSIF_GetClockPClkMode,
*/
void NX_MPEGTSIF_SetClockPClkMode( NX_PCLKMODE mode )
{
const U32 PCLKMODE = 1UL<<3;
const U32 IRQPEND = 1UL<<15;
register U32 regvalue, regctrl;
NX_ASSERT( CNULL != __g_pRegister );
regctrl = __g_pRegister->CTRL; // back-up control register before changing CLKENB.
regvalue = __g_pRegister->CLKENB;
switch( mode )
{
case NX_PCLKMODE_DYNAMIC: regvalue &= ~PCLKMODE; break;
case NX_PCLKMODE_ALWAYS : regvalue |= PCLKMODE; break;
default: NX_ASSERT( CFALSE ); break;
}
// __g_pRegister->CLKENB = regvalue;
// __g_pRegister->CTRL = regctrl & ~IRQPEND; // restore control register after changing CLKENB.
WriteIODW(&__g_pRegister->CLKENB, regvalue);
WriteIODW(&__g_pRegister->CTRL, regctrl & ~IRQPEND); // restore control register after changing CLKENB.
}
/**
* @brief Set all interrupts to be enabled or disabled.
* @param[in] 0 an index of module.
* @param[in] Enable \b Set as CTRUE to enable all interrupts. \r\n
* \b Set as CFALSE to disable all interrupts.
* @return None.
*/
void NX_USB20OTG_SetInterruptEnableAll( CBOOL Enable )
{
register NX_USB20OTG_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_USB20OTG_MODULE > 0 );
NX_ASSERT( (0==Enable) || (1==Enable) );
NX_ASSERT( CNULL != __g_pRegister[0] );
pRegister = __g_pRegister[0];
regvalue = Enable ? 0xF77EFCFE : 0 ;
WriteIODW(&pRegister->GINTMSK, regvalue);
}
/**
* @brief Set a specified interrupt to be enable or disable.
* @param[in] EnableFlag Specify interrupt bit for enable of disable. Each bit's meaning is like below \n
* - EnableFlag[0] : Set Transfer Done interrupt enable or disable. \n
* @return None.
* @see NX_MPEGTSIF_GetInterruptNumber, NX_MPEGTSIF_SetInterruptEnable,
* NX_MPEGTSIF_GetInterruptEnable,
* NX_MPEGTSIF_GetInterruptEnable32, NX_MPEGTSIF_GetInterruptPending,
* NX_MPEGTSIF_GetInterruptPending32, NX_MPEGTSIF_ClearInterruptPending,
* NX_MPEGTSIF_ClearInterruptPending32, NX_MPEGTSIF_SetInterruptEnableAll,
* NX_MPEGTSIF_GetInterruptEnableAll, NX_MPEGTSIF_GetInterruptPendingAll,
* NX_MPEGTSIF_ClearInterruptPendingAll, NX_MPEGTSIF_GetInterruptPendingNumber
*/
void NX_MPEGTSIF_SetInterruptEnable32( U32 EnableFlag )
{
register U32 regval;
const U32 IRQENB_POS = 8;
const U32 IRQENB = 1UL<<IRQENB_POS;
const U32 IRQPEND = 1UL<<15;
NX_ASSERT( CNULL != __g_pRegister );
regval = __g_pRegister->CTRL;
regval &= ~(IRQENB | IRQPEND);
regval |= ((U32)EnableFlag & 0x01)<<IRQENB_POS;
// __g_pRegister->CTRL = regval;
WriteIODW(&__g_pRegister->CTRL, regval);
}
/**
* @brief Enable the MPEG-TS Interface module.
* @param[in] bEnb Set this as CTRUE to enable the MPEG-TS interface module. \n
* Set this as CFALSE to disable the MPEG-TS interface module.
* @return None.
* @see NX_MPEGTSIF_GetEnable, NX_MPEGTSIF_GetErrorFlag
*/
void NX_MPEGTSIF_SetEnable( CBOOL bEnb )
{
const U32 IRQPEND = 1UL<<15;
const U32 ENB_POS = 6;
const U32 ENB = 1UL<<ENB_POS;
register U32 regval;
NX_ASSERT( 0==bEnb || 1==bEnb );
NX_ASSERT( CNULL != __g_pRegister );
regval = __g_pRegister->CTRL;
regval &= ~(ENB | IRQPEND);
regval |= ((bEnb&1)<<ENB_POS);
// __g_pRegister->CTRL = regval;
WriteIODW(&__g_pRegister->CTRL, regval);
}
/**
* @brief Set all interrupts to be enabled or disabled.
* @param[in] bEnb Set it as CTRUE to enable all interrupts. \n
* Set it as CFALSE to disable all interrupts.
* @return None.
* @see NX_MPEGTSIF_GetInterruptNumber, NX_MPEGTSIF_SetInterruptEnable,
* NX_MPEGTSIF_GetInterruptEnable, NX_MPEGTSIF_SetInterruptEnable32,
* NX_MPEGTSIF_GetInterruptEnable32, NX_MPEGTSIF_GetInterruptPending,
* NX_MPEGTSIF_GetInterruptPending32, NX_MPEGTSIF_ClearInterruptPending,
* NX_MPEGTSIF_ClearInterruptPending32,
* NX_MPEGTSIF_GetInterruptEnableAll, NX_MPEGTSIF_GetInterruptPendingAll,
* NX_MPEGTSIF_ClearInterruptPendingAll, NX_MPEGTSIF_GetInterruptPendingNumber
*/
void NX_MPEGTSIF_SetInterruptEnableAll( CBOOL bEnb )
{
register U32 regval;
const U32 IRQENB_POS = 8;
const U32 IRQENB = 1UL<<IRQENB_POS;
const U32 IRQPEND = 1UL<<15;
NX_ASSERT( (0==bEnb) || (1==bEnb) );
NX_ASSERT( CNULL != __g_pRegister );
regval = __g_pRegister->CTRL;
regval &= ~(IRQENB | IRQPEND);
regval |= ((U32)bEnb)<<IRQENB_POS;
// __g_pRegister->CTRL = regval;
WriteIODW(&__g_pRegister->CTRL, regval);
}
/**
* @brief Set 2bit value
* @param[in] Value This Value is changed when SetBit2() executed.
* @param[in] Bit Bit number
* @param[in] BitValue Set value of bit
* @return None.
* @see NX_GPIO_GetBit2
*/
__inline void NX_GPIO_SetBit2
(
volatile U32* Value,
U32 Bit,
U32 BitValue
)
{
register U32 newvalue = *Value;
NX_ASSERT( CNULL != Value );
NX_ASSERT( NX_GPIO_MAX_BIT > Bit );
newvalue = (U32)(newvalue & ~(3UL<<(Bit*2)));
newvalue = (U32)(newvalue | (BitValue<<(Bit*2)));
// *Value = newvalue;
WriteIODW(Value, newvalue);
}
/**
* @brief Set clock generator's operation
* @param[in] Enable \b CTRUE indicate that Enable of clock generator. \n
* \b CFALSE indicate that Disable of clock generator.
* @return None.
* @see NX_PPM_SetClockPClkMode, NX_PPM_GetClockPClkMode,
* NX_PPM_SetClockSource, NX_PPM_GetClockSource,
* NX_PPM_SetClockDivisor, NX_PPM_GetClockDivisor,
* NX_PPM_GetClockDivisorEnable
*/
void NX_PPM_SetClockDivisorEnable( CBOOL Enable )
{
const U32 CLKGENENB_POS = 2;
const U32 CLKGENENB_MASK = 1UL << CLKGENENB_POS;
register U32 ReadValue;
NX_ASSERT( (0==Enable) ||(1==Enable) );
NX_ASSERT( CNULL != __g_pRegister );
ReadValue = __g_pRegister->PPM_CLKENB;
ReadValue &= ~CLKGENENB_MASK;
ReadValue |= (U32)Enable << CLKGENENB_POS;
// __g_pRegister->PPM_CLKENB = ReadValue;
WriteIODW(&__g_pRegister->PPM_CLKENB, ReadValue);
}
/**
* @brief Set all interrupts to be enables or disables.
* @param[in] ModuleIndex A index of module. (0:GPIOA, 1:GPIOB, 2:GPIOC )
* @param[in] Enable \b CTRUE indicate that Set to all interrupt enable. \n
* \b CFALSE indicate that Set to all interrupt disable.
* @return None.
* @see NX_GPIO_GetInterruptNumber, NX_GPIO_SetInterruptEnable,
* NX_GPIO_GetInterruptEnable, NX_GPIO_SetInterruptEnable32,
* NX_GPIO_GetInterruptEnable32, NX_GPIO_GetInterruptPending,
* NX_GPIO_GetInterruptPending32, NX_GPIO_ClearInterruptPending,
* NX_GPIO_ClearInterruptPending32,
* NX_GPIO_GetInterruptEnableAll, NX_GPIO_GetInterruptPendingAll,
* NX_GPIO_ClearInterruptPendingAll, NX_GPIO_GetInterruptPendingNumber
*/
void NX_GPIO_SetInterruptEnableAll( U32 ModuleIndex, CBOOL Enable )
{
register U32 setvalue;
NX_ASSERT( NUMBER_OF_GPIO_MODULE > ModuleIndex );
NX_ASSERT( (0==Enable) || (1==Enable) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
if( Enable )
{ setvalue = ~(0UL); }
else
{ setvalue = 0UL; }
// __g_ModuleVariables[ModuleIndex].pRegister->GPIOxINTENB = setvalue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].pRegister->GPIOxINTENB, setvalue);
NX_GPIO_SetInterruptEnable32(ModuleIndex, setvalue);
}
void NX_CRYPTO_SetInterruptEnable( U32 ModuleIndex, CBOOL Enb )
{
register NX_CRYPTO_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_CRYPTO_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_pRegister[ModuleIndex] );
NX_ASSERT( Enb == CTRUE || Enb == CFALSE );
pRegister = __g_pRegister[ModuleIndex];
//@modified choiyk 2012-11-15 오후 4:03:19
// 해당 신호들은 토글용 신호들이다.
regvalue = ReadIODW(&pRegister->CRYPTO_CRT_CTRL0);
regvalue = regvalue & (~(0x00ff));
if( Enb ) regvalue = regvalue | (1<<10);
else regvalue = regvalue & (~(1<<10));
WriteIODW(&pRegister->CRYPTO_CRT_CTRL0, regvalue);
}
void NX_CRYPTO_SetInterruptMask( U32 ModuleIndex, U32 Mask )
{
register NX_CRYPTO_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_CRYPTO_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_pRegister[ModuleIndex] );
NX_ASSERT( Mask <= 1 );
pRegister = __g_pRegister[ModuleIndex];
//@modified choiyk 2012-11-15 오후 4:03:19
// 해당 신호들은 토글용 신호들이다.
regvalue = ReadIODW(&pRegister->CRYPTO_CRT_CTRL0);
regvalue = regvalue & (~(0x00ff));
if( Mask ) regvalue = regvalue | (1<<9);
else regvalue = regvalue & (~(1<<9));
WriteIODW(&pRegister->CRYPTO_CRT_CTRL0, regvalue);
}
void NX_DISPTOP_CLKGEN_SetClockOutInv( U32 ModuleIndex, U32 Index, CBOOL OutClkInv )
{
const U32 OUTCLKINV_POS = 1;
const U32 OUTCLKINV_MASK = 1UL << OUTCLKINV_POS;
register U32 ReadValue;
//NX_ASSERT( 2 > Index );
//NX_ASSERT( (0==OutClkInv) ||(1==OutClkInv) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister );
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1];
ReadValue &= ~OUTCLKINV_MASK;
ReadValue |= OutClkInv << OUTCLKINV_POS;
//__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1] = ReadValue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1], ReadValue);
}
/**
* @brief Set clock divisor of specified clock generator.
* @param[in] ModuleIndex An index of module ( 0 ~ 1 ).
* @param[in] Index Select clock generator( 0 : clock generator 0 )
* @param[in] Divisor Clock divisor ( 1 ~ 256 ).
* @return None.
* @remarks CLKGEN have one clock generator. so \e Index must set to 0.
* @see NX_DISPTOP_CLKGEN_SetClockPClkMode, NX_DISPTOP_CLKGEN_GetClockPClkMode,
* NX_DISPTOP_CLKGEN_SetClockSource, NX_DISPTOP_CLKGEN_GetClockSource,
* NX_DISPTOP_CLKGEN_GetClockDivisor,
* NX_DISPTOP_CLKGEN_SetClockDivisorEnable, NX_DISPTOP_CLKGEN_GetClockDivisorEnable
*/
void NX_DISPTOP_CLKGEN_SetClockDivisor( U32 ModuleIndex, U32 Index, U32 Divisor )
{
const U32 CLKDIV_POS = 5;
const U32 CLKDIV_MASK = 0xFF << CLKDIV_POS;
register U32 ReadValue;
NX_ASSERT( NUMBER_OF_DISPTOP_CLKGEN_MODULE > ModuleIndex );
//NX_ASSERT( 0 == Index );
NX_ASSERT( 1 <= Divisor && Divisor <= 256 );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister );
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1];
ReadValue &= ~CLKDIV_MASK;
ReadValue |= (Divisor-1) << CLKDIV_POS;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1], ReadValue);
}
CBOOL NX_DISPTOP_CLKGEN_SetInputInv( U32 ModuleIndex, U32 Index, CBOOL InClkInv )
{
const U32 INCLKINV_POS = 4 + Index;
const U32 INCLKINV_MASK = 1UL << INCLKINV_POS;
register U32 ReadValue;
NX_ASSERT( (0==InClkInv) ||(1==InClkInv) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister )
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB;
ReadValue &= ~INCLKINV_MASK;
ReadValue |= InClkInv << INCLKINV_POS;
//__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB = ReadValue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB, ReadValue);
return CTRUE;
}
/**
* @brief Clear pending state of all interrupts.
* @param[in] ModuleIndex an index of module.
* @return None.
* @see NX_TIMER_GetInterruptNumber, NX_TIMER_SetInterruptEnable,
* NX_TIMER_GetInterruptEnable, NX_TIMER_SetInterruptEnable32,
* NX_TIMER_GetInterruptEnable32, NX_TIMER_GetInterruptPending,
* NX_TIMER_GetInterruptPending32, NX_TIMER_ClearInterruptPending,
* NX_TIMER_ClearInterruptPending32, NX_TIMER_SetInterruptEnableAll,
* NX_TIMER_GetInterruptEnableAll, NX_TIMER_GetInterruptPendingAll,
* NX_TIMER_GetInterruptPendingNumber
*/
void NX_TIMER_ClearInterruptPendingAll( U32 ModuleIndex )
{
register struct NX_TIMER_RegisterSet* pRegister;
const U32 INTPEND_POS = 5;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
NX_ASSERT( CTRUE == NX_TIMER_GetClockDivisorEnable(ModuleIndex) );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCONTROL;
regvalue |= 1UL << INTPEND_POS;
// pRegister->TMRCONTROL = regvalue;
WriteIODW(&pRegister->TMRCONTROL, regvalue);
}
/**
* @brief Set a clock generator to be enabled or disabled.
* @param[in] ModuleIndex an index of module.
* @param[in] Enable \b Set as CTRUE to enable a clock generator. \n
* \b Set as CFALSE to disable a clock generator.
* @return None.
* @see NX_TIMER_SetClockPClkMode, NX_TIMER_GetClockPClkMode,
* NX_TIMER_GetClockDivisorEnable,
* NX_TIMER_SetClockSource, NX_TIMER_GetClockSource,
* NX_TIMER_SetClockDivisor, NX_TIMER_GetClockDivisor
*/
void NX_TIMER_SetClockDivisorEnable( U32 ModuleIndex, CBOOL Enable )
{
const U32 CLKGENENB_POS = 2;
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( (0==Enable) || (1==Enable) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCLKENB;
regvalue &= ~(1UL << CLKGENENB_POS);
regvalue |= (U32)Enable << CLKGENENB_POS;
// pRegister->TMRCLKENB = regvalue;
WriteIODW(&pRegister->TMRCLKENB, regvalue);
}
/**
* @brief Set clock source of clock generator
* @param[in] Index Select clock generator( 0 : clock generator 0 );
* @param[in] ClkSrc Select clock source of clock generator.\n
* 0:PLL0, 1:PLL1, 2:None, 3:XTI \n
* @remarks PPM controller have one clock generator. so \e Index must set to 0.
* @return None.
* @see NX_PPM_SetClockPClkMode, NX_PPM_GetClockPClkMode,
* NX_PPM_GetClockSource,
* NX_PPM_SetClockDivisor, NX_PPM_GetClockDivisor,
* NX_PPM_SetClockDivisorEnable, NX_PPM_GetClockDivisorEnable
*/
void NX_PPM_SetClockSource( U32 Index, U32 ClkSrc )
{
const U32 CLKSRCSEL_POS = 2;
const U32 CLKSRCSEL_MASK = 0x07 << CLKSRCSEL_POS;
register U32 ReadValue;
NX_ASSERT( 0 == Index );
NX_ASSERT( 4 > ClkSrc );
NX_ASSERT( CNULL != __g_pRegister );
ReadValue = __g_pRegister->PPM_CLKGEN[Index];
ReadValue &= ~CLKSRCSEL_MASK;
ReadValue |= ClkSrc << CLKSRCSEL_POS;
// __g_pRegister->PPM_CLKGEN[Index] = ReadValue;
WriteIODW(&__g_pRegister->PPM_CLKGEN[Index], ReadValue);
}
/**
* @brief Set clock divisor of specified clock generator.
* @param[in] Index Select clock generator( 0 : clock generator 0 );
* @param[in] Divisor Clock divisor ( 1 ~ 256 ).
* @return None.
* @remarks PPM controller have one clock generator. so \e Index must set to 0.
* @see NX_PPM_SetClockPClkMode, NX_PPM_GetClockPClkMode,
* NX_PPM_SetClockSource, NX_PPM_GetClockSource,
* NX_PPM_GetClockDivisor,
* NX_PPM_SetClockDivisorEnable, NX_PPM_GetClockDivisorEnable
*/
void NX_PPM_SetClockDivisor( U32 Index, U32 Divisor )
{
const U32 CLKDIV_POS = 5;
const U32 CLKDIV_MASK = 0xFF << CLKDIV_POS;
register U32 ReadValue;
NX_ASSERT( 0 == Index );
NX_ASSERT( 1 <= Divisor && Divisor <= 256 );
NX_ASSERT( CNULL != __g_pRegister );
ReadValue = __g_pRegister->PPM_CLKGEN[Index];
ReadValue &= ~CLKDIV_MASK;
ReadValue |= (Divisor-1) << CLKDIV_POS;
// __g_pRegister->PPM_CLKGEN[Index] = ReadValue;
WriteIODW(&__g_pRegister->PPM_CLKGEN[Index], ReadValue);
}
/**
* @brief Set the SYNC mode.
* @param[in] syncmode Specifies the SYNC mode which is one of @ref NX_MPEGTSIF_SYNCMODE enum.
* @return None.
* @remarks Bit Sync means that active sync period is a one bit time. \n
* Byte Sync means that active sync period is a one byte time.
* @see NX_MPEGTSIF_SYNCMODE,
* NX_MPEGTSIF_SetClockPolarity, NX_MPEGTSIF_GetClockPolarity,
* NX_MPEGTSIF_SetDataPolarity, NX_MPEGTSIF_GetDataPolarity,
* NX_MPEGTSIF_SetSyncSource, NX_MPEGTSIF_GetSyncSource,
* NX_MPEGTSIF_GetSyncMode,
* NX_MPEGTSIF_SetWordCount, NX_MPEGTSIF_GetWordCount
*/
void NX_MPEGTSIF_SetSyncMode( NX_MPEGTSIF_SYNCMODE syncmode )
{
const U32 IRQPEND = 1UL<<15;
const U32 SYNCMODE_BITPOS = 12;
const U32 SYNCMODE_MASK = 0x01 << SYNCMODE_BITPOS;
register U32 regval;
NX_ASSERT( (NX_MPEGTSIF_SYNCMODE_BIT==syncmode) || (NX_MPEGTSIF_SYNCMODE_BYTE==syncmode) );
NX_ASSERT( CNULL != __g_pRegister );
regval = __g_pRegister->CTRL & ~(IRQPEND | SYNCMODE_MASK);
if( NX_MPEGTSIF_SYNCMODE_BYTE == syncmode )
regval |= SYNCMODE_MASK;
// __g_pRegister->CTRL = regval;
WriteIODW(&__g_pRegister->CTRL, regval);
}
/**
* @brief Set clock generator's operation
* @param[in] ModuleIndex An index of module ( 0 ~ 1 ).
* @param[in] Enable \b CTRUE indicates that Enable of clock generator. \n
* \b CFALSE indicates that Disable of clock generator.
* @return None.
* @see NX_DISPTOP_CLKGEN_SetClockPClkMode, NX_DISPTOP_CLKGEN_GetClockPClkMode,
* NX_DISPTOP_CLKGEN_SetClockSource, NX_DISPTOP_CLKGEN_GetClockSource,
* NX_DISPTOP_CLKGEN_SetClockDivisor, NX_DISPTOP_CLKGEN_GetClockDivisor,
* NX_DISPTOP_CLKGEN_GetClockDivisorEnable
*/
void NX_DISPTOP_CLKGEN_SetClockDivisorEnable( U32 ModuleIndex, CBOOL Enable )
{
const U32 CLKGENENB_POS = 2;
const U32 CLKGENENB_MASK = 1UL << CLKGENENB_POS;
register U32 ReadValue;
NX_ASSERT( NUMBER_OF_DISPTOP_CLKGEN_MODULE > ModuleIndex );
NX_ASSERT( (0==Enable) ||(1==Enable) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister );
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB;
//ReadValue = NX_DISPTOP_CLKGEN_GetClockDivisorEnable(ModuleIndex);
ReadValue &= ~CLKGENENB_MASK;
ReadValue |= (U32)Enable << CLKGENENB_POS;
// __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB = ReadValue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB, ReadValue);
}
/**
* @brief Set a clock generator to be enabled or disabled.
* @param[in] Enable \b CTRUE indicate that Clock generator enable. \n
* \b CFALSE indicate that Clock generator disable.
* @return None.
* @see NX_PWM_SetClockPClkMode, NX_PWM_GetClockPClkMode,
* NX_PWM_GetClockDivisorEnable,
* NX_PWM_SetClockSource, NX_PWM_GetClockSource,
* NX_PWM_SetClockDivisor, NX_PWM_GetClockDivisor
*/
void NX_PWM_SetClockDivisorEnable( CBOOL Enable )
{
const U32 CLKGENENB_POS = 2;
register struct NX_PWM_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( (0==Enable) || (1==Enable) );
NX_ASSERT( CNULL != __g_pRegister );
pRegister = __g_pRegister;
regvalue = pRegister->PWM_CLKENB;
regvalue &= ~(1UL << CLKGENENB_POS);
regvalue |= (U32)Enable << CLKGENENB_POS;
// pRegister->PWM_CLKENB = regvalue;
WriteIODW(&pRegister->PWM_CLKENB, regvalue);
}
/**
* @brief Set clock source of clock generator
* @param[in] ModuleIndex An index of module ( 0 ~ 1 ).
* @param[in] Index Select clock generator( 0 : clock generator 0 );
* @param[in] ClkSrc Select clock source of clock generator ( 0: PLL0, 1:PLL1 ).
* @remarks CLKGEN have one clock generator. so \e Index must set to 0.
* @return None.
* @see NX_DISPTOP_CLKGEN_SetClockPClkMode, NX_DISPTOP_CLKGEN_GetClockPClkMode,
* NX_DISPTOP_CLKGEN_GetClockSource,
* NX_DISPTOP_CLKGEN_SetClockDivisor, NX_DISPTOP_CLKGEN_GetClockDivisor,
* NX_DISPTOP_CLKGEN_SetClockDivisorEnable, NX_DISPTOP_CLKGEN_GetClockDivisorEnable
*/
void NX_DISPTOP_CLKGEN_SetClockSource( U32 ModuleIndex, U32 Index, U32 ClkSrc )
{
const U32 CLKSRCSEL_POS = 2;
const U32 CLKSRCSEL_MASK = 0x07 << CLKSRCSEL_POS;
register U32 ReadValue;
NX_ASSERT( NUMBER_OF_DISPTOP_CLKGEN_MODULE > ModuleIndex );
//NX_ASSERT( 0 == Index );
//NX_ASSERT( 2 > ClkSrc );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister );
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1];
ReadValue &= ~CLKSRCSEL_MASK;
ReadValue |= ClkSrc << CLKSRCSEL_POS;
// __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1] = ReadValue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1], ReadValue);
}
/**
* @brief Set 1bit value
* @param[in] Value This Value is changed when SetBit() executed.
* @param[in] Bit Bit number
* @param[in] Enable \b CTRUE( Set ).\n
* \b CFALSE( Clear )
* @return None.
* @see NX_GPIO_GetBit
*/
__inline void NX_GPIO_SetBit
(
volatile U32* Value,
U32 Bit,
CBOOL Enable
)
{
register U32 newvalue;
NX_ASSERT( CNULL != Value );
NX_ASSERT( NX_GPIO_MAX_BIT > Bit );
newvalue = *Value;
newvalue &= ~(1UL << Bit );
newvalue |= (U32)Enable << Bit ;
// *Value = newvalue;
WriteIODW(Value, newvalue);
}
/**
* @brief Stop the timer.
* @param[in] ModuleIndex an index of module.
* @return None.
* @see NX_TIMER_Run,
* NX_TIMER_SetWatchDogEnable, NX_TIMER_SetTClkDivider,
* NX_TIMER_SetMatchCounter, NX_TIMER_GetMatchCounter,
* NX_TIMER_SetTimerCounter, NX_TIMER_GetTimerCounter
*/
void NX_TIMER_Stop( U32 ModuleIndex )
{
const U32 INTPEND = (1UL<<5);
const U32 RUN = (1UL<<3);
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
NX_ASSERT( CTRUE == NX_TIMER_GetClockDivisorEnable(ModuleIndex) );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCONTROL;
regvalue &= ~(INTPEND | RUN);
// pRegister->TMRCONTROL = regvalue;
WriteIODW(&pRegister->TMRCONTROL, regvalue);
}
/**
* @brief Set a clock source for clock generator.
* @param[in] ModuleIndex an index of module.
* @param[in] Index an index of clock generator
* @param[in] ClkSrc a source clock for specified clock generator, 0 for PLL0 or 1 for PLL1.
* @return None.
* @remarks Since the timer module has only one clock generator, you have to only set @a Index as 0.
* @see NX_TIMER_SetClockPClkMode, NX_TIMER_GetClockPClkMode,
* NX_TIMER_SetClockDivisorEnable, NX_TIMER_GetClockDivisorEnable,
* NX_TIMER_GetClockSource,
* NX_TIMER_SetClockDivisor, NX_TIMER_GetClockDivisor
*/
void NX_TIMER_SetClockSource( U32 ModuleIndex, U32 Index, U32 ClkSrc )
{
const U32 CLKSRCSEL_POS = 2;
const U32 CLKSRCSEL_MASK = 0x7;
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( 0 == Index );
NX_ASSERT( 1 >= ClkSrc );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCLKGEN;
regvalue &= ~(CLKSRCSEL_MASK << CLKSRCSEL_POS);
regvalue |= ( ClkSrc << CLKSRCSEL_POS );
// pRegister->TMRCLKGEN = regvalue;
WriteIODW(&pRegister->TMRCLKGEN, regvalue);
}
/**
* @brief Set a specified interrupt to be enable or disable.
* @param[in] ModuleIndex an index of module.
* @param[in] EnableFlag Specify interrupt bit for enable of disable. Each bit's meaning is like below \n
* - EnableFlag[0] : Set TIMER Counter interrupt enable or disable. \n
* @return None.
* @see NX_TIMER_GetInterruptNumber, NX_TIMER_SetInterruptEnable,
* NX_TIMER_GetInterruptEnable,
* NX_TIMER_GetInterruptEnable32, NX_TIMER_GetInterruptPending,
* NX_TIMER_GetInterruptPending32, NX_TIMER_ClearInterruptPending,
* NX_TIMER_ClearInterruptPending32, NX_TIMER_SetInterruptEnableAll,
* NX_TIMER_GetInterruptEnableAll, NX_TIMER_GetInterruptPendingAll,
* NX_TIMER_ClearInterruptPendingAll, NX_TIMER_GetInterruptPendingNumber
*/
void NX_TIMER_SetInterruptEnable32( U32 ModuleIndex, U32 EnableFlag )
{
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
const U32 INTPEND_POS = 5;
const U32 INTENB_POS = 4;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
NX_ASSERT( CTRUE == NX_TIMER_GetClockDivisorEnable(ModuleIndex) );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCONTROL;
regvalue &= ~(( 1UL << INTPEND_POS ) | ( 1UL << INTENB_POS ) );
regvalue |= (U32)((EnableFlag&0x01) << INTENB_POS);
// pRegister->TMRCONTROL = regvalue;
WriteIODW(&pRegister->TMRCONTROL, regvalue);
}
//--------
// Syncgen 용 Out Clock 1/2 ns delay Enable
// SRGB888 용 !
//@added choiyk 2012-10-31 오후 3:41:47
//---------
void NX_DISPTOP_CLKGEN_SetClockOutSelect( U32 ModuleIndex, U32 Index, CBOOL bBypass )
{
// const U32 OUTCLKSEL_POS = 0;
// const U32 OUTCLKSEL_MASK = 1UL << OUTCLKSEL_POS;
// register struct NX_DPC_RegisterSet* pRegister;
register U32 ReadValue;
NX_ASSERT( Index == 1 );
NX_ASSERT( (0==bBypass) ||(1==bBypass) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].__g_pRegister )
ReadValue = __g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1];
ReadValue = ReadValue & (~0x01);
ReadValue = ReadValue | bBypass;
//__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKENB = ReadValue;
WriteIODW(&__g_ModuleVariables[ModuleIndex].__g_pRegister->CLKGEN[Index<<1], ReadValue);
}
/**
* @brief Set a clock divider for clock generator.
* @param[in] Index Select clock generator( 0 ).
* @param[in] Divisor Divide value of clock generator( 1 ~ 256 ).
* @return None.
* @remarks PWM module have only ONE clock generator. so Index is always setting to 0.
* @see NX_PWM_SetClockPClkMode, NX_PWM_GetClockPClkMode,
* NX_PWM_SetClockDivisorEnable, NX_PWM_GetClockDivisorEnable,
* NX_PWM_SetClockSource, NX_PWM_GetClockSource,
* NX_PWM_GetClockDivisor
*/
void NX_PWM_SetClockDivisor( U32 Index, U32 Divisor )
{
const U32 CLKDIV_POS = 5;
const U32 CLKDIV_MASK = 0xFF;
register struct NX_PWM_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( 0 == Index );
NX_ASSERT( (1 <= Divisor) && ( 256 >= Divisor ) );
NX_ASSERT( CNULL != __g_pRegister );
pRegister = __g_pRegister;
regvalue = pRegister->PWM_CLKGEN;
regvalue &= ~(CLKDIV_MASK << CLKDIV_POS);
regvalue |= (Divisor-1) << CLKDIV_POS;
// pRegister->PWM_CLKGEN = regvalue;
WriteIODW(&pRegister->PWM_CLKGEN, regvalue);
}
/**
* @brief Set a clock source for clock generator.
* @param[in] Index Select clock generator
* @param[in] ClkSrc Select clock source ( 0 (PLL0), 1 (PLL1) )
* @return None.
* @remarks PWM module have only ONE clock generator. so Index is always setting to 0.
* @see NX_PWM_SetClockPClkMode, NX_PWM_GetClockPClkMode,
* NX_PWM_SetClockDivisorEnable, NX_PWM_GetClockDivisorEnable,
* NX_PWM_GetClockSource,
* NX_PWM_SetClockDivisor, NX_PWM_GetClockDivisor
*/
void NX_PWM_SetClockSource( U32 Index, U32 ClkSrc )
{
const U32 CLKSRCSEL_POS = 2;
const U32 CLKSRCSEL_MASK = 0x7;
register struct NX_PWM_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( 0 == Index );
NX_ASSERT( 1 >= ClkSrc );
NX_ASSERT( CNULL != __g_pRegister );
pRegister = __g_pRegister;
regvalue = pRegister->PWM_CLKGEN;
regvalue &= ~(CLKSRCSEL_MASK << CLKSRCSEL_POS);
regvalue |= ( ClkSrc << CLKSRCSEL_POS );
// pRegister->PWM_CLKGEN = regvalue;
WriteIODW(&pRegister->PWM_CLKGEN, regvalue);
}
/**
* @brief Set a internal clock divider for a timer clock.
* @param[in] ModuleIndex an index of module.
* @param[in] Clock a TCLK to be used.
* @see NX_TIMER_Run, NX_TIMER_Stop,
* NX_TIMER_SetWatchDogEnable,
* NX_TIMER_SetMatchCounter, NX_TIMER_GetMatchCounter,
* NX_TIMER_SetTimerCounter, NX_TIMER_GetTimerCounter
*/
void NX_TIMER_SetTClkDivider( U32 ModuleIndex, NX_TIMER_CLOCK Clock )
{
const U32 INTPEND = (1UL<<5);
const U32 SELTCLK = (3UL<<0);
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( 4 > Clock );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
NX_ASSERT( CTRUE == NX_TIMER_GetClockDivisorEnable(ModuleIndex) );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCONTROL;
regvalue &= ~(INTPEND | SELTCLK);
regvalue |= (U32)Clock;
// pRegister->TMRCONTROL = regvalue;
WriteIODW(&pRegister->TMRCONTROL, regvalue);
}
/**
* @brief Set a clock divider for clock generator.
* @param[in] ModuleIndex an index of module.
* @param[in] Index an index of clock generator
* @param[in] Divisor a divide value of clock generator from 1 to 256.
* @return None.
* @remarks Since the timer module has only one clock generator, you have to only set @a Index as 0.
* @see NX_TIMER_SetClockPClkMode, NX_TIMER_GetClockPClkMode,
* NX_TIMER_SetClockDivisorEnable, NX_TIMER_GetClockDivisorEnable,
* NX_TIMER_SetClockSource, NX_TIMER_GetClockSource,
* NX_TIMER_GetClockDivisor
*/
void NX_TIMER_SetClockDivisor( U32 ModuleIndex, U32 Index, U32 Divisor )
{
const U32 CLKDIV_POS = 5;
const U32 CLKDIV_MASK = 0xFF;
register struct NX_TIMER_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_TIMER_MODULE > ModuleIndex );
NX_ASSERT( 0 == Index );
NX_ASSERT( (1 <= Divisor) && ( 256 >= Divisor ) );
NX_ASSERT( CNULL != __g_ModuleVariables[ModuleIndex].pRegister );
pRegister = __g_ModuleVariables[ModuleIndex].pRegister;
regvalue = pRegister->TMRCLKGEN;
regvalue &= ~(CLKDIV_MASK << CLKDIV_POS);
regvalue |= (Divisor-1) << CLKDIV_POS;
// pRegister->TMRCLKGEN = regvalue;
WriteIODW(&pRegister->TMRCLKGEN, regvalue);
}
