/******************************************************************************
* Configure the I2S controller to transmit data, which will be read out from
* the local memory vector (Mem)
*
* @param u32NrSamples is the number of samples to store.
*
* @return none.
*****************************************************************************/
void fnAudioPlay(XAxiDma AxiDma, u32 u32NrSamples)
{
union ubitField uTransferVariable;
if (Demo.u8Verbose)
{
xil_printf("\r\nEnter Playback function");
}
uTransferVariable.l = XAxiDma_SimpleTransfer(&AxiDma,(u32) MEM_BASE_ADDR, 5*u32NrSamples, XAXIDMA_DMA_TO_DEVICE);
if (uTransferVariable.l != XST_SUCCESS)
{
if (Demo.u8Verbose)
xil_printf("\n fail @ play; ERROR: %d", uTransferVariable.l);
}
// Send number of samples to record
Xil_Out32(I2S_PERIOD_COUNT_REG, u32NrSamples);
// Start i2s initialization sequence
uTransferVariable.l = 0x00000000;
Xil_Out32(I2S_TRANSFER_CONTROL_REG, uTransferVariable.l);
uTransferVariable.bit.u32bit0 = 1;
Xil_Out32(I2S_TRANSFER_CONTROL_REG, uTransferVariable.l);
// Enable Stream function to send data (MM2S)
Xil_Out32(I2S_STREAM_CONTROL_REG, 0x00000002);
if (Demo.u8Verbose)
{
xil_printf("\r\nPlayback function done");
}
}
int Config_PR_Bitstream(char *bs_name,int sync_intr)
{
int Status;
int bs_pres;
int pres_first;
int pres_last;
int file_size;
bs_pres = check_bs_present(bs_list,bs_name);
if (bs_pres != -1 && bs_list[bs_pres].prev != NULL) //The bitstream is already in the list and is not the most recently used
{
//print("bitstream in the list\n\r");
bs_list[bs_pres].prev->next = bs_list[bs_pres].next;
if(bs_list[bs_pres].next != NULL)
{
bs_list[bs_pres].next->prev = bs_list[bs_pres].prev;
}
pres_first = find_first_bs(bs_list);
bs_list[bs_pres].prev = NULL;
bs_list[bs_pres].next = &bs_list[pres_first];
bs_list[pres_first].prev = &bs_list[bs_pres];
}
else if(bs_pres == -1)
{
//print("bitstream not in the list\n\r");
pres_last = find_last_bs(bs_list);
file_size = SD_TransferPartial(bs_name, bs_list[pres_last].addr);
if(file_size == XST_FAILURE)
{
print("bitstream transfer failed\n\r");
return XST_FAILURE;
}
//print("Successfully transferred PR files from flash to DDR\n\r");
pres_first = find_first_bs(bs_list);
bs_list[pres_last].prev->next = NULL; //make the second last element as the last element
strcpy(bs_list[pres_last].name,bs_name);
bs_list[pres_last].size = file_size;
bs_list[pres_last].prev = NULL;
bs_list[pres_last].next = &bs_list[pres_first];
bs_list[pres_first].prev = &bs_list[pres_last];
}
//print_schedule(bs_list);
//print("Central DMA Initialized\r\n");
pres_first = find_first_bs(bs_list);
Status = XAxiDma_SimpleTransfer(&xcdma,bs_list[pres_first].addr,bs_list[pres_first].size,XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
xil_printf("DMA transfer failed\r\n",Status);
return XST_FAILURE;
}
TxDone = 0;
Error = 0;
if(sync_intr)
{
Status = Sync_Zycap();
if (Status != XST_SUCCESS) {
xil_printf("interrupt failed\r\n",Status);
return XST_FAILURE;
}
}
return bs_list[pres_first].size;
}
int capture_samples(u32 qw_count, struct low_level_handler *low_lev_handler) {
int error;
low_lev_handler->samples_count_pos = 0;
low_lev_handler->samples_count = qw_count;
/* Workaround. Try to fix this ASAP */
u32 qw_count_fix = (low_lev_handler->id == ADC_ID) ? qw_count : qw_count-1;
/* Clear status registers before proceeding. Just a test!!! FIXME */
if(low_lev_handler->id == ADC_ID)
write_soft_register(0x0, FMC150_BASEADDR + FMC150_STATUS_REG_OFFSET, 0);
else if(low_lev_handler->id == DDC_ID)
write_soft_register(0x0, BPM_DDC_BASEADDR + BPM_DDC_STATUS_REG_OFFSET, 0);
#ifdef LOW_LEV_DEBUG
xil_printf("capture_samples: samples_count_pos = %d\n", low_lev_handler->samples_count_pos);
xil_printf("capture_samples: samples_count = %d\n", low_lev_handler->samples_count);
#endif
//XAxiDma_Reset(&low_lev_handler->attr->AxiDma);
// Check if DMA has completed its reset
/*if(XAxiDma_ResetIsDone(&low_lev_handler->attr->AxiDma) == 0){
#ifdef LOW_LEV_DEBUG
xil_printf("DMA has not completed its reset!\n");
#endif
return ERROR;
}
XAxiDma_IntrEnable(&low_lev_handler->attr->AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);*/
/* Note the fact that each sample is SAMPLE_SIZE*8-bit (SAMPLE_SIZE bytes) large. Therefore we have (qw_count * SAMPLE_SIZE) bytes */
//xil_printf("mem start_addr = %08X\n", low_lev_handler->attr->mem_start_addr);
if((error = XAxiDma_SimpleTransfer(&low_lev_handler->attr->AxiDma, (u32 *)/*dma_buf*/(low_lev_handler->attr->mem_start_addr), qw_count*(low_lev_handler->attr->sample_size), XAXIDMA_DEVICE_TO_DMA)) != XST_SUCCESS){
xil_printf("Error transferring data to buffer! Error: %s\n", (error == XST_FAILURE) ? "XST_FAILURE" : "XST_INVALID_PARAM");
return ERROR;
}
// start the adc capture. 0 -> 1 transition on bit #21
XIo_Out32(low_lev_handler->baseaddr, 0x00000000);
//delay(100);
//xil_printf("capture_ctl register reg: %08X\n", XIo_In32(low_lev_handler->baseaddr));
/* Here we have # of SAMPLE_SIZE*8-bit samples (= SAMPLE_SIZE samples) */
/* Check for the qw_count - 1 !!!!*/
XIo_Out32(low_lev_handler->baseaddr, (0x00200000 | qw_count_fix));
//delay(100);
//xil_printf("capture_ctl register reg: %08X\n", XIo_In32(low_lev_handler->baseaddr));
return SUCCESS;
}
int DMA_send(void) {
int Status;
//DMA_wait();
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32)&(ref_genome[0]),
100000/*sizeof(ref_genome)*/, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
xil_printf("address = %X\r\n", (u32)&(ref_genome[0]));
xil_printf("size = %d\r\n", sizeof(ref_genome));
xil_printf("DMA_send failed: %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
int main()
{
int status;
int temp,i,j;
//static int Result1[SIZE];
init_platform();
// Initialize DMA
init_dma();
//get data from the PL block to DDR RAM
status = XAxiDma_SimpleTransfer(&AxiDma, 0xa000000, 1023,XAXIDMA_DEVICE_TO_DMA);
/* Wait for transfer to be done */
while(XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA));
j=0;
// read data from DDR ram to UART
for(i=0;i<=1023;i+=1)
{
temp = Xil_In32(0xa000000+j);
xil_printf("DDR address 0x%x",0xa0000000+i);
xil_printf(" contains %d\n\r",temp);
j+=4;
}
return 0;
}
/**
* Sets bits contained in multiple LUTs specified by the coordinates and data in the lut_configs array.
*
* @return XST_SUCCESS or XST_FAILURE.
**/
int MiCAP_Custom_SetMultiClbBits(XGpio* gpio_InstancePtr, XAxiDma* dma_InstancePtr,LUT_config_type *lut_configs, u32 num_lut_configs) {
u8 bottom_ntop;
int Status;
int clock_row;
u32 major_frame_address;
u32 word_offset;
assert(num_lut_configs>0);
long slice_row = lut_configs[0].slice_row;
long slice_col = lut_configs[0].slice_col;
// Check if all the lutconfigs are indeed part of the same set of frames
u32 i;
for(i = 1; i<num_lut_configs; i++) {
if(!MiCAP_Custom_IsSameFrame(slice_row, slice_col, lut_configs[i].slice_row, lut_configs[i].slice_col))
return XST_FAILURE;
}
MiCAP_GetConfigurationCoordinates(slice_row, slice_col,
&bottom_ntop, &clock_row, &major_frame_address, &word_offset);
u32 frame_num = 4;
u32 frame_number_offset;
if(lut_configs[0].Resource[0][1] < 32)
frame_number_offset = 26;
else
frame_number_offset = 32;
u32 buffer[506];
u32 frame_address = XHwIcap_Custom_SetupFar7series(bottom_ntop, XHI_FAR_CLB_BLOCK, clock_row, major_frame_address, frame_number_offset);
u32 Read_frame_TxBuffer[] = {0xFFFFFFFF, 0xFFFFFFFF,0xAA995566, 0x20000000, 0x20000000, 0x30008001, 0x00000007,
0x20000000, 0x20000000, 0x30008001, 0x00000004, 0x20000000, 0x20000000,
0x20000000, 0x30002001, frame_address, 0x28006000, 0x480001FA, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x30008001, 0x0000000D, 0x20000000, 0x20000000,0xFFFFFFFF,
0xFFFFFFFF,0xFFFFFFFF};
memcpy(TxBufferPtr_rdFrame, Read_frame_TxBuffer, 57 * sizeof(u32));
// Frame Read:
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x4); // assert read ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x5); // assert read ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_rdFrame,
57*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x1)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//2) Reading the frames back
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) RxBufferPtr_rdFrame,
MAX_PKT_LEN_rdFrame, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DEVICE_TO_DMA)) {
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0); // Put data source back in reset state for next run
Xil_DCacheFlushRange((u32)RxBufferPtr_rdFrame, 540*4);
u32 *configuration = buffer + 101 + 1 + 1;
for(i = 0; i< num_lut_configs; i++) {
u32 word_offset = MiCAP_Custom_GetWordOffset(lut_configs[i].slice_row);
MiCAP_Custom_SetClbBitsInConfig(configuration, word_offset,
frame_num, frame_number_offset, lut_configs[i].Resource, lut_configs[i].Value, lut_configs[i].NumBits);
}
//3: Frame Write
u32 head[] = {0xFFFFFFFF, 0xFFFFFFFF, 0x20000000, 0xAA995566, 0x20000000, 0x20000000,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30018001, 0x03727093,
0x30002001, frame_address, 0x30008001, 0x00000001, 0x20000000, 0x300041F9};
u32 tail[] = {0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30002001, 0x00061080,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30008001, 0x0000000D,
0x20000000, 0x20000000,0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
for (j=0; j<18; j++){
TxBufferPtr_wrFrame[j] = head[j];
}
for (i=0; i<505; i++){
TxBufferPtr_wrFrame[j] = configuration[i];
j++;
}
for (i=0; i<17;i++){
TxBufferPtr_wrFrame[j] = tail[i];
j++;
}
Xil_DCacheFlushRange((u32)TxBufferPtr_wrFrame, 540*4);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x2); // assert write ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x3); // assert write ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_wrFrame,
540*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x2)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* Set up the output terminal if UART16550 is in the hardware build
* Initialize the DMA engine
* Set up Tx and Rx channels
* Set up the interrupt system for the Tx and Rx interrupts
* Submit a transfer
* Wait for the transfer to finish
* Check transfer status
* Disable Tx and Rx interrupts
* Print test status and exit
*
* @param None
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if example fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
int Tries = NUMBER_OF_TRANSFERS;
int Index;
u8 *TxBufferPtr;
u8 *RxBufferPtr;
u8 Value;
TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
RxBufferPtr = (u8 *)RX_BUFFER_BASE;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(XAxiDma_HasSg(&AxiDma)){
xil_printf("Device configured as SG mode \r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Disable all interrupts before setup */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
Value = TEST_START_VALUE;
for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
TxBufferPtr[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
#endif
/* Send a packet */
for(Index = 0; Index < Tries; Index ++) {
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (!TxDone && !RxDone && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN, 0xC);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("AXI DMA interrupt example test passed\r\n");
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
// Program entry point
int main()
{
init_platform();
int status;
//Initialize uart port
status = init_uart(uart);
if(status == XST_FAILURE){
printf("ERROR INITIALIZING UART PORT...EXITING...\n");
exit(-1);
}
// Initialize the (simple) DMA engine
status = init_dma(&axiDma);
if (status != XST_SUCCESS) {
exit(-1);
}
//Disabling the cache
Xil_DCacheDisable();
Xil_ICacheDisable();
int i=0;
int j = 0;
//always available when started
float* in = malloc(conv_channel * conv_in_x * conv_in_y * sizeof(float));
float* result = malloc(output_size * sizeof(float));
//receiving result from PL
//status = XAxiDma_SimpleTransfer(&axiDma,(u32)result,sizeof(float) * output_size,
// XAXIDMA_DEVICE_TO_DMA);
for(i=0;i<10;i++){
// result[i]= i;
printf("%f\n",(float)result[i]);
}
while(j++<5){
/*for(i=0;i<10;i++){
printf("%f\n",(float)result[i]);
}*/
for(i=0;i<256;i++){
in[i] = (float)/*i/100;*/((i*j)+2+i)/1000;
}
//receiving input
//uart_receive(in,(conv_channel*conv_in_x*conv_in_y)*sizeof(float));
//printf("test is %c\n",test);
printf("*** ATTEMPT NUMBER %d ***\n",j);
//flushing the relative cache range
//Xil_DCacheFlushRange((unsigned)in,(conv_channel*conv_in_x*conv_in_y) * sizeof(float));
//Handling the DMA to PL input transfer
status = XAxiDma_SimpleTransfer(&axiDma,(u32)in,sizeof(float) * (conv_channel*conv_in_x*conv_in_y),
XAXIDMA_DMA_TO_DEVICE);
usleep(3000000);
/*printf("BEFORE\n");
for(i=0;i<10;i++){
printf("%f\n",(float)result[i]);
}*/
//receiving result from PL
status = XAxiDma_SimpleTransfer(&axiDma,(u32)result,sizeof(float) * output_size,
XAXIDMA_DEVICE_TO_DMA);
//invalidating the relative cache range in order to receive again
//Xil_DCacheInvalidateRange((unsigned)result,output_size * sizeof(float));
//printing results on screen
//printf("AFTER\n");
for(i=0;i<10;i++){
// result[i]= i;
printf("%f\n",(float)result[i]);
}
//sending the results to the UART port
//uart_send(result,sizeof(float)*output_size);
//XUartPs_Send(&uart,(u8)result,sizeof(float) * output_size);
//resetting the DMA because SDK sucks
XAxiDma_Reset(&axiDma);
}
free(in);
free(result);
return 0;
}
