/**
* Initialize the XAxiPcie instance provided by the caller based on the
* given Config structure.
*
*
* @param InstancePtr is the XAxiPcie instance to operate on.The memory
* of the pointer references must be pre-allocated by the caller.
* @param CfgPtr is the device configuration structure containing
* required HW build data.
* @param EffectiveAddress is the Physical address of the hardware in a
* Virtual Memory operating system environment.It is the Base
* Address in a stand alone environment.
*
* @return
*
* - XST_SUCCESS Initialization was successful.
*
* @note None.
*
******************************************************************************/
int XAxiPcie_CfgInitialize(XAxiPcie *InstancePtr, XAxiPcie_Config *CfgPtr,
u32 EffectiveAddress)
{
u32 Data;
/* Assert arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
/* Clear instance memory and make copy of configuration */
memset(InstancePtr, 0, sizeof(XAxiPcie));
memcpy(&InstancePtr->Config, CfgPtr, sizeof(XAxiPcie_Config));
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
InstancePtr->Config.BaseAddress = EffectiveAddress;
/* Disable all interrupts */
XAxiPcie_DisableInterrupts(InstancePtr, XAXIPCIE_IM_DISABLE_ALL_MASK);
/* Max number of buses */
Data = XAxiPcie_ReadReg(InstancePtr->Config.BaseAddress,
XAXIPCIE_BI_OFFSET);
InstancePtr->MaxNumOfBuses = (u16)((Data & XAXIPCIE_BI_ECAM_SIZE_MASK) >>
XAXIPCIE_BI_ECAM_SIZE_SHIFT);
return (XST_SUCCESS);
}
/**
* This function initializes a AXI PCIe IP built as a root complex
*
* @param AxiPciePtr is a pointer to an instance of XAxiPcie data
* structure represents a root complex IP.
* @param DeviceId is AXI PCIe IP unique ID
*
* @return - XST_SUCCESS if successful.
* - XST_FAILURE if unsuccessful.
*
* @note None.
*
*
******************************************************************************/
int PcieInitRootComplex(XAxiPcie *AxiPciePtr, u16 DeviceId)
{
int Status;
u32 HeaderData;
u32 InterruptMask;
u8 BusNumber;
u8 DeviceNumber;
u8 FunNumber;
u8 PortNumber;
XAxiPcie_Config *ConfigPtr;
ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
Status = XAxiPcie_CfgInitialize(AxiPciePtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Failed to initialize PCIe Root Complex"
"IP Instance\r\n");
return XST_FAILURE;
}
if(!AxiPciePtr->Config.IncludeRootComplex) {
xil_printf("Failed to initialize...AXI PCIE is configured"
" as endpoint\r\n");
return XST_FAILURE;
}
/* See what interrupts are currently enabled */
XAxiPcie_GetEnabledInterrupts(AxiPciePtr, &InterruptMask);
xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
/* Make sure all interrupts disabled. */
XAxiPcie_DisableInterrupts(AxiPciePtr, XAXIPCIE_IM_ENABLE_ALL_MASK);
/* See what interrupts are currently pending */
XAxiPcie_GetPendingInterrupts(AxiPciePtr, &InterruptMask);
xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
/* Just if there is any pending interrupt then clear it.*/
XAxiPcie_ClearPendingInterrupts(AxiPciePtr,
XAXIPCIE_ID_CLEAR_ALL_MASK);
/*
* Read enabled interrupts and pending interrupts
* to verify the previous two operations and also
* to test those two API functions
*/
XAxiPcie_GetEnabledInterrupts(AxiPciePtr, &InterruptMask);
xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
XAxiPcie_GetPendingInterrupts(AxiPciePtr, &InterruptMask);
xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
/* Make sure link is up. */
Status = XAxiPcie_IsLinkUp(AxiPciePtr);
if (Status != TRUE ) {
xil_printf("Link is not up\r\n");
return XST_FAILURE;
}
xil_printf("Link is up\r\n");
/*
* Read back requester ID.
*/
XAxiPcie_GetRequesterId(AxiPciePtr, &BusNumber,
&DeviceNumber, &FunNumber, &PortNumber);
xil_printf("Bus Number is %02X\r\n"
"Device Number is %02X\r\n"
"Function Number is %02X\r\n"
"Port Number is %02X\r\n",
BusNumber, DeviceNumber, FunNumber, PortNumber);
/* Set up the PCIe header of this Root Complex */
XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
PCIE_CFG_CMD_STATUS_REG, &HeaderData);
HeaderData |= (PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN |
PCIE_CFG_CMD_IO_EN | PCIE_CFG_CMD_PARITY |
PCIE_CFG_CMD_SERR_EN);
XAxiPcie_WriteLocalConfigSpace(AxiPciePtr,
PCIE_CFG_CMD_STATUS_REG, HeaderData);
/*
* Read back local config reg.
* to verify the write.
*/
XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
PCIE_CFG_CMD_STATUS_REG, &HeaderData);
xil_printf("PCIe Local Config Space is %8X at register"
" CommandStatus\r\n", HeaderData);
/*
* Set up Bus number
*/
HeaderData = PCIE_CFG_PRIM_SEC_BUS;
XAxiPcie_WriteLocalConfigSpace(AxiPciePtr,
PCIE_CFG_PRI_SEC_BUS_REG, HeaderData);
/*
* Read back local config reg.
* to verify the write.
*/
XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
PCIE_CFG_PRI_SEC_BUS_REG, &HeaderData);
xil_printf("PCIe Local Config Space is %8X at register "
"Prim Sec. Bus\r\n", HeaderData);
/* Now it is ready to function */
xil_printf("Root Complex IP Instance has been successfully"
" initialized\r\n");
return XST_SUCCESS;
}
/**
* This initialize an IP built as an end point.
*
* @param XlnxEndPointPtr is a pointer to an instance of XAxiPcie data
* structure represents an end point IP.
* @param DeviceId is PCIe IP unique ID
*
* @return - XST_SUCCESS if successful
* - XST_FAILURE if unsuccessful
*
* @note None.
*
******************************************************************************/
int PCIeEndPointInitialize(XAxiPcie *XlnxEndPointPtr, u16 DeviceId)
{
int Status;
u32 HeaderData;
u32 InterruptMask;
u8 BusNum;
u8 DeviceNum;
u8 FunctionNum;
u8 PortNumber;
XAxiPcie_Config *ConfigPtr;
/* Initialization of the driver */
ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
xil_printf("Failed to initialize PCIe End Point Instance\r\n");
return XST_FAILURE;
}
Status = XAxiPcie_CfgInitialize(XlnxEndPointPtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Failed to initialize PCIe End Point Instance\r\n");
return Status;
}
/* See what interrupts are currently enabled */
XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
/* Disable.all interrupts */
XAxiPcie_DisableInterrupts(XlnxEndPointPtr,
XAXIPCIE_IM_ENABLE_ALL_MASK);
/* See what interrupts are currently pending */
XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
/* Clear the pending interrupt */
XAxiPcie_ClearPendingInterrupts(XlnxEndPointPtr,
XAXIPCIE_ID_CLEAR_ALL_MASK);
/*
* Read enabled interrupts and pending interrupts
* to verify the previous two operations and also
* to test those two API functions
*/
XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
/* Make sure link is up. */
Status = XAxiPcie_IsLinkUp(XlnxEndPointPtr);
if (Status != TRUE ) {
xil_printf("Link is not up\r\n");
return XST_FAILURE;
}
xil_printf("Link is up\r\n");
/* See if root complex has already configured this end point. */
XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
&HeaderData);
xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
if (HeaderData & PCIE_CFG_CMD_BUSM_EN) {
xil_printf("Root Complex has configured this end point\r\n");
}
else {
xil_printf("Root Complex has NOT yet configured this"
" end point\r\n");
return XST_FAILURE;
}
XAxiPcie_GetRequesterId(XlnxEndPointPtr, &BusNum,
&DeviceNum, &FunctionNum, &PortNumber);
xil_printf("Bus Number is %02X\r\n"
"Device Number is %02X\r\n"
"Function Number is %02X\r\n"
"Port Number is %02X\r\n",
BusNum, DeviceNum, FunctionNum, PortNumber);
/* Read my configuration space */
XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_ID_REG,
&HeaderData);
xil_printf("PCIe Vendor ID/Device ID Register is %08X\r\n",
HeaderData);
XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
&HeaderData);
xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CAH_LAT_HD_REG,
&HeaderData);
xil_printf("PCIe Header Type/Latency Timer Register is %08X\r\n",
HeaderData);
XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_BAR_ZERO_REG,
&HeaderData);
xil_printf("PCIe BAR 0 is %08X\r\n", HeaderData);
return XST_SUCCESS;
}
