/*! ********************************************************************************* * XcvrFskGetInstantRssi ***********************************************************************************/ uint8_t XcvrFskGetInstantRssi(void) { uint8_t u8Rssi; uint32_t t1,t2,t3; t1 = XCVR_RX_DIG->RX_DIG_CTRL; t2 = XCVR_RX_DIG->RSSI_CTRL_0; t3 = XCVR_PHY->CFG1; XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); uint32_t temp = XCVR_PHY->CFG1; temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); XCVR_PHY->CFG1 = temp; XCVR_ForceRxWu(); for(uint32_t i = 0; i < 10000; i++) { __asm("nop"); } u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); XCVR_ForceRxWd(); XCVR_RX_DIG->RX_DIG_CTRL = t1; XCVR_RX_DIG->RSSI_CTRL_0 = t2; XCVR_PHY->CFG1 = t3; return u8Rssi; }
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | XCVR_PHY_CFG1_CTS_THRESH(220) | XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ #if !RADIO_IS_GEN_2P1 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) #endif /* !RADIO_IS_GEN_2P1 */ , /* XCVR_RX_DIG configs */ .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), /* XCVR_TSM configs */ #if (DATA_PADDING_EN) .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), #else .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), #endif /* (DATA_PADDING_EN) */ /* XCVR_TX_DIG configs */
.phy_pre_ref2_init = 0x0000E739, .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | XCVR_PHY_CFG1_CTS_THRESH(0xCD) | XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), .phy_el_cfg_init =XCVR_PHY_EL_CFG_EL_ENABLE(1) | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0), /* XCVR_RX_DIG configs */ .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(1), .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), /* XCVR_TSM configs */ #if (DATA_PADDING_EN) .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), #else .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), #endif