/******************************************************************************
* Configures audio codes's internal PLL. With MCLK = 8 MHz it configures the
* PLL for a VCO frequency = 49.152 MHz, and an audio sample rate of 48 KHz.
*
* @param none.
*
* @return none.
*****************************************************************************/
void AudioPllConfig() {
unsigned char u8TxData[8], u8RxData[6];
AudioWriteToReg(R0_CLOCK_CONTROL, 0x0E);
// Write 6 bytes to R1
u8TxData[0] = 0x40;
u8TxData[1] = 0x02;
u8TxData[2] = 0x02; // byte 1
u8TxData[3] = 0x71; // byte 2
u8TxData[4] = 0x02; // byte 3
u8TxData[5] = 0x3C; // byte 4
u8TxData[6] = 0x21; // byte 5
u8TxData[7] = 0x01; // byte 6
XIicPs_MasterSendPolled(&Iic, u8TxData, 8, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&Iic));
// Poll PLL Lock bit
u8TxData[0] = 0x40;
u8TxData[1] = 0x02;
do {
XIicPs_MasterSendPolled(&Iic, u8TxData, 2, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&Iic));
XIicPs_MasterRecvPolled(&Iic, u8RxData, 6, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&Iic));
}
while((u8RxData[5] & 0x02) == 0);
AudioWriteToReg(R0_CLOCK_CONTROL, 0x0F);//COREN
}
/*
* IIC Write 2
*/
int iic_write2(XIicPs *IicPs, u8 Address, u8 Register, u8 Data) {
u8 WriteBuffer[2];
int Status;
/*
* A temporary write buffer must be used which contains both the address
* and the data to be written, put the address in first
*/
WriteBuffer[0] = Register;
WriteBuffer[1] = Data;
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(IicPs)) {
/* NOP */
//sleep(1);
}
/*
* Send the buffer using the IIC and check for errors.
*/
Status = XIicPs_MasterSendPolled(IicPs, WriteBuffer, 2, Address);
if (Status != XST_SUCCESS) {
myprintf("XIicPs_MasterSendPolled error!\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
* This function read data from the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param RdBuffer is the buffer into which data read
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->ReceiveComplete = FALSE;
/*
* Receive the Data.
*/
XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
while (I2cLibPtr->ReceiveComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cReadData: Failed due to errors %d\n\r",
I2cLibPtr->TotalErrorCount);
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr))
;
return XST_SUCCESS;
}
/**
* This function writes a buffer of data to the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param WrBuffer is the buffer which contains data to be written
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->TransmitComplete = FALSE;
/*
* Send the Data.
*/
XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
/*
* Wait for the entire buffer to be sent, letting the interrupt
* processing work in the background, this function may get
* locked up in this loop if the interrupts are not working
* correctly.
*/
while (I2cLibPtr->TransmitComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cWriteData: Failed due to errors\n\r");
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr));
return XST_SUCCESS;
}
int i2c_write_await(XIicPs* i2c_dev, uint8_t dev_id, uint8_t* buffer, int size)
{
int rv = 0;
rv = i2c_write(i2c_dev, dev_id, buffer, size);
if(rv != XST_SUCCESS)
return rv;
while(XIicPs_BusIsBusy(i2c_dev));
return XST_SUCCESS;
}
/******************************************************************************
* Function to write one byte (8-bits) to one of the registers from the audio
* controller.
*
* @param u8RegAddr is the LSB part of the register address (0x40xx).
* @param u8Data is the data byte to write.
*
* @return none.
*****************************************************************************/
void AudioWriteToReg(unsigned char u8RegAddr, unsigned char u8Data) {
unsigned char u8TxData[3];
u8TxData[0] = 0x40;
u8TxData[1] = u8RegAddr;
u8TxData[2] = u8Data;
XIicPs_MasterSendPolled(&Iic, u8TxData, 3, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&Iic));
}
/* ---------------------------------------------------------------------------- *
* ADAU1761_RegWrite *
* ---------------------------------------------------------------------------- *
* Function to write one byte (8-bits) to one of the registers from the audio
* controller via I2C --
* ---------------------------------------------------------------------------- */
void adau1761_regWrite(tAdau1761 *pThis, unsigned char u8RegAddr, unsigned char u8Data) {
unsigned char u8TxData[3];
u8TxData[0] = 0x40;
u8TxData[1] = u8RegAddr;
u8TxData[2] = u8Data;
XIicPs_MasterSendPolled(&pThis->Iic, u8TxData, 3, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&pThis->Iic));
}
int IicSendCommand(u8* message, int messageSize)
{
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
int Status, i;
Status = XIicPs_MasterSendPolled(&Iic, message, messageSize, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS)
{
// failed at this point..
// do something about it
return -1;
}
return 0;
}
/*
* IIC Burst Write
*/
int iic_burstWrite(XIicPs *IicPs, u8 Address, u8 Register, u32 length,
unsigned char* Data) {
u8 WriteBuffer[length + 1];
int Status;
int cnt = 0;
/*
* A temporary write buffer must be used which contains both the address
* and the data to be written, put the address in first
*/
WriteBuffer[0] = Register;
memcpy(&WriteBuffer[1], Data, length);
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(IicPs)) {
/* NOP */
usleep(100);
cnt++;
if (cnt > IIC_TIMEOUT) {
busy = BOOL_TRUE;
return XST_DEVICE_BUSY;
}
}
/*
* Send the buffer using the IIC and check for errors.
*/
Status = XIicPs_MasterSendPolled(IicPs, WriteBuffer, length + 1, Address);
if (Status != XST_SUCCESS) {
#ifdef DEBUG
//Get Timestamp
unsigned long timestamp_ms = getElapsedRuntimeUS()/1000;
myprintf("XIicPs_MasterSendPolled error at %ds!\n\r", timestamp_ms);
#endif
return Status;
}
//print and return
//myprintf("[iic_burstWrite] 0x%02X(0x%02X)=0x%X\n\r", Address, Register, *Data);
return XST_SUCCESS;
}
/*
* This function prepares a device to transfers as a master.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @param Role specifies whether the device is sending or receiving.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if bus is busy.
*
* @note Interrupts are always disabled, device which needs to use
* interrupts needs to setup interrupts after this call.
*
****************************************************************************/
static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
{
u32 ControlReg;
u32 BaseAddr;
u32 EnabledIntr = 0x0;
Xil_AssertNonvoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
/*
* Only check if bus is busy when repeated start option is not set.
*/
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
if (XIicPs_BusIsBusy(InstancePtr)) {
return XST_FAILURE;
}
}
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) {
ControlReg |= XIICPS_CR_RD_WR_MASK;
EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
}else {
ControlReg &= ~XIICPS_CR_RD_WR_MASK;
}
EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
return XST_SUCCESS;
}
/*
* IIC Write 1
*/
int iic_write1(XIicPs *IicPs, u8 Address, u8 Data) {
int Status;
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(IicPs)) {
/* NOP */
}
/*
* Send the buffer using the IIC and check for errors.
*/
Status = XIicPs_MasterSendPolled(IicPs, &Data, 1, Address);
if (Status != XST_SUCCESS) {
myprintf("XIicPs_MasterSendPolled error!\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* IIC Read 1
*/
int iic_read1(XIicPs *IicPs, u8 Address, u8 *Data) {
int Status;
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(IicPs)) {
/* NOP */
}
/*
* Receive the data.
*/
Status = XIicPs_MasterRecvPolled(IicPs, Data, 1, Address);
if (Status != XST_SUCCESS) {
myprintf("XIicPs_MasterRecvPolled error!\n\r");
return XST_FAILURE;
}
// myprintf("[iic_read1] 0x%02X=0x%02X\n\r", Address, *Data);
return XST_SUCCESS;
}
/*
* This function prepares a device to transfers as a master.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @param Role specifies whether the device is sending or receiving.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if bus is busy.
*
* @note Interrupts are always disabled, device which needs to use
* interrupts needs to setup interrupts after this call.
*
****************************************************************************/
static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
{
u32 ControlReg;
u32 BaseAddr;
Xil_AssertNonvoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
/*
* Only check if bus is busy when repeated start option is not set.
*/
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
return (s32)XST_FAILURE;
}
}
/*
* Set up master, AckEn, nea and also clear fifo.
*/
ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) {
ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
}else {
ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
}
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr);
return (s32)XST_SUCCESS;
}
/**
*
* This function does a minimal test on the Iic device and driver as a
* design example. The purpose of this function is to illustrate
* how to use the XIicPs driver.
*
* This function sends data and expects to receive the same data through the IIC
* using the Aardvark test hardware.
*
* This function uses interrupt driver mode of the IIC.
*
* @param DeviceId is the Device ID of the IicPs Device and is the
* XPAR_<IICPS_instance>_DEVICE_ID value from xparameters.h
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note
*
* This function contains an infinite loop such that if interrupts are not
* working it may never return.
*
*******************************************************************************/
int IicPsMasterIntrExample(u16 DeviceId)
{
int Status;
XIicPs_Config *Config;
int Index;
int tmp;
int BufferSizes[NUMBER_OF_SIZES] = {1, 2, 19, 31, 32, 33, 62, 63, 64,
65, 66, 94, 95, 96, 97, 98, 99, 250};
/*
* Initialize the IIC driver so that it's ready to use
* Look up the configuration in the config table, then initialize it.
*/
Config = XIicPs_LookupConfig(DeviceId);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XIicPs_CfgInitialize(&Iic, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built correctly.
*/
Status = XIicPs_SelfTest(&Iic);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the IIC to the interrupt subsystem such that interrupts can
* occur. This function is application specific.
*/
Status = SetupInterruptSystem(&Iic);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setup the handlers for the IIC that will be called from the
* interrupt context when data has been sent and received, specify a
* pointer to the IIC driver instance as the callback reference so
* the handlers are able to access the instance data.
*/
XIicPs_SetStatusHandler(&Iic, (void *) &Iic, Handler);
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(&Iic, IIC_SCLK_RATE);
/*
* Initialize the send buffer bytes with a pattern to send and the
* the receive buffer bytes to zero to allow the receive data to be
* verified.
*/
for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) {
SendBuffer[Index] = (Index % TEST_BUFFER_SIZE);
RecvBuffer[Index] = 0;
}
for(Index = 0; Index < NUMBER_OF_SIZES; Index++) {
/* Wait for bus to become idle
*/
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
SendComplete = FALSE;
/*
* Send the buffer, errors are reported by TotalErrorCount.
*/
XIicPs_MasterSend(&Iic, SendBuffer, BufferSizes[Index],
IIC_SLAVE_ADDR);
/*
* Wait for the entire buffer to be sent, letting the interrupt
* processing work in the background, this function may get
* locked up in this loop if the interrupts are not working
* correctly.
*/
while (!SendComplete) {
if (0 != TotalErrorCount) {
return XST_FAILURE;
}
}
/*
* Wait bus activities to finish.
*/
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
/*
* Receive data from slave, errors are reported through
* TotalErrorCount.
*/
RecvComplete = FALSE;
XIicPs_MasterRecv(&Iic, RecvBuffer, BufferSizes[Index],
IIC_SLAVE_ADDR);
while (!RecvComplete) {
if (0 != TotalErrorCount) {
return XST_FAILURE;
}
}
/* Check for received data.
*/
for(tmp = 0; tmp < BufferSizes[Index]; tmp ++) {
/*
* Aardvark as slave can only set up to 64 bytes for
* output.
*/
if (RecvBuffer[tmp] != tmp % 64) {
return XST_FAILURE;
}
}
}
return XST_SUCCESS;
}
/**
* This function is used to perform GT configuration for ZCU102 board.
* It also provides reset to GEM, enables FMC ADJ
*
* @param none
*
* @return
* - XFSBL_SUCCESS for successful configuration
* - errors as mentioned in xfsbl_error.h
*
*****************************************************************************/
static s32 XFsbl_BoardConfig(void)
{
u8 WriteBuffer[BUF_LEN] = {0};
XIicPs_Config *I2c0CfgPtr;
s32 Status = XFSBL_SUCCESS;
u32 ICMCfg0;
u32 ICMCfg1;
/* Initialize the IIC0 driver so that it is ready to use */
I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
if (I2c0CfgPtr == NULL) {
Status = XFSBL_ERROR_I2C_INIT;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_INIT\r\n");
goto END;
}
Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
I2c0CfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
Status = XFSBL_ERROR_I2C_INIT;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_INIT\r\n");
goto END;
}
/* Set the IIC serial clock rate */
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
/* Configure I/O pins as Output */
WriteBuffer[0] = CMD_CFG_0_REG;
WriteBuffer[1] = DATA_OUTPUT;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XFSBL_ERROR_I2C_WRITE;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_WRITE\r\n");
goto END;
}
/* Wait until bus is idle to start another transfer */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/*
* Deasserting I2C_MUX_RESETB
* And GEM3 Resetb
* Selecting lanes based on configuration
*/
WriteBuffer[0] = CMD_OUTPUT_0_REG;
/* Populate WriteBuffer[1] based on ICM_CFG configuration */
ICMCfg0 = XFsbl_In32(SERDES_ICM_CFG0) &
(SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK);
ICMCfg1 = XFsbl_In32(SERDES_ICM_CFG1) &
(SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK);
if ((ICMCfg0 == ICM_CFG0_PCIE_DP) && (ICMCfg1 == ICM_CFG1_USB_SATA))
{
/* gt1110 */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_1110_CFG;
}
else
if ((ICMCfg0 == ICM_CFG0_DP_DP) && (ICMCfg1 == ICM_CFG1_USB_SATA))
{
/* gt1111 */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_1111_CFG;
}
else
if ((ICMCfg0 == ICM_CFG0_PCIE_PCIE) && (ICMCfg1 == ICM_CFG1_USB_SATA))
{
/* gt1100 */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_1100_CFG;
}
else
{
/* gt0000 or no GT configuration */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
}
/* Send the Data */
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XFSBL_ERROR_I2C_WRITE;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_WRITE\r\n");
goto END;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/* Change the IIC serial clock rate */
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_I2CMUX);
/* Set I2C Mux for channel-2 (MAXIM_PMBUS) */
WriteBuffer[0] = CMD_CH_2_REG;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 1, PCA9544A_ADDR);
if (Status != XST_SUCCESS) {
Status = XFSBL_ERROR_I2C_WRITE;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_WRITE\r\n");
goto END;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/* Enable Regulator (FMC ADJ) */
WriteBuffer[0] = CMD_ON_OFF_CFG;
WriteBuffer[1] = ON_OFF_CFG_VAL;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, MAX15301_ADDR);
if (Status != XST_SUCCESS) {
Status = XFSBL_ERROR_I2C_WRITE;
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_I2C_WRITE\r\n");
goto END;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
XFsbl_Printf(DEBUG_INFO,"Board Configuration successful \n\r");
END:
return Status;
}
int i2c_recv(XIicPs* i2c_dev, uint8_t dev_id, uint8_t* buffer, int buf_max)
{
while(XIicPs_BusIsBusy(i2c_dev));
return XIicPs_MasterRecvPolled(i2c_dev, buffer, buf_max, dev_id);
}
/**
*
* This function simply initializes the iic component of the board
*
*******************************************************************************/
int IicInit()
{
xil_printf("Initialize iic component\r\n");
int Status;
XIicPs_Config *Config;
int Index;
/*
* Initialize the IIC driver so that it's ready to use
* Look up the configuration in the config table,
* then initialize it.
*/
Config = XIicPs_LookupConfig(IIC_DEVICE_ID);
if (NULL == Config)
{
return XST_FAILURE;
}
Status = XIicPs_CfgInitialize(&Iic, Config, Config->BaseAddress);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built correctly.
*/
Status = XIicPs_SelfTest(&Iic);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(&Iic, IIC_SCLK_RATE);
/*
* Initialize the send buffer bytes with a pattern to send and the
* the receive buffer bytes to zero to allow the receive data to be
* verified.
*/
for (Index = 0; Index < RECV_BUFFER_SIZE; Index++)
{
RecvBuffer[Index] = 0;
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
// Wait until slave is ready to communicate
Status = XIicPs_MasterRecvPolled(&Iic, RecvBuffer, RECV_BUFFER_SIZE, IIC_SLAVE_ADDR);
while (Status != XST_SUCCESS)
{
Status = XIicPs_MasterRecvPolled(&Iic, RecvBuffer, RECV_BUFFER_SIZE, IIC_SLAVE_ADDR);
usleep(100000);
}
xil_printf("iic component initialized and ready to request data!\r\n");
return XST_SUCCESS;
}
int i2c_write(XIicPs* i2c_dev, uint8_t dev_id, uint8_t* buffer, int size)
{
while(XIicPs_BusIsBusy(i2c_dev));
return XIicPs_MasterSendPolled(i2c_dev, buffer, size, dev_id);
}
/* ---------------------------------------------------------------------------- *
* AudioCodec_Config() *
* ---------------------------------------------------------------------------- *
* Configures audio codes's internal PLL. With MCLK = 10 MHz it configures the
* PLL for a VCO frequency = 49.152 MHz, and an audio sample rate of 48 KHz.
* ---------------------------------------------------------------------------- */
void adau1761_codec_init(tAdau1761 *pThis) {
unsigned char u8TxData[8], u8RxData[6];
// Disable Core Clock
adau1761_regWrite(pThis, R0_CLOCK_CONTROL, 0x0E);
/* MCLK = 12.288 MHz
R = 0100 = 4
PLL required output = 1024x48 KHz
(PLLout) = 49.152 MHz
PLLout/MCLK = 49.152 MHz/12.288 MHz
= 4 */
// Write 6 bytes to R1 @ register address 0x4002
u8TxData[0] = 0x40; // Register write address [15:8]
u8TxData[1] = 0x02; // Register write address [7:0]
u8TxData[2] = 0x00; // byte 6 - M[15:8]
u8TxData[3] = 0x00; // byte 5 - M[7:0]
u8TxData[4] = 0x00; // byte 4 - N[15:8]
u8TxData[5] = 0x00; // byte 3 - N[7:0]
u8TxData[6] = 0x20; // byte 2 - 7 = reserved, bits 6:3 = R[3:0], 2:1 = X[1:0], 0 = PLL operation mode
u8TxData[7] = 0x01; // byte 1 - 7:2 = reserved, 1 = PLL Lock, 0 = Core clock enable
// Write bytes to PLL Control register R1 @ 0x4002
XIicPs_MasterSendPolled(&(pThis->Iic), u8TxData, 8, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&pThis->Iic));
// Register address set: 0x4002
u8TxData[0] = 0x40;
u8TxData[1] = 0x02;
// Poll PLL Lock bit
do {
XIicPs_MasterSendPolled(&pThis->Iic, u8TxData, 2, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&pThis->Iic));
XIicPs_MasterRecvPolled(&pThis->Iic, u8RxData, 6, (IIC_SLAVE_ADDR >> 1));
while(XIicPs_BusIsBusy(&pThis->Iic));
}
while((u8RxData[5] & 0x02) == 0); // while not locked
adau1761_regWrite(pThis, R0_CLOCK_CONTROL, 0x0F); // 1111
// bit 3: CLKSRC = PLL Clock input
// bits 2:1: INFREQ = 1024 x fs
// bit 0: COREN = Core Clock enabled
//Initialize ADAU1761 control ports. (Refer to Page 51 of the ADAU1761 datasheet)
adau1761_regWrite(pThis, R16_SERIAL_PORT_CONTROL_1, 0x00);
adau1761_regWrite(pThis, R17_CONVERTER_CONTROL_0, 0x05);//48 KHz
adau1761_regWrite(pThis, R64_SERIAL_PORT_SAMPLING_RATE, 0x05);//48 KHz
adau1761_regWrite(pThis, R19_ADC_CONTROL, 0x13);
adau1761_regWrite(pThis, R36_DAC_CONTROL_0, 0x03);
adau1761_regWrite(pThis, R35_PLAYBACK_POWER_MANAGEMENT, 0x03);
adau1761_regWrite(pThis, R58_SERIAL_INPUT_ROUTE_CONTROL, 0x01);
adau1761_regWrite(pThis, R59_SERIAL_OUTPUT_ROUTE_CONTROL, 0x01);
adau1761_regWrite(pThis, R65_CLOCK_ENABLE_0, 0x7F);
adau1761_regWrite(pThis, R66_CLOCK_ENABLE_1, 0x03);
adau1761_regWrite(pThis, R4_RECORD_MIXER_LEFT_CONTROL_0, 0x01);
adau1761_regWrite(pThis, R5_RECORD_MIXER_LEFT_CONTROL_1, 0x05);
adau1761_regWrite(pThis, R6_RECORD_MIXER_RIGHT_CONTROL_0, 0x01);
adau1761_regWrite(pThis, R7_RECORD_MIXER_RIGHT_CONTROL_1, 0x05);
adau1761_regWrite(pThis, R22_PLAYBACK_MIXER_LEFT_CONTROL_0, 0x21);
adau1761_regWrite(pThis, R24_PLAYBACK_MIXER_RIGHT_CONTROL_0, 0x41);
adau1761_regWrite(pThis, R26_PLAYBACK_LR_MIXER_LEFT_LINE_OUTPUT_CONTROL, 0x03);
adau1761_regWrite(pThis, R27_PLAYBACK_LR_MIXER_RIGHT_LINE_OUTPUT_CONTROL, 0x09);
adau1761_regWrite(pThis, R29_PLAYBACK_HEADPHONE_LEFT_VOLUME_CONTROL, 0xE7);
adau1761_regWrite(pThis, R30_PLAYBACK_HEADPHONE_RIGHT_VOLUME_CONTROL, 0xE7);
adau1761_regWrite(pThis, R31_PLAYBACK_LINE_OUTPUT_LEFT_VOLUME_CONTROL, 0xE7);
adau1761_regWrite(pThis, R32_PLAYBACK_LINE_OUTPUT_RIGHT_VOLUME_CONTROL, 0xE7);
}
/**
* Returns a structure containing the position, heading and data read from sensors
* of the robot. The structure contains the parsed data requested by IIC from the
* slave board.
*/
robot_state IicGetRobotState()
{
int Status, Index;
// phase used for parsing the input taken from iic buffer
// 0 - positionX
// 1 - positionY
// 2 - headingAngle
// 3 - leftSensorX
// 4 - leftSensorY
// 5 - frontSensorX
// 6 - frontSensorY
// 7 - rightSensorX
// 8 - rightSensorY
int Phase = 0;
int Sign = 1;
robot_state Result = IicGetInvalidRobotState();
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
Status = XIicPs_MasterRecvPolled(&Iic, RecvBuffer, RECV_BUFFER_SIZE, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
// failed at this point..
// do something about it
return Result;
}
/*
* Verify received data is correct.
*/
char CurrentChar;
int CurrentNumber = 0;
int StoreData = 0;
for (Index = 0; Index < RECV_BUFFER_SIZE; Index++)
{
StoreData = 0;
CurrentChar = RecvBuffer[Index];
switch (CurrentChar)
{
case '-':
Sign = -1;
break;
case ',':
CurrentNumber *= Sign;
StoreData = 1;
break;
default:
CurrentNumber = CurrentNumber * 10 + (CurrentChar - '0');
break;
}
if (StoreData == 1)
{
switch(Phase)
{
case 0:
Result.numberOfCommands = CurrentNumber;
break;
case 1:
Result.vacuumStatus = CurrentNumber;
break;
case 2:
Result.sensorsServoStatus = CurrentNumber;
break;
case 3:
Result.position.x = CurrentNumber;
break;
case 4:
Result.position.y = CurrentNumber;
break;
case 5:
Result.headingAngle = CurrentNumber;
break;
case 6:
Result.leftSensor.x = CurrentNumber;
break;
case 7:
Result.leftSensor.y = CurrentNumber;
break;
case 8:
Result.frontSensor.x = CurrentNumber;
break;
case 9:
Result.frontSensor.y = CurrentNumber;
break;
case 10:
Result.rightSensor.x = CurrentNumber;
break;
case 11:
Result.rightSensor.y = CurrentNumber;
return Result;
break;
default:
break;
}
CurrentNumber = 0;
Phase ++;
Sign = 1;
}
}
return Result;
}
/**
*
* This function does polled mode transfer in slave mode. It first sends to
* master then receives.
*
* @param DeviceId is the Device ID of the IicPs Device and is the
* XPAR_<IICPS_instance>_DEVICE_ID value from xparameters.h
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
*******************************************************************************/
int IicPsSlavePolledExample(u16 DeviceId)
{
int Status;
XIicPs_Config *Config;
int Index;
/*
* Initialize the IIC driver so that it's ready to use
* Look up the configuration in the config table,
* then initialize it.
*/
Config = XIicPs_LookupConfig(DeviceId);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XIicPs_CfgInitialize(&Iic, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built correctly.
*/
Status = XIicPs_SelfTest(&Iic);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIicPs_SetupSlave(&Iic, IIC_SLAVE_ADDR);
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(&Iic, IIC_SCLK_RATE);
/*
* Initialize the send buffer bytes with a pattern to send and the
* the receive buffer bytes to zero to allow the receive data to be
* verified.
*/
for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) {
SendBuffer[Index] = (Index % TEST_BUFFER_SIZE);
RecvBuffer[Index] = 0;
}
/*
* Send the buffer using the IIC and ignore the number of bytes sent
* as the return value since we are using it in interrupt mode.
*/
Status = XIicPs_SlaveSendPolled(&Iic, SendBuffer,
TEST_BUFFER_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XIicPs_BusIsBusy(&Iic)) {
/* NOP */
}
Status = XIicPs_SlaveRecvPolled(&Iic, RecvBuffer,
TEST_BUFFER_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Verify received data is correct.
*/
for(Index = 0; Index < TEST_BUFFER_SIZE; Index ++) {
if (RecvBuffer[Index] != Index % TEST_BUFFER_SIZE) {
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
/*
* IIC Read 2
*/
int iic_read2(XIicPs *IicPs, u8 Address, u8 Register, u8 *Data, int ByteCount) {
int Status;
int cnt = 0;
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(IicPs)) {
usleep(100);
//Timeout
cnt++;
if (cnt > IIC_TIMEOUT) {
busy = BOOL_TRUE;
return XST_DEVICE_BUSY;
}
}
/*
* Set the IIC Repeated Start option.
*/
Status = XIicPs_SetOptions(IicPs, XIICPS_REP_START_OPTION);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Send the buffer using the IIC and check for errors.
*/
Status = XIicPs_MasterSendPolled(IicPs, &Register, 1, Address);
if (Status != XST_SUCCESS) {
#ifdef DEBUG
//Get Timestamp
unsigned long timestamp_ms = getElapsedRuntimeUS()/1000;
myprintf("XIicPs_MasterSendPolled error at %d ms!\n\r", timestamp_ms);
#endif
return Status;
}
/*
* Receive the data.
*/
Status = XIicPs_MasterRecvPolled(IicPs, Data, ByteCount, Address);
if (Status != XST_SUCCESS) {
#ifdef DEBUG
//Get Timestamp
unsigned long timestamp_ms = getElapsedRuntimeUS()/1000;
myprintf("XIicPs_MasterRecvPolled error at %d ms!\n\r", timestamp_ms);
#endif
return Status;
}
/*
* Clear the IIC Repeated Start option.
*/
Status = XIicPs_ClearOptions(IicPs, XIICPS_REP_START_OPTION);
if (Status != XST_SUCCESS) {
return Status;
}
//myprintf("[iic_read2] 0x%02X(0x%02X)=0x%X\n\r", Address, Register, *Data);
return XST_SUCCESS;
}