static void
fifo_error_handler(xaxiemacif_s *xaxiemacif, u32_t pending_intr)
{
XLlFifo *llfifo = &xaxiemacif->axififo;
if (pending_intr & XLLF_INT_RPURE_MASK) {
print("llfifo: Rx under-read error");
}
if (pending_intr & XLLF_INT_RPORE_MASK) {
print("llfifo: Rx over-read error");
}
if (pending_intr & XLLF_INT_RPUE_MASK) {
print("llfifo: Rx fifo empty");
}
if (pending_intr & XLLF_INT_TPOE_MASK) {
print("llfifo: Tx fifo overrun");
}
if (pending_intr & XLLF_INT_TSE_MASK) {
print("llfifo: Tx length mismatch");
}
/* Reset the tx or rx side of the fifo as needed */
if (pending_intr & XLLF_INT_RXERROR_MASK) {
XLlFifo_IntClear(llfifo, XLLF_INT_RRC_MASK);
XLlFifo_RxReset(llfifo);
}
if (pending_intr & XLLF_INT_TXERROR_MASK) {
XLlFifo_IntClear(llfifo, XLLF_INT_TRC_MASK);
XLlFifo_TxReset(llfifo);
}
}
static void
xllfifo_intr_handler(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
XLlFifo *llfifo = &xaxiemacif->axififo;
u32_t pending_fifo_intr = XLlFifo_IntPending(llfifo);
#ifdef OS_IS_FREERTOS
xInsideISR++;
#endif
while (pending_fifo_intr) {
if (pending_fifo_intr & XLLF_INT_RC_MASK) {
/* receive interrupt */
XLlFifo_IntClear(llfifo, XLLF_INT_RC_MASK);
xllfifo_recv_handler(xemac);
} else if (pending_fifo_intr & XLLF_INT_TC_MASK) {
/* tx intr */
XLlFifo_IntClear(llfifo, XLLF_INT_TC_MASK);
} else {
XLlFifo_IntClear(llfifo, XLLF_INT_ALL_MASK &
~(XLLF_INT_RC_MASK |
XLLF_INT_TC_MASK));
fifo_error_handler(xaxiemacif, pending_fifo_intr);
}
pending_fifo_intr = XLlFifo_IntPending(llfifo);
}
#ifdef OS_IS_FREERTOS
xInsideISR--;
#endif
}
static void
xllfifo_intr_handler(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
XLlFifo *llfifo = &xlltemacif->llfifo;
u32_t pending_fifo_intr = XLlFifo_IntPending(llfifo);
while (pending_fifo_intr) {
if (pending_fifo_intr & XLLF_INT_RC_MASK) {
/* receive interrupt */
XLlFifo_IntClear(llfifo, XLLF_INT_RC_MASK);
xllfifo_recv_handler(xlltemacif);
} else if (pending_fifo_intr & XLLF_INT_TC_MASK) {
/* tx intr */
XLlFifo_IntClear(llfifo, XLLF_INT_TC_MASK);
} else {
XLlFifo_IntClear(llfifo, XLLF_INT_ALL_MASK &
~(XLLF_INT_RC_MASK |
XLLF_INT_TC_MASK));
fifo_error_handler(xlltemacif, pending_fifo_intr);
}
pending_fifo_intr = XLlFifo_IntPending(llfifo);
}
}
XStatus
init_ll_fifo(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xlltemacif->llfifo,
XLlTemac_LlDevBaseAddress(&xlltemacif->lltemac));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
#if NO_SYS
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xlltemacif->lltemac.Config.LLFifoIntr)
| (1 << xlltemacif->lltemac.Config.TemacIntr);
/* set new mask */
XIntc_mEnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
enable_interrupt(xlltemacif->lltemac.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xlltemacif->lltemac.Config.LLFifoIntr);
#endif
return 0;
}
/**
*
* This is the interrupt handler for the fifo it checks for the type of interrupt
* and proceeds according to it.
*
* @param InstancePtr is a reference to the Fifo device instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void FifoHandler(XLlFifo *InstancePtr)
{
u32 Pending;
Pending = XLlFifo_IntPending(InstancePtr);
while (Pending) {
if (Pending & XLLF_INT_RC_MASK) {
FifoRecvHandler(InstancePtr);
XLlFifo_IntClear(InstancePtr, XLLF_INT_RC_MASK);
}
else if (Pending & XLLF_INT_TC_MASK) {
FifoSendHandler(InstancePtr);
}
else if (Pending & XLLF_INT_ERROR_MASK){
FifoErrorHandler(InstancePtr, Pending);
XLlFifo_IntClear(InstancePtr, XLLF_INT_ERROR_MASK);
} else {
XLlFifo_IntClear(InstancePtr, Pending);
}
Pending = XLlFifo_IntPending(InstancePtr);
}
}
/**
* This functions polls the Tx status and waits for an indication that a frame
* has been transmitted successfully or a transmit related error has occurred.
* If an error is reported, it handles all the possible error conditions.
*
* @param None.
*
* @return Status is the status of the last call to the
* XLlTemac_FifoQuerySendStatus() function.
*
* @note None.
*
******************************************************************************/
int TemacPollForTxStatus(void)
{
int Status = XST_NO_DATA;
int Attempts = 100000; /* Number of attempts to get status before giving
up */
/*
* Wait for transmit complete indication
*/
do {
if (--Attempts <= 0)
break; /* Give up? */
if (XLlFifo_Status(&FifoInstance) & XLLF_INT_TC_MASK) {
XLlFifo_IntClear(&FifoInstance, XLLF_INT_TC_MASK);
Status = XST_SUCCESS;
}
if (XLlFifo_Status(&FifoInstance) & XLLF_INT_ERROR_MASK) {
Status = XST_FIFO_ERROR;
}
} while (Status == XST_NO_DATA);
switch (Status) {
case XST_SUCCESS: /* Frame sent without error */
case XST_NO_DATA: /* Timeout */
break;
case XST_FIFO_ERROR:
TemacUtilErrorTrap("FIFO error");
TemacResetDevice();
break;
default:
TemacUtilErrorTrap("Driver returned unknown transmit status");
break;
}
return (Status);
}
/**
*
* This function demonstrates the usage AXI FIFO
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the Axi FIFO Device.
* - Transmit the data
* - Receive the data from fifo
* - Compare the data
* - Return the result
*
* @param InstancePtr is a pointer to the instance of the
* XLlFifo component.
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int Error;
Status = XST_SUCCESS;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}
/* Transmit the Data Stream */
Status = TxSend(InstancePtr, SourceBuffer);
if (Status != XST_SUCCESS){
xil_printf("Transmisson of Data failed\n\r");
return XST_FAILURE;
}
/* Revceive the Data Stream */
Status = RxReceive(InstancePtr, DestinationBuffer);
if (Status != XST_SUCCESS){
xil_printf("Receiving data failed");
return XST_FAILURE;
}
Error = 0;
/* Compare the data send with the data received */
xil_printf(" Comparing data ...\n\r");
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
Error = 1;
break;
}
}
if (Error != 0){
return XST_FAILURE;
}
return Status;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
#ifdef OS_IS_FREERTOS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr,
AXIETH_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
#ifdef OS_IS_XILKERNEL
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#endif
#endif
#endif
return 0;
}
/*
*
* This is the transfer Complete Interrupt handler function.
*
* This clears the trasmit complete interrupt and set the done flag.
*
* @param InstancePtr is a pointer to Instance of AXI FIFO device.
*
* @return None
*
* @note None
*
******************************************************************************/
static void FifoSendHandler(XLlFifo *InstancePtr)
{
XLlFifo_IntClear(InstancePtr, XLLF_INT_TC_MASK);
Done = 1;
}
/**
*
* This function demonstrates the usage of AXI FIFO
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the Axi FIFO Device.
* - Set up the interrupt handler for fifo
* - Transmit the data
* - Compare the data
* - Return the result
*
* @param InstancePtr is a pointer to the instance of the
* XLlFifo instance.
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int err;
Status = XST_SUCCESS;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}
/*
* Connect the Axi Streaming FIFO to the interrupt subsystem such
* that interrupts can occur. This function is application specific.
*/
Status = SetupInterruptSystem(&Intc, InstancePtr, FIFO_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
XLlFifo_IntEnable(InstancePtr, XLLF_INT_ALL_MASK);
Done = 0;
/* Transmit the Data Stream */
Status = TxSend(InstancePtr, SourceBuffer);
if (Status != XST_SUCCESS){
xil_printf("Transmission of Data failed\n\r");
return XST_FAILURE;
}
while(!Done);
/* Check for errors */
if(Error) {
xil_printf("Errors in the FIFO\n\r");
return XST_FAILURE;
}
err = 0;
/* Compare the data sent with the data received */
xil_printf("Comparing data...\n\r");
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
err = 1;
break;
}
}
if (err != 0){
return XST_FAILURE;
}
DisableIntrSystem(&Intc, FIFO_INTR_ID);
return Status;
}
/**
*
* This function demonstrates the usage Traffic Generator
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the AXI Traffic Generator device
* - Initialize the Streaming FIFO device
* - Set the Desired Transfer Count and Transfer Length
* - Enable the Traffic Genration on the Core
* - Check for the Streaming data on the FIFO
* - Return test status and exit
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
*
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId)
{
XTrafGen_Config *Config;
int Status = XST_SUCCESS;
u32 Len;
u32 TransferCnt;
u32 AtgPacket;
u32 FifoOcy;
u32 FifoLen;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XTrafGen_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XTrafGen_CfgInitialize(InstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Streaming Mode */
if(InstancePtr->OperatingMode != XTG_MODE_STREAMING) {
return XST_FAILURE;
}
/* Initialize the Fifo Instance */
XLlFifo_Initialize(&XLlFifoInstance , STR_FIFO0_ADDR);
Status = XLlFifo_Status(&XLlFifoInstance);
XLlFifo_IntClear(&XLlFifoInstance,0xffffffff);
Status = XLlFifo_Status(&XLlFifoInstance);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(&XLlFifoInstance));
return XST_FAILURE;
}
/*
* Set the Required trasaction length
* and required transaction count
*/
XTrafGen_ResetStreamingRandomLen(InstancePtr);
XTrafGen_SetStreamingTransLen(InstancePtr , 3);
XTrafGen_SetStreamingTransCnt(InstancePtr , 2);
Len = XTrafGen_GetStreamingTransLen(InstancePtr);
TransferCnt = XTrafGen_GetStreamingTransCnt(InstancePtr);
/*
* Calculate the ATG data that is sent on the
* CORE when Streaming is Enabled
*/
AtgPacket = (Len +1) * TransferCnt;
/* Enable the traffic genration */
XTrafGen_StreamEnable(InstancePtr);
FifoOcy = XLlFifo_iRxOccupancy(&XLlFifoInstance);
if(FifoOcy != AtgPacket) {
xil_printf("\n ERROR : Not received complete packets : 0x%x \t"
"Expected : 0x%x \n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance), AtgPacket);
return XST_FAILURE;
}
FifoLen = XLlFifo_iRxGetLen(&XLlFifoInstance);
if(FifoLen != (AtgPacket*4/TransferCnt)) {
xil_printf("\n ERROR : Not received complete bytes : 0x%x \t"
"Expected : 0x%x \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance),Len);
return XST_FAILURE;
}
while(XLlFifo_iRxGetLen(&XLlFifoInstance)) {
xil_printf("Recived packet DATA: 0x%x \n\r",
XLlFifo_RxGetWord(&XLlFifoInstance));
}
if(XLlFifo_iRxOccupancy(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RDFO is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance));
return XST_FAILURE;
}
if(XLlFifo_iRxGetLen(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RLR is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance));
return XST_FAILURE;
}
return XST_SUCCESS;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#endif
return 0;
}
