/* update 24/06/2003 : replace dcbz by dcbzl to get
the intended effect (Apple "fixed" dcbz)
unfortunately this cannot be used unless the assembler
knows about dcbzl ... */
static long check_dcbzl_effect(void)
{
register char *fakedata = av_malloc(1024);
register char *fakedata_middle;
register long zero = 0;
register long i = 0;
long count = 0;
if (!fakedata) {
return 0L;
}
fakedata_middle = (fakedata + 512);
XMemSet(fakedata, 0xFF, 1024);
/* below the constraint "b" seems to mean "Address base register"
in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
//__asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
__dcbz128(i,fakedata_middle);
for (i = 0; i < 1024 ; i ++) {
if (fakedata[i] == (char)0)
count++;
}
av_free(fakedata);
return count;
}
/* same as above, when dcbzl clear a whole 128B cache line
i.e. the PPC970 aka G5 */
static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
{
register int misal = ((unsigned long)blocks & 0x0000007f);
register int i = 0;
#if 1
if (misal) {
// we could probably also optimize this case,
// but there's not much point as the machines
// aren't available yet (2003-06-26)
//memset(blocks, 0, sizeof(DCTELEM)*6*64);
XMemSet(blocks, 0, sizeof(DCTELEM)*6*64);
}
else
for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
//__asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
__dcbz128(i,blocks);
}
#else
XMemSet(blocks, 0, sizeof(DCTELEM)*6*64);
#endif
POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
}
int BurnClearScreen()
{
const struct BurnDriver* pbd = pDriver[nBurnDrvSelect];
int w, h;
int condition = pbd->flags & BDF_ORIENTATION_VERTICAL;
unsigned char* pl;
int y;
w = condition ? pbd->nHeight : pbd->nWidth;
h = condition ? pbd->nWidth : pbd->nHeight;
w *= nBurnBpp;
// clear the screen to zero
for (pl = pBurnDraw, y = 0; y < h; pl += nBurnPitch, y++)
XMemSet(pl, 0x00, w);
return 0;
}