/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
void XPROGTarget_EnableTargetPDI(void)
{
IsSending = false;
/* Turn on clock */
sysclk_enable_peripheral_clock(USART_PDI_ID);
/* Set Tx and XCK as outputs, Rx as input */
gpio_configure_pin(PIN_PDIDTX_GPIO, PIN_PDIDTX_OUT_FLAGS);
gpio_configure_pin(PIN_PDIDRX_GPIO, PIN_PDIDRX_FLAGS);
gpio_configure_pin(PIN_PDIC_GPIO, PIN_PDIC_OUT_FLAGS);
delay_us(50);
/* Set DATA line high for at least 90ns to disable /RESET functionality */
gpio_set_pin_high(PIN_PDIDTX_GPIO);
delay_us(10);
/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
const sam_usart_opt_t usart_pdid_settings = {
PDI_BAUD_RATE,
US_MR_CHRL_8_BIT,
US_MR_PAR_EVEN,
US_MR_NBSTOP_2_BIT,
US_MR_CHMODE_NORMAL
};
usart_init_sync_master(USART_PDI, &usart_pdid_settings, sysclk_get_main_hz());
/* Turn on clock */
gpio_configure_pin(PIN_PDIC_GPIO, PIN_PDIC_USART_FLAGS);
/* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
XPROGTarget_SendIdle();
XPROGTarget_SendIdle();
}
/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
void XPROGTarget_EnableTargetPDI(void)
{
IsSending = false;
/* Set Tx and XCK as outputs, Rx as input */
DDRD |= (1 << 5) | (1 << 3);
DDRD &= ~(1 << 2);
/* Set DATA line high for at least 90ns to disable /RESET functionality */
PORTD |= (1 << 3);
_delay_us(1);
/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
/* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
XPROGTarget_SendIdle();
XPROGTarget_SendIdle();
}
/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
void XPROGTarget_EnableTargetTPI(void)
{
IsSending = false;
/* Set /RESET line low for at least 400ns to enable TPI functionality */
AUX_LINE_DDR |= AUX_LINE_MASK;
AUX_LINE_PORT &= ~AUX_LINE_MASK;
_delay_us(1);
/* Set Tx and XCK as outputs, Rx as input */
DDRD |= (1 << 5) | (1 << 3);
DDRD &= ~(1 << 2);
/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
/* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
XPROGTarget_SendIdle();
XPROGTarget_SendIdle();
}
