int zed_ali3_controller_demo_control(zed_ali3_controller_demo_t *pDemo)
{
// Fill frame stores with color bars
uint32_t frame, row, col;
uint32_t pixel;
interface_graphic_t graphic;
volatile uint32_t *pStorageMem = (uint32_t *)pDemo->uBaseAddr_MEM_FrameBuffer;
for (frame = 0; frame < pDemo->uNumFrames_FrameBuffer; frame++)
{
for (row = 0; row < pDemo->ali3_height; row++)
{
for (col = 0; col < pDemo->ali3_width; col++)
{
pixel = 0x00373333; // DarkGray
*pStorageMem++ = pixel;
}
}
}
// Set the demo mode to control.
pDemo->mode = control;
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Write the control panel background color data to the display.
pStorageMem = (uint32_t *)pDemo->uBaseAddr_MEM_FrameBuffer;
// Draw user interface to the display.
graphic.location_x = 21;
graphic.location_y = 20;
graphic.size_x = avnet_control_title_plate_width;
graphic.size_y = avnet_control_title_plate_height;
graphic.default_image_data = avnet_control_title_plate;
draw_image_data(pDemo, &graphic);
/*
* Draw the PL push button indicators.
*/
zed_ali3_controller_demo_button(pDemo, 0, pDemo->button0_state);
zed_ali3_controller_demo_button(pDemo, 1, pDemo->button1_state);
/*
* Draw the PL LED indicators.
*/
zed_ali3_controller_demo_led(pDemo, 0, pDemo->led0_state);
zed_ali3_controller_demo_led(pDemo, 1, pDemo->led1_state);
zed_ali3_controller_demo_led(pDemo, 2, pDemo->led2_state);
zed_ali3_controller_demo_led(pDemo, 3, pDemo->led3_state);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
return 0;
}
/******************************************************************************
* @brief Reads data from an ADC usign AXI_DMA core
*
* @param buf - Start address of the buffer where to store the read data
* @param size - Size in bytes of the data to read
* @return None
******************************************************************************/
void ReadAdcData(u32 buf, u32 size)
{
// program DMA engine
Xil_Out32((DMA_BASEADDR + 0x030), 0); // Clear dma operations
Xil_Out32((DMA_BASEADDR + 0x030), 1); // Enable Run bit
Xil_Out32((DMA_BASEADDR + 0x048), buf); // Configure DMA with the destination address
Xil_Out32((DMA_BASEADDR + 0x058), (size * 4 )); // Number of bites to be written
// program the DMA module in the ADC core
Xil_Out32((CF_BASEADDR + 0x040), 0x1); // Power up the core
Xil_Out32((CF_BASEADDR + 0x088), 0x7); // Reset overflows
Xil_Out32((CF_BASEADDR + 0x080), 0x0); // DMA stop
Xil_Out32((CF_BASEADDR + 0x084), size * 4 ); // Program the number of bytes to be captured
Xil_Out32((CF_BASEADDR + 0x080), 0x1); // Start capturing data
// Wait for data transfer to finish
do {
delay_ms(1);
}
while ((Xil_In32(CF_BASEADDR + 0x088) & 0x1) == 1);
if (Xil_In32(CF_BASEADDR + 0x088) != 0x00) {
xil_printf("overflow occured, capture may be corrupted\n\r");
xil_printf ("%x\n", Xil_In32(CF_BASEADDR + 0x088) );
}
Xil_DCacheFlush();
}
/***************************************************************************//**
* @brief Captures a specified number of samples from the ADC.
*
* @param size - number of bytes to read from the device
* @param address - capture start address
*
* @return None.
*******************************************************************************/
void adc_capture(u32 size, u32 address)
{
Xil_Out32((DMA_BASEADDR + 0x030), 0); // clear dma operations
Xil_Out32((DMA_BASEADDR + 0x030), 1); // enable dma operations
Xil_Out32((DMA_BASEADDR + 0x048), address); // capture start address
Xil_Out32((DMA_BASEADDR + 0x058), (size * 8)); // number of bytes
Xil_Out32((CF_BASEADDR + CF_REG_CAPTURE_CTRL),
CF_CAPTURE_CTRL_CAPTURE_START(0)); // capture disable
Xil_Out32((CF_BASEADDR + CF_REG_ADC_STATUS),
CF_ADC_STATUS_UNDERFLOW |
CF_ADC_STATUS_OVERFLOW |
CF_ADC_STATUS_BUSY); // clear status
Xil_Out32((CF_BASEADDR + CF_REG_DATA_MONITOR),
CF_DATA_MONITOR_PN_ERR |
CF_DATA_MONITOR_PN_SYNC |
CF_DATA_MONITOR_PN_OVER_RNG); // clear status
Xil_Out32((CF_BASEADDR + CF_REG_CAPTURE_CTRL),
CF_CAPTURE_CTRL_CAPTURE_START(1) |
CF_CAPTURE_CTRL_CAPTURE_COUNT(size)); // capture enable
do
{
delay_ms(1);
}
while ((Xil_In32(CF_BASEADDR + CF_REG_ADC_STATUS) & CF_ADC_STATUS_BUSY));
if ((Xil_In32(CF_BASEADDR + CF_REG_ADC_STATUS) & CF_ADC_STATUS_OVERFLOW))
{
xil_printf("overflow occurred, capture may be corrupted\n\r");
}
Xil_DCacheFlush();
}
int zed_ali3_controller_demo_cbars( zed_ali3_controller_demo_t *pDemo, int32u offset )
{
int32u frame, row, col;
int32u cbar, pixel;
volatile int32u *pStorageMem = (int32u *)pDemo->uBaseAddr_MEM_FrameBuffer;
for ( frame = 0; frame < pDemo->uNumFrames_FrameBuffer; frame++ )
{
for ( row = 0; row < pDemo->ali3_height; row++ )
{
for ( col = 0; col < pDemo->ali3_width; col++ )
{
cbar = (col * 8) / pDemo->ali3_width; // color bar = 0..7
cbar = (cbar + offset) % 8;
switch ( cbar )
{
case 0: pixel = 0x00000000; break; // Black
case 1: pixel = 0x00FF0000; break; // Red
case 2: pixel = 0x0000FF00; break; // Green
case 3: pixel = 0x000000FF; break; // Blue
case 4: pixel = 0x0000FFFF; break; // Cyan
case 5: pixel = 0x00FF00FF; break; // Purple
case 6: pixel = 0x00FFFF00; break; // Yellow
case 7: pixel = 0x00FFFFFF; break; // White
}
*pStorageMem++ = pixel;
}
}
}
// Wait for DMA to synchronize.
Xil_DCacheFlush();
return 0;
}
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
{
INTPTR *ptr;
INTPTR section;
u64 block_size;
/* if region is less than 4GB MMUTable level 2 need to be modified */
if(Addr < ADDRESS_LIMIT_4GB){
/* block size is 2MB for addressed < 4GB*/
block_size = BLOCK_SIZE_2MB;
section = Addr / block_size;
ptr = &MMUTableL2 + section;
}
/* if region is greater than 4GB MMUTable level 1 need to be modified */
else{
/* block size is 1GB for addressed > 4GB */
block_size = BLOCK_SIZE_1GB;
section = Addr / block_size;
ptr = &MMUTableL1 + section;
}
*ptr = (Addr & (~(block_size-1))) | attrib;
Xil_DCacheFlush();
mtcptlbi(ALLE3);
dsb(); /* ensure completion of the BP and TLB invalidation */
isb(); /* synchronize context on this processor */
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr & !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
int zed_ali3_controller_demo_logo(zed_ali3_controller_demo_t *pDemo)
{
// Fill frame stores with logo image data.
uint32_t frame, row, col;
uint32_t pixel;
volatile uint32_t *pStorageMem = (uint32_t *)pDemo->uBaseAddr_MEM_FrameBuffer;
for (frame = 0; frame < pDemo->uNumFrames_FrameBuffer; frame++)
{
for (row = 0; row < pDemo->ali3_height; row++)
{
for (col = 0; col < pDemo->ali3_width; col++)
{
pixel = 0x00000000; // Black
*pStorageMem++ = pixel;
}
}
}
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Write the logo image data to the display.
pStorageMem = (uint32_t *)pDemo->uBaseAddr_MEM_FrameBuffer;
for (frame = 0; frame < pDemo->uNumFrames_FrameBuffer; frame++)
{
for (row = 0; row < pDemo->ali3_height; row++)
{
for (col = 0; col < pDemo->ali3_width; col++)
{
// Grab the next pixel data from the static image array.
pixel = avnet_logo_image_data[((row * pDemo->ali3_width) + col)];
// Store the next pixel into the frame buffer space.
*(volatile uint32_t *) pStorageMem++ = pixel;
}
}
}
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Set the mode to draw.
pDemo->mode = draw;
return 0;
}
/*****************************************************************************
*
* Disable MMU for Cortex A53 processors. This function invalidates the TLBs,
* Branch Predictor Array and flushed the D Caches before disabling
* the MMU and D cache.
*
* @param None.
*
* @return None.
*
******************************************************************************/
void Xil_DisableMMU(void)
{
u32 Reg;
mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
Xil_DCacheFlush();
Reg = mfcp(XREG_CP15_SYS_CONTROL);
Reg &= (u32)(~0x05U);
mtcp(XREG_CP15_SYS_CONTROL, Reg);
}
int demo_init_frame_buffer( demo_t *pdemo )
{
// Clear frame stores
if ( pdemo->bVerbose )
{
xil_printf( "Video Frame Buffer Initialization ...\n\r" );
}
Xuint32 frame, row, col;
Xuint16 pixel;
volatile Xuint16 *pStorageMem;
// Fill HDMI frame buffer with Gray ramps
pStorageMem = (Xuint16 *)0x10000000;
volatile Xuint16 *pStorageMem2 = (Xuint16 *)0x18000000;
for ( frame = 0; frame < 3; frame++ )
{
//for ( row = 0; row < pdemo->hdmio_height; row++ )
for ( row = 0; row < 2048; row++ )
{
//for ( col = 0; col < pdemo->hdmio_width; col++ )
for ( col = 0; col < 2048; col++ )
{
pixel = 0x8000 | (col & 0x00FF); // Grey ramp
*pStorageMem++ = pixel;
}
}
}
// Fill Camera frame buffer with green screen
pStorageMem = (Xuint16 *)0x18000000;
for ( frame = 0; frame < 3; frame++ )
{
//for ( row = 0; row < pdemo->hdmio_height; row++ )
for ( row = 0; row < 2048; row++ )
{
//for ( col = 0; col < pdemo->hdmio_width; col++ )
for ( col = 0; col < 2048; col++ )
{
pixel = 0x0000; // Green
*pStorageMem++ = pixel;
}
}
}
// Wait for DMA to synchronize
Xil_DCacheFlush();
return 1;
}
int main()
{
int i = 0;
int audioSize = 0;
int sendValDac = 0;
Xil_DCacheFlush();
Xil_DCacheDisable();
xil_printf("PmodAMP3 Demonstration Project\n\r");
audioSize = (sizeof(audio_data) / sizeof(u32));
xil_printf("Preparing Audio Data...");
for(i = 0; i < audioSize; i++)
{
sendValDac = audio_data[i];
Xil_Out32((PMOD_DATA_BASEADDR + (i * 0x04)), sendValDac);
}
xil_printf("Done!\n\r");
xil_printf("Programming VDMA Core...");
Xil_Out32((VDMA_BASEADDR + 0x000), 0x00000000);
Xil_Out32((VDMA_BASEADDR + 0x000), 0x00000003); // enable circular mode
while((Xil_In32(VDMA_BASEADDR + 0x04) & 0x01) != 0x00);
Xil_Out32((VDMA_BASEADDR + 0x018), 0x01); // frm store
Xil_Out32((VDMA_BASEADDR + 0x05c), PMOD_DATA_BASEADDR); // start address
Xil_Out32((VDMA_BASEADDR + 0x058), 63928); // h offset bytes
Xil_Out32((VDMA_BASEADDR + 0x054), 63928); // h size bytes
Xil_Out32((VDMA_BASEADDR + 0x050), 12); // v size
xil_printf("Done!\n\r");
xil_printf("Enabling SSM2518 Core...");
Xil_Out32(CF_BASEADDR + 0x4040, 0x01);
Xil_Out32(CF_BASEADDR + 0x4044, 0x01);
xil_printf("Done!\n\r");
while(1)
{
}
return 0;
}
/****************************************************************************
*
* Disable the Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheDisable(void)
{
register u32 CtrlReg;
/* clean and invalidate the Data cache */
Xil_DCacheFlush();
/* disable the Data cache */
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
}
/***************************************************************************//**
* @brief Captures a specified number of samples from the ADC.
*
* @param size - number of bytes to read from the device
* @param address - capture start address
*
* @return None.
*******************************************************************************/
void adc_capture(uint32_t size, uint32_t address)
{
uint32_t reg_val;
uint32_t transfer_id;
uint32_t length;
length = (size * 2);
adc_dma_write(AXI_DMAC_REG_CTRL, 0x0);
adc_dma_write(AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
adc_dma_write(AXI_DMAC_REG_IRQ_MASK, 0x0);
adc_dma_read(AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
adc_dma_read(AXI_DMAC_REG_IRQ_PENDING, ®_val);
adc_dma_write(AXI_DMAC_REG_IRQ_PENDING, reg_val);
adc_dma_write(AXI_DMAC_REG_DEST_ADDRESS, address);
adc_dma_write(AXI_DMAC_REG_DEST_STRIDE, 0x0);
adc_dma_write(AXI_DMAC_REG_X_LENGTH, length - 1);
adc_dma_write(AXI_DMAC_REG_Y_LENGTH, 0x0);
adc_dma_write(AXI_DMAC_REG_START_TRANSFER, 0x1);
/* Wait until the new transfer is queued. */
do {
adc_dma_read(AXI_DMAC_REG_START_TRANSFER, ®_val);
}
while(reg_val == 1);
/* Wait until the current transfer is completed. */
do {
adc_dma_read(AXI_DMAC_REG_IRQ_PENDING, ®_val);
}
while(reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));
adc_dma_write(AXI_DMAC_REG_IRQ_PENDING, reg_val);
/* Wait until the transfer with the ID transfer_id is completed. */
do {
adc_dma_read(AXI_DMAC_REG_TRANSFER_DONE, ®_val);
}
while((reg_val & (1 << transfer_id)) != (1 << transfer_id));
#ifdef _XPARAMETERS_PS_H_
Xil_DCacheFlush();
#else
microblaze_flush_dcache();
microblaze_invalidate_dcache();
#endif
}
/**
* Perform DCache all related API test such as Xil_DCacheFlush and
* Xil_DCacheInvalidate. This test function writes a constant value
* to the Data array, flushes the DCache, writes a new value, then invalidates
* the DCache.
*
* @return
* - 0 is returned for a pass
* - -1 is returned for a failure
*/
int Xil_TestDCacheAll(void)
{
int Index;
int Status;
u32 Value;
print("-- Cache All Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0x50500A0A;
print(" initialize Data done:\r\n");
Xil_DCacheFlush();
print(" flush all done\r\n");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = Index + 3;
Xil_DCacheInvalidate();
print(" invalidate all done\r\n");
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0x50500A0A) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
print(" Invalidate all worked\r\n");
}
else {
print("Error: Invalidate dcache all not working\r\n");
}
print("-- DCache all Test Complete --\n\r");
return Status;
}
/*****************************************************************************
*
* Set the memory attributes for a section, in the translation table. Each
* section covers 1MB of memory.
*
* @param addr is the address for which attributes are to be set.
* @param attrib specifies the attributes for that memory region.
*
* @return None.
*
* @note The MMU and D-cache need not be disabled before changing an
* translation table attribute.
*
******************************************************************************/
void Xil_SetTlbAttributes(u32 addr, u32 attrib)
{
u32 *ptr;
u32 section;
section = addr / 0x100000;
ptr = &MMUTable + section;
*ptr = (addr & 0xFFF00000) | attrib;
Xil_DCacheFlush();
mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0);
/* Invalidate all branch predictors */
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
dsb(); /* ensure completion of the BP and TLB invalidation */
isb(); /* synchronize context on this processor */
}
/*****************************************************************************
*
* Set the memory attributes for a section, in the translation table. Each
* section covers 1MB of memory.
*
* @param Addr is the address for which attributes are to be set.
* @param attrib specifies the attributes for that memory region.
*
* @return None.
*
* @note The MMU and D-cache need not be disabled before changing an
* translation table attribute.
*
******************************************************************************/
void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
{
u32 *ptr;
u32 section;
section = Addr / 0x100000U;
ptr = &MMUTable;
ptr += section;
if(ptr != NULL) {
*ptr = (Addr & 0xFFF00000U) | attrib;
}
Xil_DCacheFlush();
mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
/* Invalidate all branch predictors */
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
dsb(); /* ensure completion of the BP and TLB invalidation */
isb(); /* synchronize context on this processor */
}
/*****************************************************************************
*
* Disable MMU for Cortex A9 processors. This function invalidates the TLBs,
* Branch Predictor Array and flushed the D Caches before disabling
* the MMU and D cache.
*
* @param None.
*
* @return None.
*
******************************************************************************/
void Xil_DisableMMU(void)
{
u32 Reg;
mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0);
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
Xil_DCacheFlush();
#ifdef __GNUC__
Reg = mfcp(XREG_CP15_SYS_CONTROL);
#else
{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
Reg = Cp15Reg; }
#endif
Reg &= ~0x05;
#ifdef CONFIG_ARM_ERRATA_794073
/* Disable Branch Prediction */
Reg &= ~0x800;
#endif
mtcp(XREG_CP15_SYS_CONTROL, Reg);
}
/**
* @brief Set the memory attributes for a section of memory in the
* translation table.
*
* @param Addr: 32-bit address for which memory attributes need to be set..
* @param size: size is the size of the region.
* @param attrib: Attribute for the given memory region.
* @return None.
*
*
******************************************************************************/
u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
{
u32 Regionsize = 0;
INTPTR Localaddr = addr;
u32 NextAvailableMemRegion;
unsigned int i;
NextAvailableMemRegion = Xil_GetNextMPURegion();
if (NextAvailableMemRegion == 0xFF) {
xdbg_printf(DEBUG, "No regions available\r\n");
return XST_FAILURE;
}
Xil_DCacheFlush();
Xil_ICacheInvalidate();
mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
isb();
/* Lookup the size. */
for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
if (size <= region_size[i].size) {
Regionsize = region_size[i].encoding;
break;
}
}
Localaddr &= ~(region_size[i].size - 1);
Regionsize <<= 1;
Regionsize |= REGION_EN;
dsb();
mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */
mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */
mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/
dsb();
isb();
Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
return XST_SUCCESS;
}
static int SD_TransferPartial(char *FileName, u32 DestinationAddress)
{
FIL fil;
FRESULT rc;
UINT br;
u32 file_size;
rc = f_open(&fil, FileName, FA_READ);
if (rc) {
xil_printf(" ERROR : f_open returned %d\r\n", rc);
return XST_FAILURE;
}
file_size = f_size(&fil);
//xil_printf("file size is %0x\n\r",file_size);
rc = f_lseek(&fil, 0);
if (rc) {
xil_printf(" ERROR : f_lseek returned %d\r\n", rc);
return XST_FAILURE;
}
rc = f_read(&fil, (void*) DestinationAddress, file_size, &br);
if (rc) {
xil_printf(" ERROR : f_read returned %d\r\n", rc);
return XST_FAILURE;
}
rc = f_close(&fil);
if (rc) {
xil_printf(" ERROR : f_close returned %d\r\n", rc);
return XST_FAILURE;
}
Xil_DCacheFlush();
return file_size;
}
////////////////////////////////////////////////////////////////////////////////
//! Perform the wavelet decomposition
////////////////////////////////////////////////////////////////////////////////
int runTest( int argc, char** argv)
{
int i;
#ifdef HW
XFcuda xcore;
int Status;
Status = XFcuda_Initialize(&xcore, 0);
if (Status != XST_SUCCESS) {
printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
#endif
unsigned int slength = 262144;
// get the number of decompositions necessary to perform a full decomposition
unsigned int dlevels_complete = 0;
if (1 != getLevels( slength, &dlevels_complete))
{
// error message
fprintf( stderr, "Signal length not supported.\n");
return;
}
// device in data
float* d_idata = NULL;
// device out data
float* d_odata = NULL;
// device approx_final data
float* approx_final = NULL;
// The very final approximation coefficient has to be written to the output
// data, all others are reused as input data in the next global step and
// therefore have to be written to the input data again.
// The following flag indicates where to copy approx_final data
// - 0 is input, 1 is output
int approx_is_input;
// allocate device mem
const unsigned int smem_size = sizeof(float) * slength;
d_idata = (float*) malloc(smem_size);
d_odata = (float*) malloc(smem_size);
approx_final = (float*) malloc(smem_size);
// copy input data to device
memcpy(d_idata, signal, smem_size);
// clear result memory
float* tmp = (float*) malloc( smem_size);
for (i = 0; i < slength; ++i)
tmp[i] = 0.0;
memcpy(d_odata, tmp, smem_size);
free(tmp);
// total number of threads
// in the first decomposition step always one thread computes the average and
// detail signal for one pair of adjacent values
unsigned int num_threads_total_left = slength / 2;
// decomposition levels performed in the current / next step
unsigned int dlevels_step = dlevels_complete;
// 1D signal so the arrangement of elements is also 1D
dim3 block_size;
dim3 grid_size;
// number of decomposition levels left after one iteration on the device
unsigned int dlevels_left = dlevels_complete;
// if less or equal 1k elements, then the data can be processed in one block,
// this avoids the Wait-For-Idle (WFI) on host side which is necessary if the
// computation is split accross multiple SM's if enough input data
if( dlevels_complete <= 10) {
// decomposition can be performed at once
block_size.x = num_threads_total_left;
approx_is_input = 0;
} else {
// 512 threads per block
grid_size.x = (num_threads_total_left / 512);
block_size.x = 512;
// 512 threads corresponds to 10 decomposition steps
dlevels_step = 10;
dlevels_left -= 10;
approx_is_input = 1;
}
grid_size.y = 1;
grid_size.z = 1;
block_size.y = 1;
block_size.z = 1;
#ifdef HW
XFcuda_SetGriddim_y(&xcore, grid_size.y);
//XFcuda_SetGriddim_z(&xcore, grid_size.z);
//XFcuda_SetBlockdim_y(&xcore, block_size.y);
//XFcuda_SetBlockdim_z(&xcore, block_size.z);
XFcuda_SetId_addr(&xcore, (int)d_idata / sizeof(float));
XFcuda_SetOd_addr(&xcore, (int)d_odata / sizeof(float));
XFcuda_SetApprox_final_addr(&xcore, (int)approx_final / sizeof(float));
#endif
while( 0 != num_threads_total_left) {
#ifndef HW
//PS execution
dwtHaar1D(d_idata, d_odata, approx_final, dlevels_step, num_threads_total_left, block_size.x, grid_size, block_size, 1, 0);
#else
XFcuda_SetDlevels(&xcore, dlevels_step);
XFcuda_SetSlength_step_half(&xcore, num_threads_total_left);
XFcuda_SetBdim(&xcore, block_size.x);
XFcuda_SetGriddim_x(&xcore, grid_size.x);
XFcuda_SetBlockdim_x(&xcore, block_size.x);
Xil_DCacheFlush();
XFcuda_SetEn_fcuda1(&xcore, 1);
XFcuda_Start(&xcore);
while (!XFcuda_IsDone(&xcore));
#endif
// Copy approx_final to appropriate location
if (approx_is_input) {
memcpy(d_idata, approx_final, grid_size.x*4);
}
else {
memcpy(d_odata, approx_final, grid_size.x*4);
}
// update level variables
if( dlevels_left < 10) {
// approx_final = d_odata;
approx_is_input = 0;
}
// more global steps necessary
dlevels_step = (dlevels_left > 10) ? dlevels_left - 10 : dlevels_left;
dlevels_left -= 10;
// after each step only half the threads are used any longer
// therefore after 10 steps 2^10 less threads
num_threads_total_left = num_threads_total_left >> 10;
// update block and grid size
grid_size.x = (num_threads_total_left / 512)
+ (0 != (num_threads_total_left % 512)) ? 1 : 0;
if( grid_size.x <= 1) {
block_size.x = num_threads_total_left;
}
}
#ifdef VERIFY
for (i = 0; i < 10; i++)
printf("index=%d, ref=%f, fpga=%f\n", i, reference[i], d_odata[i]);
int res = compareData(reference, d_odata, slength, 0.1f);
printf("%s\n", (1 == res) ? "PASSED." : "FAILED.");
#endif
free(d_idata);
free(d_odata);
free(approx_final);
}
int zed_ali3_controller_demo_touch_process(zed_ali3_controller_demo_t *pDemo)
{
int result = 0;
interface_graphic_t graphic;
touch_calibration_matrix_t touch_calibration_matrix;
touch_location_t touch_location_raw;
touch_location_t touch_location_cal;
// Set the calibration matrix with the demo instance coefficients.
touch_calibration_matrix.An = pDemo->calibration_An;
touch_calibration_matrix.Bn = pDemo->calibration_Bn;
touch_calibration_matrix.Cn = pDemo->calibration_Cn;
touch_calibration_matrix.Dn = pDemo->calibration_Dn;
touch_calibration_matrix.En = pDemo->calibration_En;
touch_calibration_matrix.Fn = pDemo->calibration_Fn;
touch_calibration_matrix.divisor = pDemo->calibration_divisor;
/*
* Check to see if any touch events have been registered. This call
* needs to be thread safe with respect to the touch controller
* interrupts. Disable interrupts before the call and re-enable
* after the call to process the touch event.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// This call must be thread safe in order to maintain queue stability.
result = tmg120_process_touch_event(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
if (result == 1)
{
// Update the touch location with the most recent raw touch position.
touch_location_raw.position_x = pDemo->touch_posx_raw;
touch_location_raw.position_y = pDemo->touch_posy_raw;
tmg120_translate_location(pDemo, &touch_location_raw, &touch_location_cal, &touch_calibration_matrix);
// Update the calibrated touch location with translated location.
pDemo->touch_posx_cal = touch_location_cal.position_x;
pDemo->touch_posy_cal = touch_location_cal.position_y;
/*
* A little maintenance is needed on the translated points. Due to
* the integer math involved, if a point is represented beyond the
* display dimensions, it should get mapped to 0 because it is an
* overflow calculation.
*/
if (pDemo->touch_posx_cal > pDemo->ali3_width)
{
pDemo->touch_posx_cal = 0;
}
if (pDemo->touch_posy_cal > pDemo->ali3_height)
{
pDemo->touch_posy_cal = 0;
}
if (pDemo->bVerbose > 0)
{
xil_printf("Processed PCAP Event:Raw PosX=0x%04X,Raw PosY=0x%04X,Cal PosX=%3d,Cal PosY=%3d\n\r",
pDemo->touch_posx_raw,
pDemo->touch_posy_raw,
pDemo->touch_posx_cal,
pDemo->touch_posy_cal
);
}
// Check to see how the touch event should be handled.
if (pDemo->mode == draw)
{
// Draw the touch location indicator 'dot' to the display.
if ((pDemo->touch_posx_cal > avnet_draw_pen_black_width) &&
(pDemo->touch_posx_cal < (pDemo->ali3_width - avnet_draw_pen_black_width)))
{
graphic.location_x = pDemo->touch_posx_cal - (avnet_draw_pen_black_width / 2); // Centered on graphic
}
else if (pDemo->touch_posx_cal >= (pDemo->ali3_width - avnet_draw_pen_black_width))
{
graphic.location_x = pDemo->ali3_width - avnet_draw_pen_black_width;
}
else
{
graphic.location_x = avnet_draw_pen_black_width;
}
if ((pDemo->touch_posy_cal > avnet_draw_pen_black_height) &&
(pDemo->touch_posy_cal < (pDemo->ali3_height - avnet_draw_pen_black_height)))
{
graphic.location_y = pDemo->touch_posy_cal - (avnet_draw_pen_black_height / 2); // Centered on graphic
}
else if (pDemo->touch_posy_cal >= (pDemo->ali3_height - avnet_draw_pen_black_height))
{
graphic.location_y = pDemo->ali3_height - avnet_draw_pen_black_height;
}
else
{
graphic.location_y = avnet_draw_pen_black_height;
}
graphic.size_x = avnet_draw_pen_black_width;
graphic.size_y = avnet_draw_pen_black_height;
graphic.default_image_data = avnet_draw_pen_black;
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
}
else if ((pDemo->mode == control) &&
(pDemo->touch_pen_down_transition == 1))
{
/*
* Decode touch location against control positions.
*/
if ((pDemo->touch_posx_cal >= LED0_POSITION_X) && (pDemo->touch_posx_cal <= (LED0_POSITION_X + avnet_control_led_off_width)) &&
(pDemo->touch_posy_cal >= LED0_POSITION_Y) && (pDemo->touch_posy_cal <= (LED0_POSITION_Y + avnet_control_led_off_height)))
{
// Touch event on LED0 control.
if (pDemo->bVerbose)
{
xil_printf("Registered touch on LED 0 control.\n\r");
}
if (pDemo->led0_state == 0)
{
// Old state was off, so new state should be on.
zed_ali3_controller_demo_led(pDemo, 0, 1);
}
else
{
// Old state was on, so new state should be off.
zed_ali3_controller_demo_led(pDemo, 0, 0);
}
}
if ((pDemo->touch_posx_cal >= LED1_POSITION_X) && (pDemo->touch_posx_cal <= (LED1_POSITION_X + avnet_control_led_off_width)) &&
(pDemo->touch_posy_cal >= LED1_POSITION_Y) && (pDemo->touch_posy_cal <= (LED1_POSITION_Y + avnet_control_led_off_height)))
{
// Touch event on LED1 control.
if (pDemo->bVerbose)
{
xil_printf("Registered touch on LED 1 control.\n\r");
}
if (pDemo->led1_state == 0)
{
// Old state was off, so new state should be on.
zed_ali3_controller_demo_led(pDemo, 1, 1);
}
else
{
// Old state was on, so new state should be off.
zed_ali3_controller_demo_led(pDemo, 1, 0);
}
}
if ((pDemo->touch_posx_cal >= LED2_POSITION_X) && (pDemo->touch_posx_cal <= (LED2_POSITION_X + avnet_control_led_off_width)) &&
(pDemo->touch_posy_cal >= LED2_POSITION_Y) && (pDemo->touch_posy_cal <= (LED2_POSITION_Y + avnet_control_led_off_height)))
{
// Touch event on LED2 control.
if (pDemo->bVerbose)
{
xil_printf("Registered touch on LED 2 control.\n\r");
}
if (pDemo->led2_state == 0)
{
// Old state was off, so new state should be on.
zed_ali3_controller_demo_led(pDemo, 2, 1);
}
else
{
// Old state was on, so new state should be off.
zed_ali3_controller_demo_led(pDemo, 2, 0);
}
}
if ((pDemo->touch_posx_cal >= LED3_POSITION_X) && (pDemo->touch_posx_cal <= (LED3_POSITION_X + avnet_control_led_off_width)) &&
(pDemo->touch_posy_cal >= LED3_POSITION_Y) && (pDemo->touch_posy_cal <= (LED3_POSITION_Y + avnet_control_led_off_height)))
{
// Touch event on LED3 control.
if (pDemo->bVerbose)
{
xil_printf("Registered touch on LED 3 control.\n\r");
}
if (pDemo->led3_state == 0)
{
// Old state was off, so new state should be on.
zed_ali3_controller_demo_led(pDemo, 3, 1);
}
else
{
// Old state was on, so new state should be off.
zed_ali3_controller_demo_led(pDemo, 3, 0);
}
}
}
}
return 0;
}
/**
*
* File system example using SD driver to write to and read from an SD card
* in polled mode. This example creates a new file on an
* SD card (which is previously formatted with FATFS), write data to the file
* and reads the same data back to verify.
*
* @param None
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None
*
******************************************************************************/
int FfsSdPolledExample(void)
{
FRESULT Res;
UINT NumBytesRead;
UINT NumBytesWritten;
u32 BuffCnt;
u32 FileSize = (8*1024*1024);
Xil_DCacheFlush();
Xil_DCacheDisable();
for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
SourceAddress[BuffCnt] = TEST + BuffCnt;
}
/*
* Register volume work area, initialize device
*/
Res = f_mount(0, &fatfs);
if (Res != FR_OK) {
return XST_FAILURE;
}
/*
* Open file with required permissions.
* Here - Creating new file with read/write permissions. .
*/
SD_File = (char *)FileName;
Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
if (Res) {
return XST_FAILURE;
}
/*
* Pointer to beginning of file .
*/
Res = f_lseek(&fil, 0);
if (Res) {
return XST_FAILURE;
}
/*
* Write data to file.
*/
Res = f_write(&fil, (const void*)SourceAddress, FileSize,
&NumBytesWritten);
if (Res) {
return XST_FAILURE;
}
/*
* Pointer to beginning of file .
*/
Res = f_lseek(&fil, 0);
if (Res) {
return XST_FAILURE;
}
/*
* Read data from file.
*/
Res = f_read(&fil, (void*)DestinationAddress, FileSize,
&NumBytesRead);
if (Res) {
return XST_FAILURE;
}
/*
* Data verification
*/
for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
if(SourceAddress[BuffCnt] != DestinationAddress[BuffCnt]){
return XST_FAILURE;
}
}
/*
* Close file.
*/
Res = f_close(&fil);
if (Res) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
int zed_ali3_controller_demo_init( zed_ali3_controller_demo_t *pDemo )
{
int ret;
xil_printf("\n\r");
xil_printf("------------------------------------------------------\n\r");
xil_printf("-- Zynq Mini-ITX Display Kit --\n\r");
xil_printf("-- ALI3 Controller Demonstration --\n\r");
xil_printf("-- DH TMG120 Diagnostics Application --\n\r");
xil_printf("------------------------------------------------------\n\r");
xil_printf("\n\r");
// Fill frame stores with color bars
xil_printf( "Video Frame Buffer Initialization ...\n\r" );
int32u frame, row, col;
int32u pixel;
volatile int32u *pStorageMem = (int32u *)pDemo->uBaseAddr_MEM_FrameBuffer;
for ( frame = 0; frame < pDemo->uNumFrames_FrameBuffer; frame++ )
{
for ( row = 0; row < pDemo->ali3_height; row++ )
{
for ( col = 0; col < pDemo->ali3_width; col++ )
{
pixel = 0x00000000; // Black
*pStorageMem++ = pixel;
}
}
}
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Initialize Output Side of AXI VDMA
xil_printf( "Video DMA (Output Side) Initialization ...\n\r" );
vfb_common_init(
pDemo->uDeviceId_VDMA_FrameBuffer, // uDeviceId
&(pDemo->vdma_ali3) // pAxiVdma
);
vfb_tx_init(
&(pDemo->vdma_ali3), // pAxiVdma
&(pDemo->vdmacfg_ali3_read), // pReadCfg
pDemo->ali3_resolution, // uVideoResolution
pDemo->ali3_resolution, // uStorageResolution
pDemo->uBaseAddr_MEM_FrameBuffer, // uMemAddr
pDemo->uNumFrames_FrameBuffer // uNumFrames
);
// IIC Initialization for touch controller
xil_printf( "I2C Touch Controller Initialization ...\n\r");
ret = zed_iic_axi_init(&(pDemo->touch_iic),"ALI3 Touch I2C Controller", pDemo->uBaseAddr_IIC_Touch);
if ( !ret )
{
xil_printf("ERROR : Failed to open ZED-IIC driver\n\r");
return -1;
}
/* For Zynq Mini-ITX, the I2C mux must be set to Channel 4 in order to
* communicate with the touch controller.
*/
ret = zed_ali3_controller_demo_initialize_mux(pDemo, I2C_MUX_SLAVE_ADDRESS);
pDemo->touch_irqs = 0;
pDemo->touch_events = 0;
pDemo->touch_posx = 0x0000;
pDemo->touch_posy = 0x0000;
zed_ali3_controller_demo_SetupInterruptSystem( pDemo );
tmg_120_initialize( pDemo );
return 0;
}
int zed_ali3_controller_demo_touch_calibrate(zed_ali3_controller_demo_t *pDemo)
{
int result = 0;
interface_graphic_t graphic;
touch_calibration_data_t touch_calibration_data;
touch_calibration_matrix_t touch_calibration_matrix;
/* This routine must collect three sample points based upon the operators
* actual touch input. To do this, three targets are drawn on the display
* while we await touch input for each target location. The targets should
* be widely separated but also need to avoid the areas near the edges
* where touch sensor output tends to become non-linear.
*/
xil_printf("\n\r");
xil_printf("-----------------------------------------------------------------------\n\r");
xil_printf("-- Zed Display Kit --\n\r");
xil_printf("-- Starting Calibration Procedure, Touch Targets Shown On Display --\n\r");
xil_printf("-----------------------------------------------------------------------\n\r");
xil_printf("\n\r");
// Set first target location to 25% display width and 50% display height.
touch_calibration_data.reference_touch_position1.position_x = (pDemo->ali3_width / 4);
touch_calibration_data.reference_touch_position1.position_y = (pDemo->ali3_height / 2);
// Set second target location to 50% display width and 25% display height.
touch_calibration_data.reference_touch_position2.position_x = (pDemo->ali3_width / 2);
touch_calibration_data.reference_touch_position2.position_y = (pDemo->ali3_height / 4);
// Set third target location to 75% display width and 75% display height.
touch_calibration_data.reference_touch_position3.position_x = (pDemo->ali3_width / 4) * 3;
touch_calibration_data.reference_touch_position3.position_y = (pDemo->ali3_height / 4) * 3;
// Blank the screen,
draw_blank_screen(pDemo, COLOR_BLACK);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Draw the first target to the display.
graphic.location_x = touch_calibration_data.reference_touch_position1.position_x - (avnet_touch_target_width / 2); // Centered on graphic
graphic.location_y = touch_calibration_data.reference_touch_position1.position_y - (avnet_touch_target_height / 2); // Centered on graphic
graphic.size_x = avnet_touch_target_width;
graphic.size_y = avnet_touch_target_height;
graphic.default_image_data = avnet_touch_target;
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
/*
* Flush any registered touch events from the queue. This call must
* be threadsafe since it operates on the queue itself.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// Flush any existing touch events.
tmg120_flush_touch_events(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
result = 0;
while (result != 1)
{
/*
* Check to see if any touch events have been registered. This call
* needs to be thread safe with respect to the touch controller
* interrupts. Disable interrupts before the call and re-enable
* after the call to process the touch event.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// This call must be thread safe in order to maintain queue stability.
result = tmg120_process_touch_event(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
millisleep(100);
}
xil_printf("Processed PCAP Calibration Event: PosX=0x%04X, PoxY=0x%04X\n\r",
pDemo->touch_posx_raw,
pDemo->touch_posy_raw
);
// Capture the sample information for the calibration matrix.
touch_calibration_data.raw_touch_position1.position_x = pDemo->touch_posx_raw;
touch_calibration_data.raw_touch_position1.position_y = pDemo->touch_posy_raw;
// Blank the screen,
draw_blank_screen(pDemo, COLOR_BLACK);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Sleep while the display is updated.
sleep(1);
// Draw the second target to the display.
graphic.location_x = touch_calibration_data.reference_touch_position2.position_x - (avnet_touch_target_width / 2); // Centered on graphic
graphic.location_y = touch_calibration_data.reference_touch_position2.position_y - (avnet_touch_target_height / 2); // Centered on graphic
graphic.size_x = avnet_touch_target_width;
graphic.size_y = avnet_touch_target_height;
graphic.default_image_data = avnet_touch_target;
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
/*
* Flush any registered touch events from the queue. This call must
* be threadsafe since it operates on the queue itself.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// Flush any existing touch events.
tmg120_flush_touch_events(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
result = 0;
while (result != 1)
{
/*
* Check to see if any touch events have been registered. This call
* needs to be thread safe with respect to the touch controller
* interrupts. Disable interrupts before the call and re-enable
* after the call to process the touch event.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// This call must be thread safe in order to maintain queue stability.
result = tmg120_process_touch_event(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
millisleep(100);
}
xil_printf("Processed PCAP Calibration Event: PosX=0x%04X, PoxY=0x%04X\n\r",
pDemo->touch_posx_raw,
pDemo->touch_posy_raw
);
// Capture the sample information for the calibration matrix.
touch_calibration_data.raw_touch_position2.position_x = pDemo->touch_posx_raw;
touch_calibration_data.raw_touch_position2.position_y = pDemo->touch_posy_raw;
// Blank the screen,
draw_blank_screen(pDemo, COLOR_BLACK);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Sleep while the display is updated.
sleep(1);
// Draw the third target to the display.
graphic.location_x = touch_calibration_data.reference_touch_position3.position_x - (avnet_touch_target_width / 2); // Centered on graphic
graphic.location_y = touch_calibration_data.reference_touch_position3.position_y - (avnet_touch_target_height / 2); // Centered on graphic
graphic.size_x = avnet_touch_target_width;
graphic.size_y = avnet_touch_target_height;
graphic.default_image_data = avnet_touch_target;
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
/*
* Flush any registered touch events from the queue. This call must
* be threadsafe since it operates on the queue itself.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// Flush any existing touch events.
tmg120_flush_touch_events(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
result = 0;
while (result != 1)
{
/*
* Check to see if any touch events have been registered. This call
* needs to be thread safe with respect to the touch controller
* interrupts. Disable interrupts before the call and re-enable
* after the call to process the touch event.
*/
XScuGic_Disable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
// This call must be thread safe in order to maintain queue stability.
result = tmg120_process_touch_event(pDemo);
// Re-enable touch interrupts.
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
millisleep(100);
}
xil_printf("Processed PCAP Calibration Event: PosX=0x%04X, PoxY=0x%04X\n\r",
pDemo->touch_posx_raw,
pDemo->touch_posy_raw
);
// Capture the sample information for the calibration matrix.
touch_calibration_data.raw_touch_position3.position_x = pDemo->touch_posx_raw;
touch_calibration_data.raw_touch_position3.position_y = pDemo->touch_posy_raw;
// Blank the screen,
draw_blank_screen(pDemo, COLOR_BLACK);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
/*
* Calculate the calibration matrix coefficients based upon the three
* touch points that were just captured.
*/
result = tmg120_get_calibration_matrix(pDemo, &touch_calibration_data, &touch_calibration_matrix);
// Update the demo instance with the new calibration coefficients.
pDemo->calibration_An = touch_calibration_matrix.An;
pDemo->calibration_Bn = touch_calibration_matrix.Bn;
pDemo->calibration_Cn = touch_calibration_matrix.Cn;
pDemo->calibration_Dn = touch_calibration_matrix.Dn;
pDemo->calibration_En = touch_calibration_matrix.En;
pDemo->calibration_Fn = touch_calibration_matrix.Fn;
pDemo->calibration_divisor = touch_calibration_matrix.divisor;
/*
* Store the updated calibration matrix coefficients to SPI flash so
* that they are persisted between power cycles.
*/
result = qspi_flash_store_calibration_data(pDemo);
if (result != 0)
{
xil_printf("Calibration not written to Flash due to error.\n\r");
}
return result;
}
int zed_ali3_controller_demo_init(zed_ali3_controller_demo_t *pDemo)
{
int ret;
interface_graphic_t graphic;
xil_printf("\n\r");
xil_printf("------------------------------------------------------\n\r");
xil_printf("-- Zed Display Kit --\n\r");
xil_printf("-- ALI3 Controller Demonstration --\n\r");
xil_printf("-- Standalone Application --\n\r");
xil_printf("------------------------------------------------------\n\r");
xil_printf("\n\r");
// Blank the screen,
draw_blank_screen(pDemo, COLOR_BLACK);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Draw the system configuration graphic to the display.
graphic.location_x = 400 - (avnet_control_system_config_width / 2); // Centered on graphic
graphic.location_y = 240 - (avnet_control_system_config_height / 2); // Centered on graphic
graphic.size_x = avnet_control_system_config_width;
graphic.size_y = avnet_control_system_config_height;
graphic.default_image_data = avnet_control_system_config;
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
// Initialize Output Side of AXI VDMA
xil_printf("Video DMA (Output Side) Initialization ...\n\r");
vfb_common_init(
pDemo->uDeviceId_VDMA_FrameBuffer, // uDeviceId
&(pDemo->vdma_ali3) // pAxiVdma
);
vfb_tx_init(
&(pDemo->vdma_ali3), // pAxiVdma
&(pDemo->vdmacfg_ali3_read), // pReadCfg
pDemo->ali3_resolution, // uVideoResolution
pDemo->ali3_resolution, // uStorageResolution
pDemo->uBaseAddr_MEM_FrameBuffer, // uMemAddr
pDemo->uNumFrames_FrameBuffer // uNumFrames
);
/*
* Initialize the QSPI flash and load any stored touch screen calibration
* values.
*/
if (qspi_flash_polled_init() != 0)
{
xil_printf("ERROR : Failed to open QSPI driver\n\r");
}
/*
* Load the touch calibration data from flash memory.
*/
if (qspi_flash_load_calibration_data(pDemo) != 0)
{
xil_printf("No Valid Calibration Data Found in Flash\n\r");
/*
* Cause touch calibration to occur after init() finishes.
*/
pDemo->calibration_success = 0;
}
else
{
pDemo->calibration_success = 1;
}
// IIC Initialization for touch controller
xil_printf("I2C Touch Controller Initialization ...\n\r");
ret = zed_iic_axi_init(&(pDemo->touch_iic),"ALI3 Touch I2C Controller", pDemo->uBaseAddr_IIC_Touch);
if (!ret)
{
xil_printf("ERROR : Failed to open ZED-IIC driver\n\r");
return -1;
}
// Initialize the touch controller and prepare the event handler.
tmg120_initialize(pDemo);
// Setup the interrupt handling for the touch controller.
zed_ali3_controller_demo_SetupInterruptSystem(pDemo);
// Enable the touch controller to begin detecting touch input.
tmg120_enable_touch(pDemo);
// Initialize the GPIO interfaces.
pDemo->button0_state = 0;
pDemo->button1_state = 0;
pDemo->led0_state = 0;
pDemo->led1_state = 0;
pDemo->led2_state = 0;
pDemo->led3_state = 0;
zed_ali3_controller_demo_button(pDemo, 0, pDemo->button0_state);
zed_ali3_controller_demo_button(pDemo, 1, pDemo->button1_state);
zed_ali3_controller_demo_led(pDemo, 0, pDemo->led0_state);
zed_ali3_controller_demo_led(pDemo, 1, pDemo->led1_state);
zed_ali3_controller_demo_led(pDemo, 2, pDemo->led2_state);
zed_ali3_controller_demo_led(pDemo, 3, pDemo->led3_state);
// Set the mode to draw by default.
pDemo->mode = draw;
return 0;
}
int zed_ali3_controller_demo_led(zed_ali3_controller_demo_t *pDemo, int led_number, int led_state)
{
interface_graphic_t graphic;
// Update the LED hardware on the board.
ps_gpio_set_led(pDemo, led_number, led_state);
// Update the user interface to match the LED state change.
if (led_number == 0)
{
pDemo->led0_state = led_state;
graphic.location_x = LED0_POSITION_X;
graphic.location_y = LED0_POSITION_Y;
}
else if (led_number == 1)
{
pDemo->led1_state = led_state;
graphic.location_x = LED1_POSITION_X;
graphic.location_y = LED1_POSITION_Y;
}
else if (led_number == 2)
{
pDemo->led2_state = led_state;
graphic.location_x = LED2_POSITION_X;
graphic.location_y = LED2_POSITION_Y;
}
else if (led_number == 3)
{
pDemo->led3_state = led_state;
graphic.location_x = LED3_POSITION_X;
graphic.location_y = LED3_POSITION_Y;
}
else
{
return -1;
}
// Determine the ON/OFF state graphic to be shown.
if (led_state == 0)
{
// Draw the LED off state.
graphic.default_image_data = avnet_control_led_off;
graphic.alternate_image_data = avnet_control_led_on;
// All the LED images have the same OFF width.
graphic.size_x = avnet_control_led_off_width;
graphic.size_y = avnet_control_led_off_height;
}
else if (led_state == 1)
{
// Draw the LED on state.
graphic.default_image_data = avnet_control_led_on;
graphic.alternate_image_data = avnet_control_led_off;
// All the LED images have the same ON width.
graphic.size_x = avnet_control_led_on_width;
graphic.size_y = avnet_control_led_on_height;
}
else
{
return -1;
}
// Check to see how the touch event should be handled.
if (pDemo->mode == control)
{
// Draw the LED graphic to the display.
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
}
return 0;
}
void platform_dcache_all_flush()
{
Xil_DCacheFlush();
}
int zed_ali3_controller_demo_button(zed_ali3_controller_demo_t *pDemo, int button_number, int button_state)
{
interface_graphic_t graphic;
// Update the user interface to match the button state change.
if (button_number == 0)
{
pDemo->button0_state = button_state;
graphic.location_x = BUTTON0_POSITION_X;
graphic.location_y = BUTTON0_POSITION_Y;
}
else if (button_number == 1)
{
pDemo->button1_state = button_state;
graphic.location_x = BUTTON1_POSITION_X;
graphic.location_y = BUTTON1_POSITION_Y;
}
else
{
return -1;
}
// Determine the ON/OFF state graphic to be shown.
if (button_state == 0)
{
// Draw the switch off state.
graphic.default_image_data = avnet_control_pb_off;
graphic.alternate_image_data = avnet_control_pb_on;
// All the switch images have the same OFF width.
graphic.size_x = avnet_control_pb_off_width;
graphic.size_y = avnet_control_pb_off_height;
}
else if (button_state == 1)
{
// Draw the switch on state.
graphic.default_image_data = avnet_control_pb_on;
graphic.alternate_image_data = avnet_control_pb_off;
// All the switch images have the same ON width.
graphic.size_x = avnet_control_pb_on_width;
graphic.size_y = avnet_control_pb_on_height;
}
else
{
return -1;
}
// Check to see how the touch event should be handled.
if (pDemo->mode == control)
{
// Draw the button graphic to the display.
draw_image_data(pDemo, &graphic);
// Wait for DMA to synchronize.
Xil_DCacheFlush();
}
return 0;
}
/**
*
* Disable the data cache.
*
* @param None
*
* @return None.
*
****************************************************************************/
void Xil_DCacheDisable(void)
{
Xil_DCacheFlush();
Xil_DCacheInvalidate();
Xil_L1DCacheDisable();
}
void platform_cache_all_flush_invalidate() {
Xil_DCacheFlush();
Xil_DCacheInvalidate();
Xil_ICacheInvalidate();
}
/***************************************************************************//**
* @brief dac_init
*******************************************************************************/
void dac_init(uint8_t data_sel)
{
uint32_t status;
uint32_t tx_count;
uint32_t index;
uint32_t index_i1;
uint32_t index_q1;
uint32_t index_i2;
uint32_t index_q2;
uint32_t data_i1;
uint32_t data_q1;
uint32_t data_i2;
uint32_t data_q2;
dac_write(ADI_REG_RSTN, 0x0);
dac_write(ADI_REG_RSTN, ADI_RSTN);
dac_write(ADI_REG_RATECNTRL, ADI_RATE(3));
dds_st.dac_clk = &ad9361_phy->clks[TX_SAMPL_CLK]->rate;
dac_write(ADI_REG_CNTRL_1, 0);
switch (data_sel) {
case DATA_SEL_DDS:
dds_default_setup(DDS_CHAN_TX1_I_F1, 90000, 1000000, 4);
dds_default_setup(DDS_CHAN_TX1_I_F2, 90000, 1000000, 4);
dds_default_setup(DDS_CHAN_TX1_Q_F1, 0, 1000000, 4);
dds_default_setup(DDS_CHAN_TX1_Q_F2, 0, 1000000, 4);
dds_default_setup(DDS_CHAN_TX2_I_F1, 90000, 1000000, 4);
dds_default_setup(DDS_CHAN_TX2_I_F2, 90000, 1000000, 4);
dds_default_setup(DDS_CHAN_TX2_Q_F1, 0, 1000000, 4);
dds_default_setup(DDS_CHAN_TX2_Q_F2, 0, 1000000, 4);
dac_write(ADI_REG_CNTRL_2, ADI_DATA_SEL(DATA_SEL_DDS));
break;
case DATA_SEL_DMA:
tx_count = sizeof(sine_lut) / sizeof(uint16_t);
dac_write(ADI_REG_VDMA_FRMCNT, tx_count * 8);
for(index = 0; index < (tx_count * 2); index+=2)
{
index_i1 = index;
index_q1 = index + (tx_count / 4);
if(index_q1 >= (tx_count * 2))
index_q1 -= (tx_count * 2);
data_i1 = (sine_lut[index_i1 / 2] << 20);
data_q1 = (sine_lut[index_q1 / 2] << 4);
Xil_Out32(DAC_DDR_BASEADDR + index * 4, data_i1 | data_q1);
index_i2 = index_i1 + (tx_count / 2);
index_q2 = index_q1 + (tx_count / 2);
if(index_i2 >= (tx_count * 2))
index_i2 -= (tx_count * 2);
if(index_q2 >= (tx_count * 2))
index_q2 -= (tx_count * 2);
data_i2 = (sine_lut[index_i2 / 2] << 20);
data_q2 = (sine_lut[index_q2 / 2] << 4);
Xil_Out32(DAC_DDR_BASEADDR + (index + 1) * 4, data_i2 | data_q2);
}
Xil_DCacheFlush();
vdma_write(XAXIVDMA_CR_OFFSET, 0x0);
vdma_write(XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_TAIL_EN_MASK | XAXIVDMA_CR_RUNSTOP_MASK);
do {
vdma_read(XAXIVDMA_SR_OFFSET, &status);
}
while((status & 0x01) == 0x01);
vdma_write(XAXIVDMA_FRMSTORE_OFFSET, 0x01);
vdma_write(XAXIVDMA_MM2S_ADDR_OFFSET | XAXIVDMA_START_ADDR_OFFSET, DAC_DDR_BASEADDR);
vdma_write(XAXIVDMA_MM2S_ADDR_OFFSET | XAXIVDMA_STRD_FRMDLY_OFFSET, tx_count * 8);
vdma_write(XAXIVDMA_MM2S_ADDR_OFFSET | XAXIVDMA_HSIZE_OFFSET, tx_count * 8);
vdma_write(XAXIVDMA_MM2S_ADDR_OFFSET | XAXIVDMA_VSIZE_OFFSET, 1);
dac_write(ADI_REG_CNTRL_2, ADI_DATA_SEL(DATA_SEL_DMA));
break;
default:
break;
}
dac_write(ADI_REG_CNTRL_1, ADI_ENABLE);
}
