/* Application entry point */
int main() {
Xil_ExceptionDisable();
#ifdef USE_FREERTOS
BaseType_t stat;
/* Create the tasks */
stat = xTaskCreate(communication_task, ( const char * ) "HW2",
1024, NULL,2,&comm_task);
if(stat != pdPASS)
return -1;
stat = xTaskCreate(matrix_mul, ( const char * ) "HW2",
1024, NULL, 1, &mat_mul );
if(stat != pdPASS)
return -1;
/*Create Queues*/
mat_mul_queue = xQueueCreate( 1, sizeof( queue_data ) );
OpenAMPInstPtr.send_queue = xQueueCreate( 1, sizeof( queue_data ) );
env_create_sync_lock(&OpenAMPInstPtr.lock,LOCKED);
/* Start the tasks and timer running. */
vTaskStartScheduler();
while(1);
#else
/*Create Queues*/
mat_mul_queue = pq_create_queue();
OpenAMPInstPtr.send_queue = pq_create_queue();
communication_task();
#endif
return 0;
}
int zynqMP_r5_gic_initialize() {
u32 Status;
Xil_ExceptionDisable();
XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) zynqMP_r5_irq_isr,
&InterruptController);
Xil_ExceptionEnable();
return 0;
}
//----------------------------------------------------------------------------------------------------//
// @func - hw_init
//! @desc
//! PPC405 hardware specific initialization
//! - Initialize PPC exception handling mechanism
//! - If an interrupt controller is present, register interrupt controller handler
//! as the external interrupt handler.
//! - Register PPC timer interrupt handler as the handler for the PPC PIT interrupt
//! @param
//! - none
//! @return
//! - nothing
//! @note
//! - none
//----------------------------------------------------------------------------------------------------//
void hw_init(void)
{
Xil_ExceptionInit(); // Initialize exception handling
Xil_ExceptionDisable();
#ifdef CONFIG_INTC
int_system_init();
#endif
Xil_ExceptionRegisterHandler(PIT_INT, (Xil_ExceptionHandler)timer_int_handler, (void *)0); // Register PIT interrupt handler
pit_initialize (SYSTMR_INTERVAL); // use SYSTMR_INTERVAL as configured in MSS
}
/**
* @brief init_irq() - Initialize GIC and connect IPI interrupt
* This function will initialize the GIC and connect the IPI
* interrupt.
*
* @return 0 - succeeded, non-0 for failures
*/
int init_irq()
{
int ret = 0;
XScuGic_Config *IntcConfig; /* The configuration parameters of
* the interrupt controller */
Xil_ExceptionDisable();
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return (int)XST_FAILURE;
}
ret = XScuGic_CfgInitialize(&xInterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (ret != XST_SUCCESS) {
return (int)XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
&xInterruptController);
Xil_ExceptionEnable();
/* Connect IPI Interrupt ID with libmetal ISR */
XScuGic_Connect(&xInterruptController, IPI_IRQ_VECT_ID,
(Xil_ExceptionHandler)metal_xlnx_irq_isr,
(void *)IPI_IRQ_VECT_ID);
XScuGic_Enable(&xInterruptController, IPI_IRQ_VECT_ID);
return 0;
}
/* Interrupt Controller setup */
static int app_gic_initialize(void)
{
u32 Status;
XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
Xil_ExceptionDisable();
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&xInterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,&xInterruptController);
Xil_ExceptionEnable();
/* Connect Interrupt ID with ISR */
XScuGic_Connect(&xInterruptController, VRING1_IPI_INTR_VECT,
(Xil_ExceptionHandler)bm_env_isr,
(void *)VRING1_IPI_INTR_VECT);
return 0;
}
/*-----------------------------------------------------------------------------*
* Application entry point
*-----------------------------------------------------------------------------*/
int main(void)
{
BaseType_t stat;
Xil_ExceptionDisable();
/* Create the tasks */
stat = xTaskCreate(mat_mul_demo, ( const char * ) "HW2",
1024, NULL, 2, &comm_task);
if (stat != pdPASS) {
xil_printf("Error: cannot create task\n");
} else {
/* Start running FreeRTOS tasks */
vTaskStartScheduler();
}
/* Will not get here, unless a call is made to vTaskEndScheduler() */
while (1) {
__asm__("wfi\n\t");
}
/* suppress compilation warnings*/
return 0;
}
/**
*
* This function is the main entry point for the MST/SST example using the
* XDpTxSs driver.
*
* @param DeviceId is the unique device ID of the DisplayPort TX
* Subsystem core.
*
* @return
* - XST_SUCCESS if DisplayPort TX Subsystem configured in SST/MST
* successfully.
* - XST_FAILURE, if DisplayPort TX Subsystem failed to configure
* in SST/MST.
*
* @note None.
*
******************************************************************************/
u32 DpTxSs_MstExample(u16 DeviceId)
{
u32 Status;
u8 VSplitMode = 0;
XDpTxSs_Config *ConfigPtr;
/* Do platform initialization in this function. This is hardware
* system specific. It is up to the user to implement this function.
*/
xil_printf("PlatformInit\n\r");
Status = DpTxSs_PlatformInit();
if (Status != XST_SUCCESS) {
xil_printf("Platform init failed!\n\r");
}
xil_printf("Platform initialization done.\n\r");
/* Obtain the device configuration for the DisplayPort TX Subsystem */
ConfigPtr = XDpTxSs_LookupConfig(DeviceId);
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the DpTxSsInst's Config
* structure. */
Status = XDpTxSs_CfgInitialize(&DpTxSsInst, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("DPTXSS config initialization failed.\n\r");
return XST_FAILURE;
}
/* Check for SST/MST support */
if (DpTxSsInst.UsrOpt.MstSupport) {
xil_printf("\n\rINFO:DPTXSS is MST enabled. DPTXSS can be "
"switched to SST/MST\n\r\n\r");
}
else {
xil_printf("\n\rINFO:DPTXSS is SST enabled. DPTXSS works "
"only in SST mode.\n\r\n\r");
}
/* Disable interrupts. */
Xil_ExceptionDisable();
/* Read capabilities of RX device */
Status = XDpTxSs_GetRxCapabilities(&DpTxSsInst);
if (Status != XST_SUCCESS) {
xil_printf("ERR: RX device is not connected.\r\n");
/* Enable interrupts. */
Xil_ExceptionEnable();
return XST_FAILURE;
}
/* Set Link rate and lane count to maximum */
XDpTxSs_SetLinkRate(&DpTxSsInst, DPTXSS_LINK_RATE);
XDpTxSs_SetLaneCount(&DpTxSsInst, DPTXSS_LANE_COUNT);
/* Set video mode */
XDpTxSs_SetVidMode(&DpTxSsInst, DPTXSS_VID_MODE);
/* Set BPC */
XDpTxSs_SetBpc(&DpTxSsInst, DPTXSS_BPC);
/* Check whether DPTXSS and RX device is in MST */
Status = XDpTxSs_IsMstCapable(&DpTxSsInst);
if (DpTxSsInst.UsrOpt.MstSupport && DPTXSS_MST &&
(Status == XST_SUCCESS)) {
/* Set DPTXSS in MST mode */
XDpTxSs_SetTransportMode(&DpTxSsInst, 1);
}
else {
/* Set DPTXSS in SST mode */
XDpTxSs_SetTransportMode(&DpTxSsInst, 0);
}
/* Start DPTXSS parameters set */
Status = XDpTxSs_Start(&DpTxSsInst);
if (Status != XST_SUCCESS) {
xil_printf("ERR:DPTX SS start failed\n\r");
/* Enable interrupts. */
Xil_ExceptionEnable();
return XST_FAILURE;
}
if ((DpTxSsInst.UsrOpt.VmId == (XVIDC_VM_UHD2_60_P)) &&
(DpTxSsInst.UsrOpt.MstSupport)) {
VSplitMode = 1;
}
else {
VSplitMode = 0;
}
/* Do stream setup in this function. It is up to the user to implement
* this function.
*/
DpTxSs_StreamSrc(VSplitMode);
/* Enable interrupts. */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function is the primary interrupt handler for the driver. It must be
* connected to the interrupt source such that is called when an interrupt of
* the interrupt controller is active. It will resolve which interrupts are
* active and enabled and call the appropriate interrupt handler. It uses
* the AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized.It does not verify that entries in the table are valid before
* calling an interrupt handler. In Cascade mode this function calls
* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
* This functions also handles interrupts nesting by saving and restoring link
* register of Microblaze and Interrupt Level register of interrupt controller
* properly.
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller. Note that even though the
* argument is a void pointer, the value is not a pointer but the
* actual device ID. The void pointer type is necessary to meet
* the XInterruptHandler typedef for interrupt handlers.
*
* @return None.
*
* @note For nested interrupts, this function saves microblaze r14
* register on entry and restores on exit. This is required since
* compiler does not support nesting. This function enables
* Microblaze interrupts after blocking further interrupts
* from the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
*
******************************************************************************/
void XIntc_DeviceInterruptHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
XIntc_Config *CfgPtr;
u32 Imr;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
XIntc_CascadeHandler(DeviceId);
}
else
#endif
{ /* This extra brace is required for compilation in Cascade Mode */
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
volatile u32 R14_register;
/* Save r14 register */
R14_register = mfgpr(r14);
#endif
volatile u32 ILR_reg;
/* Save ILR register */
ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
#endif
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
#if XPAR_XINTC_HAS_ILR == TRUE
/* Write to ILR the current interrupt
* number
*/
Xil_Out32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET, IntrNumber);
/* Read back ILR to ensure the value
* has been updated and it is safe to
* enable interrupts
*/
Xil_In32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET);
/* Enable interrupts */
Xil_ExceptionEnable();
#endif
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
/* If the interrupt has been setup to
* acknowledge it after it has been serviced
* then ack it
*/
if ((CfgPtr->AckBeforeService &
IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
#if XPAR_XINTC_HAS_ILR == TRUE
/* Disable interrupts */
Xil_ExceptionDisable();
/* Restore ILR */
Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
ILR_reg);
#endif
/*
* Read the ISR again to handle architectures
* with posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to
* be serviced, exit loop and return after
* servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all
* interrupts have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
}
}
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
*/
void _profile_clean( void )
{
Xil_ExceptionDisable();
disable_timer();
}
//----------------------------------------------------------------------------------------------------//
// @func - xmk_enter_kernel
//! @desc
//! Lock kernel by turning off ALL system interrupts
//! @return
//! - Nothing
//! @note
//! - Locks kernel against ALL interrupts.
//! - Does not lock against critical interrupts.
//----------------------------------------------------------------------------------------------------//
inline void xmk_enter_kernel (void)
{
Xil_ExceptionDisable(); // Does not disable critical interrupt though
}
XStatus
emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
{
struct pbuf *q;
int n_pbufs;
XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL;
XStatus Status;
XEmacPs_BdRing *txring;
unsigned int BdIndex;
unsigned int Index;
u32 RegVal;
u32 Cntr;
unsigned int *Temp;
Xil_ExceptionDisable();
#ifdef PEEP
while((XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress, XEMACPS_TXSR_OFFSET)) & 0x08);
#endif
txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
/* first count the number of pbufs */
for (q = p, n_pbufs = 0; q != NULL; q = q->next)
n_pbufs++;
/* obtain as many BD's */
Status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
if (Status != XST_SUCCESS) {
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
Xil_ExceptionEnable();
return ERR_IF;
}
for(q = p, txbd = txbdset; q != NULL; q = q->next) {
BdIndex = XEMACPS_BD_TO_INDEX(txring, txbd);
if (tx_pbufs_storage[BdIndex] != 0) {
Xil_ExceptionEnable();
LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
return ERR_IF;
}
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
Xil_DCacheFlushRange((unsigned int)q->payload, (unsigned)q->len);
XEmacPs_BdSetAddressTx(txbd, (u32)q->payload);
if (q->len > (XEMACPS_MAX_FRAME_SIZE - 18))
XEmacPs_BdSetLength(txbd, (XEMACPS_MAX_FRAME_SIZE - 18) & 0x3FFF);
else
XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
tx_pbufs_storage[BdIndex] = (int)q;
pbuf_ref(q);
last_txbd = txbd;
XEmacPs_BdClearLast(txbd);
dmb();
dsb();
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdSetLast(last_txbd);
for (txbd = txbdset, Cntr = n_pbufs; Cntr != 0; Cntr--) {
XEmacPs_BdClearTxUsed(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
dmb();
dsb();
Status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
if (Status != XST_SUCCESS) {
Xil_ExceptionEnable();
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
return ERR_IF;
}
/* Start transmit */
XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
dmb();
dsb();
Xil_ExceptionEnable();
return Status;
}
