int main (void) {
/*
* Enable and initialize cache
*/
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheInvalidate();
Xil_ICacheEnable();
#endif
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0x84c00000 (FLASH_2Mx16)
* because it is a read-only memory
*/
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheDisable();
Xil_DCacheInvalidate();
#endif
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheDisable();
Xil_ICacheInvalidate();
#endif
print("-- Exiting main() --\r\n");
return 0;
}
int main(void)
{
microblaze_disable_interrupts();
#if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
{
Xil_ICacheInvalidate();
Xil_ICacheEnable();
}
#endif
#if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
{
Xil_DCacheInvalidate();
Xil_DCacheEnable();
}
#endif
// Before a queue is used it must be explicitly created. The queue is
// created to hold a maximum of 5 character pointers.
xPrintQueue = xQueueCreate(5, sizeof(char*));
// The tasks are going to use a pseudo random delay, seed the random number
// generator.
srand(567);
// Check the queue was created successfully.
if (xPrintQueue != NULL)
{
// Create two instances of the tasks that send messages to the gatekeeper.
// The index to the string the task uses is passed to the task via the
// task parameter (the 4th parameter to xTaskCreate()). The tasks are
// created at different priorities so the higher priority task will
// occasionally preempt the lower priority task.
xTaskCreate(prvPrintTask, "Print1", configMINIMAL_STACK_SIZE, (void*)0,
tskIDLE_PRIORITY+1, NULL);
xTaskCreate(prvPrintTask, "Print2", configMINIMAL_STACK_SIZE, (void*)1,
tskIDLE_PRIORITY+2, NULL);
// Create the gatekeeper task. This is the only task that is permitted
// to directly access standard out.
xTaskCreate(prvStdioGatekeeperTask, "Gatekeeper", configMINIMAL_STACK_SIZE,
NULL, tskIDLE_PRIORITY, NULL);
// Start the scheduler so the created tasks start executing.
vTaskStartScheduler();
}
// If all is well then main() will never reach here as the scheduler will
// now be running the tasks. If main() does reach here then it is likely
// that there was insufficient heap memory available for the idle task
// to be created. Chapter 5 provides more information on memory management.
for (;;);
return 0;
}
int main(void)
{
microblaze_disable_interrupts();
#if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
{
Xil_ICacheInvalidate();
Xil_ICacheEnable();
}
#endif
#if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
{
Xil_DCacheInvalidate();
Xil_DCacheEnable();
}
#endif
// The queue is created to hold a maximum of 3 structures of type xData.
xQueue = xQueueCreate(3, sizeof(xData));
if (xQueue != NULL)
{
// Create two instances of the task that will write to the queue. The
// parameter is used to pass the structure that the task will write to
// the queue, so one task will continuously send xStructsToSend[0] to
// the queue while the other task will continuously send xStructsSend[1].
// Both tasks are created at priority 2 which is above the priority of
// the receiver.
xTaskCreate(vSenderTask, "Sender1", configMINIMAL_STACK_SIZE,
(void*)&xStructsToSend[0], tskIDLE_PRIORITY+2, NULL);
xTaskCreate(vSenderTask, "Sender2", configMINIMAL_STACK_SIZE,
(void*)&xStructsToSend[1], tskIDLE_PRIORITY+2, NULL);
// Create the task that will read from the queue. The task is created
// with priority 1, so below the priority of the sender tasks.
xTaskCreate(vReceiverTask, "Receiver", configMINIMAL_STACK_SIZE,
NULL, tskIDLE_PRIORITY+1, NULL);
// Start the scheduler so the created tasks start executing.
vTaskStartScheduler();
}
else
{
// The queue could not be created.
}
// If all is well then main() will never reach here as the scheduler will
// now be running the tasks. If main() does reach here then it is likely
// that there was insufficient heap memory available for the idle task to
// be created. Chapter 5 provides more information on memory management.
for (;;);
return 0;
}
/*****************************************************************************
*
* Invalidate the caches, enable MMU and D Caches for Cortex A53 processor.
*
* @param None.
* @return None.
*
******************************************************************************/
void Xil_EnableMMU(void)
{
u32 Reg;
Xil_DCacheInvalidate();
Xil_ICacheInvalidate();
Reg = mfcp(XREG_CP15_SYS_CONTROL);
Reg |= (u32)0x05U;
mtcp(XREG_CP15_SYS_CONTROL, Reg);
dsb();
isb();
}
int main(void)
{
int Status;
#ifdef XPAR_XUARTNS550_NUM_INSTANCES
XUartNs550_SetBaud(STDIN_BASEADDRESS, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(STDIN_BASEADDRESS, XUN_LCR_8_DATA_BITS);
#endif
#if XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheInvalidate();
Xil_ICacheEnable();
#endif
#if XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
AxiEthernetUtilErrorTrap("\r\n--- Enter main() ---");
AxiEthernetUtilErrorTrap("This test may take several minutes to finish");
/*
* Call the Axi Ethernet vlan example main function
*/
Status = AxiEthernetExtVlanExample(&IntcInstance,
&AxiEthernetInstance,
&DmaInstance,
AXIETHERNET_DEVICE_ID,
AXIDMA_DEVICE_ID,
AXIETHERNET_IRPT_INTR,
DMA_RX_IRPT_INTR,
DMA_TX_IRPT_INTR);
if (Status != XST_SUCCESS) {
AxiEthernetUtilErrorTrap("Failed test intr sgdma");
AxiEthernetUtilErrorTrap("--- Exiting main() ---");
return XST_FAILURE;
}
AxiEthernetUtilErrorTrap("Test passed");
AxiEthernetUtilErrorTrap("--- Exiting main() ---");
return XST_SUCCESS;
}
/*****************************************************************************
*
* Invalidate the caches, enable MMU and D Caches for Cortex A9 processor.
*
* @param None.
* @return None.
*
******************************************************************************/
void Xil_EnableMMU(void)
{
u32 Reg;
Xil_DCacheInvalidate();
Xil_ICacheInvalidate();
#ifdef __GNUC__
Reg = mfcp(XREG_CP15_SYS_CONTROL);
#else
{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
Reg = Cp15Reg; }
#endif
Reg |= 0x05;
mtcp(XREG_CP15_SYS_CONTROL, Reg);
dsb();
isb();
}
int main(void)
{
microblaze_disable_interrupts();
#if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
{
Xil_ICacheInvalidate();
Xil_ICacheEnable();
}
#endif
#if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
{
Xil_DCacheInvalidate();
Xil_DCacheEnable();
}
#endif
// Create the first task at priority 2. The task parameter is not used
// and set to NULL. The task handle is also not used so is also set to NULL.
xTaskCreate(vTask1, "Task 1", configMINIMAL_STACK_SIZE, NULL,
tskIDLE_PRIORITY+2, NULL);
// The task is created at priority 2-----^
// Create the second task at priority 1 - which is lower than the priority
// given to Task 1. Again the task parameter is not used so is set to NULL -
// BUT this time the task handle is required so the address of xTask2Handle
// is passed int the last parameter.
xTaskCreate(vTask2, "Task 2", configMINIMAL_STACK_SIZE, NULL,
tskIDLE_PRIORITY+1, &xTask2Handle);
// The task handle is the last parameter ___^^^^^^^^^^^^^
// Start the scheduler so the tasks start executing.
vTaskStartScheduler();
// If all is well the main() will never reach here as the scheduler will
// now be running the tasks. If main() does reach here then it is likely
// that there was insufficient heap memory available for the idle task to
// be created. Chapter 5 provides more information on memory management.
for (;;);
return 0;
}
/**
* @brief Set the memory attributes for a section of memory in the
* translation table.
*
* @param Addr: 32-bit address for which memory attributes need to be set..
* @param size: size is the size of the region.
* @param attrib: Attribute for the given memory region.
* @return None.
*
*
******************************************************************************/
u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
{
u32 Regionsize = 0;
INTPTR Localaddr = addr;
u32 NextAvailableMemRegion;
unsigned int i;
NextAvailableMemRegion = Xil_GetNextMPURegion();
if (NextAvailableMemRegion == 0xFF) {
xdbg_printf(DEBUG, "No regions available\r\n");
return XST_FAILURE;
}
Xil_DCacheFlush();
Xil_ICacheInvalidate();
mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
isb();
/* Lookup the size. */
for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
if (size <= region_size[i].size) {
Regionsize = region_size[i].encoding;
break;
}
}
Localaddr &= ~(region_size[i].size - 1);
Regionsize <<= 1;
Regionsize |= REGION_EN;
dsb();
mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */
mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */
mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/
dsb();
isb();
Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
return XST_SUCCESS;
}
int main( void )
{
microblaze_disable_interrupts();
#if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
{
Xil_ICacheInvalidate();
Xil_ICacheEnable();
}
#endif
#if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
{
Xil_DCacheInvalidate();
Xil_DCacheEnable();
}
#endif
// Start the two tasks
xTaskCreate(prvHelloWorld, "HW", configMINIMAL_STACK_SIZE, NULL,
mainHELLO_WORLD_TASK_PRIORITY, NULL);
xTaskCreate(prvGoodBye, "GB", configMINIMAL_STACK_SIZE, NULL,
mainGOOD_BYE_TASK_PRIORITY, NULL);
// Start the tasks and timer running
vTaskStartScheduler();
// If all is well, the scheduler will now be running, and the following line
// will never be reached. If the following line does execute, then there was
// insufficient FreeRTOS heap memory available for the idle and/or timer
// tasks to be created. See the memory management section on the FreeRTOS
// web site for more details.
for (;;);
return 0;
}
void platform_cache_all_flush_invalidate() {
Xil_DCacheFlush();
Xil_DCacheInvalidate();
Xil_ICacheInvalidate();
}
/**
* This main function starts the USB Intrerrupt example.
*
*
* @param None.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if test fails.
* @note None.
*
*****************************************************************************/
int main()
{
int Status;
int Index = 0;
int Cnt = 0;
/*
* Initialize the USB driver.
*/
UsbConfigPtr = XUsb_LookupConfig(USB_DEVICE_ID);
if (UsbConfigPtr == NULL) {
return XST_FAILURE;
}
#ifdef __PPC__
Xil_ICacheEnableRegion (0x80000001);
Xil_DCacheEnableRegion (0x80000001);
#endif
#ifdef __MICROBLAZE__
Xil_ICacheInvalidate();
Xil_ICacheEnable();
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
Status = XUsb_CfgInitialize(&UsbInstance,
UsbConfigPtr,
UsbConfigPtr->BaseAddress);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
/*
* Initialize the USB instance as required for the
* application.
*/
InitUsbInterface(&UsbInstance);
/*
* Set our function address to 0 which is the unenumerated state.
*/
Status = XUsb_SetDeviceAddress(&UsbInstance, 0);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
/*
* Setup the interrupt handlers.
*/
XUsb_IntrSetHandler(&UsbInstance, (void *) UsbIfIntrHandler,
&UsbInstance);
XUsb_EpSetHandler(&UsbInstance, 0,
(XUsb_EpHandlerFunc *) Ep0IntrHandler, &UsbInstance);
XUsb_EpSetHandler(&UsbInstance, 1,
(XUsb_EpHandlerFunc *) Ep1IntrHandler, &UsbInstance);
/*
* Setup the interrupt system.
*/
Status = SetupInterruptSystem(&UsbInstance);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts.
*/
XUsb_IntrEnable(&UsbInstance, XUSB_STATUS_GLOBAL_INTR_MASK |
XUSB_STATUS_RESET_MASK |
XUSB_STATUS_SUSPEND_MASK |
XUSB_STATUS_DISCONNECT_MASK |
XUSB_STATUS_FIFO_BUFF_RDY_MASK |
XUSB_STATUS_FIFO_BUFF_FREE_MASK |
XUSB_STATUS_EP0_BUFF1_COMP_MASK |
XUSB_STATUS_EP1_BUFF1_COMP_MASK |
XUSB_STATUS_EP2_BUFF1_COMP_MASK |
XUSB_STATUS_EP1_BUFF2_COMP_MASK |
XUSB_STATUS_EP2_BUFF2_COMP_MASK);
XUsb_Start(&UsbInstance);
/*
* Set the device configuration to unenumerated state.
*/
UsbInstance.DeviceConfig.CurrentConfiguration = 0;
/*
* Wait untill the USB device is enumerated.
*/
while (!UsbInstance.DeviceConfig.CurrentConfiguration);
/*
* Stop the test if the Stop key is pressed or
* device lost enumeration.
*/
while (1) {
if (UsbInstance.Config.DmaEnabled) {
/* Flush the cache before DMA transfer */
Xil_DCacheFlushRange((u32)&Hello_wav[Index],(u32)1024);
}
if (XUsb_EpDataSend(&UsbInstance, 1, &Hello_wav[Index],
1024) == XST_SUCCESS){
Index += 1024;
Cnt ++;
if (Cnt >= 9000){
Cnt =0;
Index = 0;
}
}
}
return XST_SUCCESS;
}
int main (void) {
static XIntc intc;
/*
* Enable and initialize cache
*/
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheInvalidate();
Xil_ICacheEnable();
#endif
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
static XLlTemac Hard_Ethernet_MAC_LlTemac;
static XLlDma Hard_Ethernet_MAC_LlDma;
/* Initialize RS232_Uart_1 - Set baudrate and number of stop bits */
XUartNs550_SetBaud(XPAR_RS232_UART_1_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(XPAR_RS232_UART_1_BASEADDR, XUN_LCR_8_DATA_BITS);
static XUartNs550 RS232_Uart_2_UartNs550;
static XTmrCtr xps_timer_0_Timer;
print("-- Entering main() --\r\n");
{
int status;
print("\r\n Running IntcSelfTestExample() for xps_intc_0...\r\n");
status = IntcSelfTestExample(XPAR_XPS_INTC_0_DEVICE_ID);
if (status == 0) {
print("IntcSelfTestExample PASSED\r\n");
}
else {
print("IntcSelfTestExample FAILED\r\n");
}
}
{
int Status;
Status = IntcInterruptSetup(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
if (Status == 0) {
print("Intc Interrupt Setup PASSED\r\n");
}
else {
print("Intc Interrupt Setup FAILED\r\n");
}
}
{
u32 status;
print("\r\nRunning GpioOutputExample() for LEDs_8Bit...\r\n");
status = GpioOutputExample(XPAR_LEDS_8BIT_DEVICE_ID,8);
if (status == 0) {
print("GpioOutputExample PASSED.\r\n");
}
else {
print("GpioOutputExample FAILED.\r\n");
}
}
{
u32 status;
print("\r\nRunning GpioOutputExample() for LEDs_Positions...\r\n");
status = GpioOutputExample(XPAR_LEDS_POSITIONS_DEVICE_ID,5);
if (status == 0) {
print("GpioOutputExample PASSED.\r\n");
}
else {
print("GpioOutputExample FAILED.\r\n");
}
}
{
u32 status;
print("\r\nRunning GpioInputExample() for Push_Buttons_5Bit...\r\n");
u32 DataRead;
status = GpioInputExample(XPAR_PUSH_BUTTONS_5BIT_DEVICE_ID, &DataRead);
if (status == 0) {
xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
}
else {
print("GpioInputExample FAILED.\r\n");
}
}
{
u32 status;
print("\r\nRunning GpioInputExample() for DIP_Switches_8Bit...\r\n");
u32 DataRead;
status = GpioInputExample(XPAR_DIP_SWITCHES_8BIT_DEVICE_ID, &DataRead);
if (status == 0) {
xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
}
else {
print("GpioInputExample FAILED.\r\n");
}
}
{
int status;
print("\r\n Running IicSelfTestExample() for IIC_EEPROM...\r\n");
status = IicSelfTestExample(XPAR_IIC_EEPROM_DEVICE_ID);
if (status == 0) {
print("IicSelfTestExample PASSED\r\n");
}
else {
print("IicSelfTestExample FAILED\r\n");
}
}
/* TemacPolledExample does not support SGDMA
{
XStatus status;
print("\r\n Running TemacPolledExample() for Hard_Ethernet_MAC...\r\n");
status = TemacPolledExample( XPAR_HARD_ETHERNET_MAC_CHAN_0_DEVICE_ID,
);
if (status == 0) {
print("TemacPolledExample PASSED\r\n");
}
else {
print("TemacPolledExample FAILED\r\n");
}
}
*/
{
XStatus Status;
print("\r\nRunning TemacSgDmaIntrExample() for Hard_Ethernet_MAC...\r\n");
Status = TemacSgDmaIntrExample(&intc, &Hard_Ethernet_MAC_LlTemac,
&Hard_Ethernet_MAC_LlDma,
XPAR_HARD_ETHERNET_MAC_CHAN_0_DEVICE_ID,
XPAR_XPS_INTC_0_HARD_ETHERNET_MAC_TEMACINTC0_IRPT_INTR,
XPAR_LLTEMAC_0_LLINK_CONNECTED_DMARX_INTR,
XPAR_LLTEMAC_0_LLINK_CONNECTED_DMATX_INTR);
if (Status == 0) {
print("Temac Interrupt Test PASSED.\r\n");
}
else {
print("Temac Interrupt Test FAILED.\r\n");
}
}
{
int status;
print("\r\nRunning SysAceSelfTestExample() for SysACE_CompactFlash...\r\n");
status = SysAceSelfTestExample(XPAR_SYSACE_COMPACTFLASH_DEVICE_ID);
if (status == 0) {
print("SysAceSelfTestExample PASSED\r\n");
}
else {
print("SysAceSelfTestExample FAILED\r\n");
}
}
/*
* Peripheral SelfTest will not be run for RS232_Uart_1
* because it has been selected as the STDOUT device
*/
{
XStatus status;
print("\r\nRunning UartNs550SelfTestExample() for RS232_Uart_2...\r\n");
status = UartNs550SelfTestExample(XPAR_RS232_UART_2_DEVICE_ID);
if (status == 0) {
print("UartNs550SelfTestExample PASSED\r\n");
}
else {
print("UartNs550SelfTestExample FAILED\r\n");
}
}
{
XStatus Status;
print("\r\n Running Interrupt Test for RS232_Uart_2...\r\n");
Status = UartNs550IntrExample(&intc, &RS232_Uart_2_UartNs550, \
XPAR_RS232_UART_2_DEVICE_ID, \
XPAR_XPS_INTC_0_RS232_UART_2_IP2INTC_IRPT_INTR);
if (Status == 0) {
print("UartNs550 Interrupt Test PASSED\r\n");
}
else {
print("UartNs550 Interrupt Test FAILED\r\n");
}
}
{
int status;
print("\r\n Running TmrCtrSelfTestExample() for xps_timer_0...\r\n");
status = TmrCtrSelfTestExample(XPAR_XPS_TIMER_0_DEVICE_ID, 0x0);
if (status == 0) {
print("TmrCtrSelfTestExample PASSED\r\n");
}
else {
print("TmrCtrSelfTestExample FAILED\r\n");
}
}
{
int Status;
print("\r\n Running Interrupt Test for xps_timer_0...\r\n");
Status = TmrCtrIntrExample(&intc, &xps_timer_0_Timer, \
XPAR_XPS_TIMER_0_DEVICE_ID, \
XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR, 0);
if (Status == 0) {
print("Timer Interrupt Test PASSED\r\n");
}
else {
print("Timer Interrupt Test FAILED\r\n");
}
}
{
int status;
print("\r\nRunning UartLiteSelfTestExample() for mdm_0...\r\n");
status = UartLiteSelfTestExample(XPAR_MDM_0_DEVICE_ID);
if (status == 0) {
print("UartLiteSelfTestExample PASSED\r\n");
}
else {
print("UartLiteSelfTestExample FAILED\r\n");
}
}
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheDisable();
Xil_DCacheInvalidate();
#endif
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheDisable();
Xil_ICacheInvalidate();
#endif
print("-- Exiting main() --\r\n");
return 0;
}
/**
*
* Main function for the CPRI emulation test
*
****************************************************************************/
int main(void) {
int Status;
#if XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheInvalidate();
Xil_ICacheEnable();
#endif
#if XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
xil_printf("\r\n------ UFA13 - Radio over Ethernet ------r\n");
xil_printf("Initializing Modules and Peripherals\r\n");
/*
* Init Interrupt Controller
*/
Status = initIntc();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Init AXI Ethernet
*/
//#ifndef ROE_BYPASS_FRONTHAUL
// Status = initAxiEthernet(AXIETHERNET_DEVICE_ID, FIFO_DEVICE_ID);
// if (Status != XST_SUCCESS) {
// AxiEthernetUtilErrorTrap("Failed test poll mode fifo");
// return XST_FAILURE;
// }
//#endif
/*
* Setup interrupts
*/
//#if SI_5324 == 1
//
// // Setup the interrupts for the IIC and Si5324
// if (SetUpInterruptSystem(IIC_INTR_ID,
// (XInterruptHandler) XIic_InterruptHandler,
// (void *) &IicInstance) != XST_SUCCESS)
// return XST_FAILURE;
//
// /*
// * Run the Si5324 IIC configuration.
// */
// Status = initIicEeprom();
// if (Status != XST_SUCCESS) {
// return XST_FAILURE;
// }
//
// init_clock(clock);
// // Wait enough for the clock to lock before starting the CPRI emulator
// MB_Sleep(10000);
//
//#elif ~SI_5324 && RRU_MODE
// /*
// * Init Clock Wizard Configuration
// * (Old) Note: do this before initializing the interrupt controller,
// * since the ISR requires the global clock struct pointer.
// */
// init_clock(clock);
//#endif
//#if SYNC_MODE == PTP
// /*
// * Init AVB
// */
// Status = initAvb(ETH_SYSTEM_ADDRESS_EUI48_HIGH,
// ETH_SYSTEM_ADDRESS_EUI48_LOW);
// if (Status != XST_SUCCESS) {
// AxiEthernetUtilErrorTrap("Failed to initialize AVB mode");
// return XST_FAILURE;
// }
//#endif
//#if (ROE_CPRI_SRC == ROE_SRC_ADC || ROE_CPRI_SINK == ROE_SINK_DAC) && RRU_MODE
// // Wait for PTP (if being used) to lock before initialize AD9361
// xil_printf("Waiting PTP to lock...\r\n");
// while (ptp_lock_countdown != 0) {
// }
// xil_printf("\r\n");
//#if SYNC_MODE == PTP
// // Disable all PTP interrupts while initialize AD9361
// disableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_PTP_TX_VEC_ID);
// disableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_PTP_RX_VEC_ID);
// disableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_10MS_VEC_ID);
//#endif
Status = initAd9361();
if (Status != XST_SUCCESS) {
xil_printf("Failed to initialize AD 9361");
return XST_FAILURE;
}
//#if SYNC_MODE == PTP
// // Re-enable PTP interrupts
// enableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_PTP_TX_VEC_ID);
// enableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_PTP_RX_VEC_ID);
// enableInterrupt(XPAR_INTC_0_AXIETHERNET_0_AV_INTERRUPT_10MS_VEC_ID);
//#endif
//#endif
//#if ROE_CPRI_SRC == ROE_SRC_DMA || ROE_CPRI_SINK == ROE_SINK_DMA
Status = initAXIDma();
if (Status != XST_SUCCESS) {
xil_printf("Failed to initialize AXI DMA");
return XST_FAILURE;
}
//#endif
/*
* Radio over Ethernet Configuration
*/
// Reset
//RoE_reset();
// Setup RoE Interrupts
//#if SYNC_MODE == BUFFER_BASED
// if (SetUpInterruptSystem(ROE_INTR_ID,
// (XInterruptHandler) RoE_interruptHandler, (void *) 0) != XST_SUCCESS)
// return XST_FAILURE;
//#endif
// Define the CPRI control word
//RoE_setCpriControlWord();
//#ifndef ROE_BYPASS_FRONTHAUL
// // Set EtherType filters for demux
// //RoE_setEthTypeFilters();
//
// // Initialize "CPRI to Ethernet" module
// //RoE_initCpri2Ethernet(ROE_FLOW_CONTROL);
//#endif
//
//#if ROE_CPRI_SRC == ROE_SRC_DMA
// Fire a transmission
Status = startCyclicDmaRead();
if (Status != XST_SUCCESS) {
xil_printf("Failed to transmit data via DMA");
return XST_FAILURE;
}
//#else
// // Initialize CPRI Emulation:
// RoE_initCpriEmulator();
//#endif
// Poll RoE status forever:
//RoE_pollStatus();
return XST_SUCCESS;
}
int main(void)
{
XPeriph *PeriphPtr;
XVprocSs *VpssPtr;
vpssVidio *thisCase;
int status, cnt;
u32 Timeout;
static int Lock = FALSE;
/* Bind instance pointer with definition */
PeriphPtr = &PeriphInst;
VpssPtr = &VprocInst;
/* Initialize ICache */
Xil_ICacheInvalidate();
Xil_ICacheEnable();
/* Initialize DCache */
Xil_DCacheInvalidate();
Xil_DCacheEnable();
xil_printf("\r\n--------------------------------------------------------\r\n");
xil_printf(" Video Processing Subsystem Example Design %s\r\n", XVPROCSS_SW_VER);
xil_printf(" (c) 2015, 2016 by Xilinx Inc.\r\n");
status = XSys_Init(PeriphPtr, VpssPtr);
if(status != XST_SUCCESS)
{
xil_printf("CRITICAL ERR:: System Init Failed. Cannot recover from this error. Check HW\n\r");
}
/* Based on the customized Video Processing Subsystem functionality
* the video input and output formats are chosen.
*/
cnt = 0;
while (cnt < USECASE_COUNT) {
xil_printf("--------------------------------------------------------\r\n");
printf("Topology is %s, case %d\r\n",topo_name[VpssPtr->Config.Topology],cnt+1);
thisCase = &useCase[VpssPtr->Config.Topology][cnt];
switch (VpssPtr->Config.Topology) {
case XVPROCSS_TOPOLOGY_SCALER_ONLY:
// In Scaler-only mode only the picture size may change
// Choose video format based on the "422 Enabled" option
// Video In: 720P Video Out: 1080P
thisCase->Cformat_in = XV_HscalerIs422Enabled(VpssPtr->HscalerPtr)?
XVIDC_CSF_YCRCB_422:
XVIDC_CSF_YCRCB_444;
thisCase->Cformat_out = thisCase->Cformat_in;
break;
case XVPROCSS_TOPOLOGY_FULL_FLEDGED:
// Full Fledged mode may deinterlace, change picture size and/or color format.
// In the Full Fledged configuration, the presence of a sub-core
// is indicated by a non-NULL pointer to the sub-core driver instance.
// If there is no Deinterlacer AND 420 input is supported (Vcr present),
// choose progressive 420 input format
if ((VpssPtr->DeintPtr == NULL) &&
(VpssPtr->VcrsmplrInPtr != NULL)) {
// Video In: 720P 420 Video Out: 1080P RGB
thisCase->width_in = 1280;
thisCase->height_in = 720;
thisCase->Cformat_in = XVIDC_CSF_YCRCB_420;
thisCase->IsInterlaced = FALSE;
// If the Deinterlacer is present,
// choose 480i interlaced input 422 (Hcr present) or 444 (Hcr absent)
} else {
if (VpssPtr->DeintPtr != NULL) {
// Video In: 480i YUV Video Out: 1080P RGB
thisCase->width_in = 720;
thisCase->height_in = 240;
thisCase->Cformat_in = (VpssPtr->HcrsmplrPtr != NULL)?
XVIDC_CSF_YCRCB_422 : XVIDC_CSF_YCRCB_444;
thisCase->IsInterlaced = TRUE;
}
}
break;
default:
break;
}
printf ("Set up Video Input and Output streams.\r\n");
setup_video_io(PeriphPtr, VpssPtr, thisCase);
printf ("Start VPSS.\r\n");
status = start_system(PeriphPtr, VpssPtr);
//Query video processing subsystem configuration
XVprocSs_ReportSubsystemConfig(VpssPtr);
if(status == XST_SUCCESS)
{
//Configure and start VTC with output timing
printf ("Start VTC.\r\n");
XPeriph_ConfigVtc(PeriphPtr,
&VpssPtr->VidOut,
VprocInst.Config.PixPerClock);
//Configure and start the TPG
printf ("Start TPG.\r\n");
XPeriph_ConfigTpg(PeriphPtr);
/* check for output lock */
xil_printf("Waiting for lock... ");
Timeout = VIDEO_MONITOR_LOCK_TIMEOUT;
while(!Lock && Timeout) {
if(XPeriph_IsVideoLocked(PeriphPtr)) {
xil_printf("Locked.\r\n");
Lock = TRUE;
}
--Timeout;
}
if(!Timeout) {
xil_printf("\r\nTEST FAILED\r\n");
} else {
xil_printf("\r\nTEST PASSED\r\n\r\n");
}
xil_printf("Stop... ");
XVprocSs_Stop(VpssPtr);
// In the Deint-only configuration, it is necessary to allow
// some time for aximm traffic to stop, and the core to become idle
if (XVprocSs_IsConfigModeDeinterlaceOnly(VpssPtr)) {
if (XV_DeintWaitForIdle(VpssPtr->DeintPtr) == XST_SUCCESS)
xil_printf ("Deint subcore IDLE.\r\n");
else
xil_printf ("Error: Deint subcore NOT IDLE.\r\n");
}
} else {
xil_printf("\r\nERR:: VProcss Configuration Failed. \r\n");
xil_printf("\r\nTEST FAILED\r\n");
}
#if VERBOSE_MODE
XVprocSs_LogDisplay(VpssPtr);
#endif
xil_printf ("End testing this use case.\r\n");
Lock = FALSE;
cnt++;
}
while(1) {
//NOP
}
return 0;
}
/**
* This main function starts the USB application.
*
*
* @param None.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if test fails.
* @note None.
*
*****************************************************************************/
int main()
{
int Status;
u32 ReadRegData = 0;
/*
* Initialize the USB driver.
*/
UsbConfigPtr = XUsb_LookupConfig(USB_DEVICE_ID);
if (NULL == UsbConfigPtr) {
return XST_FAILURE;
}
#ifdef __PPC__
Xil_ICacheEnableRegion (0x80000001);
Xil_DCacheEnableRegion (0x80000001);
#endif
#ifdef __MICROBLAZE__
Xil_ICacheInvalidate();
Xil_ICacheEnable();
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
/*
* We are passing the physical base address as the third argument
* because the physical and virtual base address are the same in our
* example. For systems that support virtual memory, the third
* argument needs to be the virtual base address.
*/
Status = XUsb_CfgInitialize(&UsbInstance,
UsbConfigPtr, UsbConfigPtr->BaseAddress);
if (XST_SUCCESS != Status) {
return XST_FAILURE;
}
XUsb_UlpiIntrSetHandler (&UsbInstance, (void *) UsbIfPhyIntrHandler,
&UsbInstance);
/*
* Setup the interrupt system.
*/
Status = SetupInterruptSystem(&UsbInstance);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts.
*/
XUsb_IntrEnable(&UsbInstance, XUSB_STATUS_GLOBAL_INTR_MASK |
XUSB_STATUS_PHY_ACCESS_MASK);
XUsb_Start(&UsbInstance);
/*
* Initiate a ULPI register write transaction.
*/
XUsb_UlpiPhyWriteRegister(&UsbInstance, ULPI_SCRATCH_REGISTER,
WRITE_REG_DATA);
/* Wait until the write transaction is done */
while (!PhyAccessDone);
/*
* Read the PHY read register. We do not wait for transaction
* complete interrupt in this case. The API internally polls for the
* completion and then returns the register value read.
*/
ReadRegData = XUsb_UlpiPhyReadRegister(&UsbInstance,
ULPI_SCRATCH_REGISTER);
/* Compare the Written data and read data*/
if (ReadRegData != WRITE_REG_DATA) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* Disable the instruction cache.
*
* @param None
*
* @return None.
*
* @note
*
*
****************************************************************************/
void Xil_ICacheDisable(void)
{
Xil_ICacheInvalidate();
Xil_L1ICacheDisable();
}
/**
* Perform Xil_ICacheInvalidate().
*
* @return
*
* - 0 is returned for a pass
* The function will hang if it fails.
*/
int Xil_TestICacheAll(void)
{
Xil_ICacheInvalidate();
print("-- Invalidate icache all done --\r\n");
return 0;
}
/***************************************************************************
* This is the main thread that will do all initializations.
* It will call configure functions for all subsystems and system level
* peripherals
***************************************************************************/
int main(void)
{
XPeriph *PeriphPtr;
XVprocSs *VpssPtr;
int status;
u32 Timeout;
static int Lock = FALSE;
/* Bind instance pointer with definition */
PeriphPtr = &PeriphInst;
VpssPtr = &VprocInst;
/* Initialize ICache */
Xil_ICacheInvalidate();
Xil_ICacheEnable();
/* Initialize DCache */
Xil_DCacheInvalidate();
Xil_DCacheEnable();
xil_printf("\r\n--------------------------------------------------------\r\n");
xil_printf(" Video Processing Subsystem Example Design %s\r\n", XVPROCSS_SW_VER);
xil_printf(" (c) 2015 by Xilinx Inc.\r\n");
xil_printf("--------------------------------------------------------\r\n");
xil_printf("\r\nInitialize System Design...\r\n");
status = XSys_Init(PeriphPtr, VpssPtr);
if(status != XST_SUCCESS)
{
xil_printf("CRITICAL ERR:: System Init Failed. Cannot recover from this error. Check HW\n\r");
}
#if (VERBOSE_MODE == 1)
xil_printf("\r\nINFO> Setting up VPSS AXIS In/Out\r\n");
#endif
//Set TPG default parameters
XPeriph_SetTpgParams(PeriphPtr,
1920,
1080,
XVIDC_CSF_RGB,
XTPG_BKGND_COLOR_BARS,
FALSE);
//Set AXIS In to TPG settings
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_IN,
PeriphInst.TpgConfig.Width,
PeriphInst.TpgConfig.Height,
PeriphInst.TpgConfig.ColorFmt,
PeriphInst.TpgConfig.IsInterlaced);
if(VpssPtr->Config.Topology == XVPROCSS_TOPOLOGY_SCALER_ONLY)
{
/* Only Scaling Ratio can be changed. Stream out color format
* must be same as stream in
*/
//Set AXIS Out
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_OUT,
3840,
2160,
PeriphInst.TpgConfig.ColorFmt,
FALSE);
}
else //FULL_FLEDGED
{
//Set AXIS Out
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_OUT,
3840,
2160,
XVIDC_CSF_YCRCB_422,
FALSE);
}
//Configure video processing subsystem
status = XVprocSs_SetSubsystemConfig(VpssPtr);
//Query vpss configuration
XVprocSs_ReportSubsystemConfig(VpssPtr);
if(status == XST_SUCCESS)
{
//Configure VTC with output timing
XPeriph_ConfigVtc(PeriphPtr,
&VpssPtr->VidOut,
VprocInst.Config.PixPerClock);
//Config TPG for AXIS In
XPeriph_ConfigTpg(PeriphPtr);
#if (VERBOSE_MODE == 1)
XPeriph_TpgDbgReportStatus(PeriphPtr);
#endif
/* vtc is running at 9Mhz essentially providing < 2fps frame rate
* Need to wait for 3-4 frames (~2sec) for vidout to acquire lock
*/
xil_printf("\r\nWaiting for output to lock: ");
MB_Sleep(2000);
/* check for output lock */
Timeout = VIDEO_MONITOR_LOCK_TIMEOUT;
while(!Lock && Timeout)
{
if(XPeriph_IsVideoLocked(PeriphPtr))
{
xil_printf("Locked\r\n");
Lock = TRUE;
}
--Timeout;
}
if(!Timeout)
{
xil_printf("\r\nTEST FAILED\r\n");
}
else
{
xil_printf("\r\nTEST PASSED\r\n");
}
}
else
{
xil_printf("\r\nERR:: VProcss Configuration Failed. \r\n");
xil_printf("\r\nTEST FAILED\r\n");
}
while(1)
{
//NOP
}
/* Clean up DCache. For writeback caches, the disable_dcache routine
internally does the flush and invalidate. For write through caches,
an explicit invalidation must be performed on the entire cache. */
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 0
Xil_DCacheInvalidate ();
#endif
Xil_DCacheDisable ();
/* Clean up ICache */
Xil_ICacheInvalidate ();
Xil_ICacheDisable ();
return 0;
}