void config_filterVDMA(int VDMA_baseAddr, int vdma_direction, unsigned long base_address) { if(vdma_direction == DMA_DEV_TO_MEM) // from device to memory {// rx : S2MM /* FOR HDMI RELEVANT SETTINGS of VDMA*/ Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_CTRL), 0x00011003); // enable circular mode Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_START1), base_address); // start address // Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_START2), base_address); // start address // Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_START3), base_address); // start address Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_FRMDLY_STRIDE), (detailedTiming[currentResolution][H_ACTIVE_TIME]*4)); // h offset Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_HSIZE), (detailedTiming[currentResolution][H_ACTIVE_TIME]*4)); // h size Xil_Out32((VDMA_baseAddr + AXI_FILTER_RX_VSIZE), detailedTiming[currentResolution][V_ACTIVE_TIME]); // v size } else if (vdma_direction ==DMA_MEM_TO_DEV) // from memory to device {//tx : MM2S /* FOR HDMI RELEVANT SETTINGS of VDMA */ Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_CTRL), 0x00011003); // enable circular mode, genlock synEn Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_START1), base_address); // start address // Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_START2), base_address); // start address // Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_START3), base_address); // start address Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_FRMDLY_STRIDE), (detailedTiming[currentResolution][H_ACTIVE_TIME]*4)); // h offset Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_HSIZE), (detailedTiming[currentResolution][H_ACTIVE_TIME]*4)); // h size Xil_Out32((VDMA_baseAddr + AXI_FILTER_TX_VSIZE), detailedTiming[currentResolution][V_ACTIVE_TIME]); // v size } }
void PIC_Initialize() { //PIC_mWriteSlaveReg0(XPAR_PIC_0_BASEADDR, PIC_SLV_REG0_OFFSET, PIC_ENABLE); // Control register //PIC_mWriteSlaveReg1(XPAR_PIC_0_BASEADDR, PIC_SLV_REG0_OFFSET, PIC_CLOCKS_BETWEEN_STROBES); // Delay register Xil_Out32(XPAR_PIT_0_0_BASEADDR, PIC_ENABLE); Xil_Out32(XPAR_PIT_0_0_BASEADDR+4, clocks_between_strobes); }
int awdt_init(unsigned int seconds) { // set 2'b11 to RS_AWDT_CTRL // - unlock slcr first Xil_Out32(SLCR_UNLOCK, UNLOCK_KEY); unsigned int awdt_ctrl; Xil_Out32(RS_AWDT_CTRL, 0x3); awdt_ctrl = Xil_In32(RS_AWDT_CTRL); if (awdt_ctrl != 0x3) { printf("error, RS_AWDT_CTRL set unsuccessful\n\r"); sleep(2); exit(0); } // set initial load awdt_kick_seconds(seconds); // set watchdog control unsigned int wdt_control = 1 << WD_ENABLE_BIT | 0 << AUTO_RELOAD_BIT | 1 << WD_MODE_BIT | 0xFF << PRESCALER_BIT; Xil_Out32(WDT_CONTROL, wdt_control); return 0; }
/** * This function contains the implementation for updating the slcr mio registers * with reset values * @param N/A. * * @return N/A. * * @note None. * ******************************************************************************/ void XSlcr_MioWriteResetValues(void) { u32 i; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Update all the MIO registers with reset values */ for (i=0U; i<=1U;i++) { Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } for (; i<=8U;i++) { Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_02_RESET_VAL); } for (; i<=53U ;i++) { Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } }
/***************************************************************************//** * @brief Writes data to a slave device. * * @param slaveAddress - Adress of the slave device. * @param dataBuffer - Pointer to a buffer storing the transmission data. * @param bytesNumber - Number of bytes to write. * @param stopBit - Stop condition control. * Example: 0 - A stop condition will not be sent; * 1 - A stop condition will be sent. * * @return status - Number of read bytes or 0xFF if the slave address was not * acknowledged by the device. *******************************************************************************/ unsigned char I2C_Write(unsigned char slaveAddress, unsigned char* dataBuffer, unsigned char bytesNumber, unsigned char stopBit) { u32 txCnt = 0; /*!< Reset tx fifo */ Xil_Out32((I2C_BASEADDR + CR), 0x002); /*!< Enable iic */ Xil_Out32((I2C_BASEADDR + CR), 0x001); TIME_DelayMs(10); /*!< Set the I2C address */ Xil_Out32((I2C_BASEADDR + TX_FIFO), (0x100 | (slaveAddress << 1))); /*!< Write data to the I2C slave */ while(txCnt < bytesNumber) { /*!< Put the Tx data into the Tx FIFO */ Xil_Out32((I2C_BASEADDR + TX_FIFO), (txCnt == bytesNumber - 1) ? (0x200 | dataBuffer[txCnt]) : dataBuffer[txCnt]); txCnt++; } TIME_DelayMs(10); return txCnt; }
/**************************************************************************//** * @brief Writes data to an I2C slave. * * @param i2cAddr - The address of the I2C slave. * @param regAddr - Address of the I2C register to be read. * Must be set to -1 if it is not used. * @param txSize - Number of bytes to write to the slave. * @param txBuf - Buffer to store the data to be transmitted. * * @return Returns the number of bytes written. ******************************************************************************/ uint32_t I2C_Write_axi(uint32_t i2cAddr, uint32_t regAddr, uint32_t txSize, uint8_t* txBuf) { uint32_t txCnt = 0; uint32_t timeout = I2C_TIMEOUT; // Reset tx fifo Xil_Out32((axi_iic_baseaddr + CR), 0x002); // enable iic Xil_Out32((axi_iic_baseaddr + CR), 0x001); delay_us(I2C_DELAY); // Set the I2C address Xil_Out32((axi_iic_baseaddr + TX_FIFO), (0x100 | (i2cAddr << 1))); if(regAddr != -1) { // Set the slave register address Xil_Out32((axi_iic_baseaddr + TX_FIFO), regAddr); } // Write data to the I2C slave while((txCnt < txSize) && (timeout)) { timeout = I2C_TIMEOUT; // put the Tx data into the Tx FIFO Xil_Out32((axi_iic_baseaddr + TX_FIFO), (txCnt == txSize - 1) ? (0x200 | txBuf[txCnt]) : txBuf[txCnt]); while (((Xil_In32(axi_iic_baseaddr + SR) & 0x80) == 0x00) && (--timeout)); txCnt++; } delay_us(I2C_DELAY); return (timeout ? txCnt : 0); }
/**************************************************************************//** * @brief Writes data to an I2C slave. * * @param axiBaseAddr - Microblaze I2C peripheral AXI base address. * @param i2cAddr - The address of the I2C slave. * @param regAddr - Address of the I2C register to be read. * Must be set to -1 if it is not used. * @param txSize - Number of bytes to write to the slave. * @param txBuf - Buffer to store the data to be transmitted. * @return Returns the number of bytes written. ******************************************************************************/ u32 I2C_Write_axi(u32 axiBaseAddr, u32 i2cAddr, u32 regAddr, u32 txSize, unsigned char* txBuf) { u32 txCnt = 0; // Reset tx fifo Xil_Out32((axiBaseAddr + CR), 0x002); // enable iic Xil_Out32((axiBaseAddr + CR), 0x001); delay_ms(10); // Set the I2C address Xil_Out32((axiBaseAddr + TX_FIFO), (0x100 | (i2cAddr << 1))); if(regAddr != -1) { // Set the slave register address Xil_Out32((axiBaseAddr + TX_FIFO), regAddr); } // Write data to the I2C slave while(txCnt < txSize) { // put the Tx data into the Tx FIFO Xil_Out32((axiBaseAddr + TX_FIFO), (txCnt == txSize - 1) ? (0x200 | txBuf[txCnt]) : txBuf[txCnt]); txCnt++; } delay_ms(10); return txCnt; }
/***************************************************************************//** * @brief Initializes the AD9467 FPGA core. * * @param dco_delay - ADC delay. * * @return None. *******************************************************************************/ void adc_setup(uint32_t dco_delay) { Xil_Out32((CF_BASEADDR + 0x040), 0x3); delay_ms(10); // setup device ad9467_write(AD9467_REG_TEST_IO, 0x05); // pn23 ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x01); // update ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x00); xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(AD9467_REG_OUT_PHASE)); // setup adc core Xil_Out32((CF_BASEADDR+0x44), 0x2); // DDR_EDGESEL active Xil_Out32((CF_BASEADDR+0x400), 0x3); // pn23 Xil_Out32((CF_BASEADDR+0x60), 0x0); // clear Delay Control Xil_Out32((CF_BASEADDR+0x60), 0x20F1F); // Setup Delay Control delay_ms(10); if (adc_delay(8, 1)) { xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(0x16)); ad9467_write(AD9467_REG_OUT_PHASE, 0x80); ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x01); ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x00); xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(0x16)); delay_ms(10); if (adc_delay(16, 1)) { xil_printf("adc_setup: can not set a zero error delay!\n\r"); } } }
/****************************************************************************** * Configure the I2S controller to transmit data, which will be read out from * the local memory vector (Mem) * * @param u32NrSamples is the number of samples to store. * * @return none. *****************************************************************************/ void fnAudioPlay(XAxiDma AxiDma, u32 u32NrSamples) { union ubitField uTransferVariable; if (Demo.u8Verbose) { xil_printf("\r\nEnter Playback function"); } uTransferVariable.l = XAxiDma_SimpleTransfer(&AxiDma,(u32) MEM_BASE_ADDR, 5*u32NrSamples, XAXIDMA_DMA_TO_DEVICE); if (uTransferVariable.l != XST_SUCCESS) { if (Demo.u8Verbose) xil_printf("\n fail @ play; ERROR: %d", uTransferVariable.l); } // Send number of samples to record Xil_Out32(I2S_PERIOD_COUNT_REG, u32NrSamples); // Start i2s initialization sequence uTransferVariable.l = 0x00000000; Xil_Out32(I2S_TRANSFER_CONTROL_REG, uTransferVariable.l); uTransferVariable.bit.u32bit0 = 1; Xil_Out32(I2S_TRANSFER_CONTROL_REG, uTransferVariable.l); // Enable Stream function to send data (MM2S) Xil_Out32(I2S_STREAM_CONTROL_REG, 0x00000002); if (Demo.u8Verbose) { xil_printf("\r\nPlayback function done"); } }
/***************************************************************************//** * @brief Initializes the SPI communication peripheral. * * @param lsbFirst - Transfer format (0 or 1). * Example: 0x0 - MSB first. * 0x1 - LSB first. * @param clockFreq - SPI clock frequency (Hz). * The primary and secondary prescalers have to be modified * in order to change the SPI clock frequency * @param clockPol - SPI clock polarity (0 or 1). * Example: 0x0 - Idle state for clock is a low level; active * state is a high level; * 0x1 - Idle state for clock is a high level; active * state is a low level. * @param clockEdg - SPI clock edge (0 or 1). * Example: 0x0 - Serial output data changes on transition * from idle clock state to active clock * state; * 0x1 - Serial output data changes on transition * from active clock state to idle clock state * * @return status - Result of the initialization procedure. * Example: 0 - if initialization was successful; * -1 - if initialization was unsuccessful. ******************************************************************************/ char SPI_Init(unsigned char lsbFirst, unsigned long clockFreq, unsigned char clockPol, unsigned char clockEdg) { /*!< Configuration Register Settings */ configValue |= (lsbFirst << LSBFirst) | // MSB First transfer format (1 << MasterTranInh) | // Master transactions disabled (1 << ManualSlaveAssEn) | // Slave select output follows data in slave select register (1 << RxFifoReset) | // Receive FIFO normal operation (0 << TxFifoReset) | // Transmit FIFO normal operation (!clockEdg << CHPA) | // Data valid on first SCK edge (clockPol << CPOL) | // Active high clock, SCK idles low (1 << Master) | // SPI in Master configuration mode (1 << SPE) | // SPI enabled (0 << LOOP); // Normal operation /*!< Set the slave select register to all ones */ Xil_Out32(SPI_BASEADDR + SPISSR, 0xFFFFFFFF); /*!< Set corresponding value to the Configuration Register */ Xil_Out32(SPI_BASEADDR + SPICR, configValue); return 0; }
/**************************************************************************//** * @brief Initializes the communication with the Microblaze I2C peripheral. * * @param i2cAddr - The address of the I2C slave. * @param fmcPort - Set to 0 for LPC, set to 1 for HPC * @param enableCommMux - Set to 1 if the carrier board has an I2C multiplexer, * set to 0 otherwise * * @return Returns 0 or negative error code. ******************************************************************************/ uint32_t I2C_Init_axi(uint32_t i2cAddr, uint32_t fmcPort, uint32_t enableCommMux, uint32_t carrierBoard) { uint32_t ret = 0; //set the I2C core AXI address axi_iic_baseaddr = fmcPort == 0 ? AXI_IIC_BASEADDR_0 : AXI_IIC_BASEADDR_1; //disable the I2C core Xil_Out32((axi_iic_baseaddr + CR), 0x00); //set the Rx FIFO depth to maximum Xil_Out32((axi_iic_baseaddr + RX_FIFO_PIRQ), 0x0F); //reset the I2C core and flush the Tx fifo Xil_Out32((axi_iic_baseaddr + CR), 0x02); //enable the I2C core Xil_Out32((axi_iic_baseaddr + CR), 0x01); //enable the I2C mux if(enableCommMux) { if(carrierBoard == 3) ret = I2C_EnableMux_axi(0x20); else if(carrierBoard == 4) ret = I2C_EnableMux_axi(0x40); else ret = I2C_EnableMux_axi(fmcPort == 0 ? (uint8_t)I2C_LPC_AXI : (uint8_t)I2C_HPC_AXI); } return ret; }
static void RtcCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len) { XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_RTC_SECONDS); /* Enable Seconds Alarm */ Xil_Out32(RTC_RTC_INT_EN, 1U); Xil_Out32(RTC_RTC_INT_STATUS, 1U); fw_printf("RTC (MOD-%d): Initialized.\r\n", ModPtr->ModId); }
const NWADP * DEMRF24::deIPGetAdaptor(void) { // get our pins set up Xil_Out32(WF_GPIO_BASEADDRESS+4, 0b0001); Xil_Out32(WF_GPIO_BASEADDRESS, Xil_In32(WF_GPIO_BASEADDRESS)&0b0001); return(GetMRF24GAdaptor(NULL, hRRAdpHeap, NULL)); }
/** * * Perform a destructive 32-bit wide register IO test. Each location is tested * by sequentially writing a 32-bit wide regsiter, reading the register, and * comparing value. This function tests three kinds of register IO functions, * normal register IO, little-endian register IO, and big-endian register IO. * When testing little/big-endian IO, the function perform the following * sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, * Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value * before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. * @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. * @param Swap indicates whether to byte swap the read-in value. * * @return * * - -1 is returned for a failure * - 0 is returned for a pass * *****************************************************************************/ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) { u32 *TempAddr; u32 ValueIn = 0U; s32 Index; TempAddr = Addr; Xil_AssertNonvoid(TempAddr != NULL); for (Index = 0; Index < Length; Index++) { switch (Kind) { case XIL_TESTIO_LE: Xil_Out32LE((INTPTR)TempAddr, Value); break; case XIL_TESTIO_BE: Xil_Out32BE((INTPTR)TempAddr, Value); break; default: Xil_Out32((INTPTR)TempAddr, Value); break; } ValueIn = Xil_In32((INTPTR)TempAddr); if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); } if (Value != ValueIn) { return -1; } /* second round */ Xil_Out32((INTPTR)TempAddr, Value); switch (Kind) { case XIL_TESTIO_LE: ValueIn = Xil_In32LE((INTPTR)TempAddr); break; case XIL_TESTIO_BE: ValueIn = Xil_In32BE((INTPTR)TempAddr); break; default: ValueIn = Xil_In32((INTPTR)TempAddr); break; } if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); } if (Value != ValueIn) { return -1; } TempAddr += sizeof(u32); } return 0; }
void SysAlloc_init(void){ Xil_Out32(MMU_BASE + MMU_INIT_RANGE, 2396745 - 32768); Xil_Out32(MMU_BASE + MMU_INIT, 1); int init_done = 0; while(init_done == 0){ init_done = Xil_In32(MMU_BASE + MMU_INIT); } print("(SysAlloc Init Done) "); }
static void pumpOn(UArm *uarm) { if(FALSE == uarm->status.pump) { Xil_Out32(ADDR(PUMP_EN),LOW); Xil_Out32(ADDR(VALVE_EN),HIGH); uarm->status.pump = TRUE; } }
static void Xil_L2CacheSync(void) #endif { #ifdef CONFIG_PL310_ERRATA_753970 Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U); #else Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); #endif }
/***************************************************************************//** * @brief Configures the AD9467 device to run in the selected test mode * and checks if the read data pattern corresponds to the expected * values for the set test mode. * * @param mode - The test mode. Range 0 ..7 * 0 - test mode off * 1 - midscale short * 2 - +FS short * 3 - -FS short * 4 - checkerboard output * 5 - PN 23 sequence * 6 - PN 9 sequence * 7 - one/zero word toggle * @param format - Sets the data format: * 0 - offset binary * 1 - twos complement * 2 - gray code * * @return None. *******************************************************************************/ void adc_test(u32 mode, u32 format) { u32 n; u32 rdata; u32 edata; edata = 0; ad9467_output_format(format); ad9467_test_mode(mode); ad9467_transfer(); adc_capture(16, DDR_BASEADDR); xil_printf("adc_test(): mode(%2d), format(%2d)\n\r", mode, format); if ((mode == 0x5) || (mode == 0x6)) { if (format == 0x1) return; Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), ((mode == 0x5) ? 0x01 : 0x00)); delay_ms(10); Xil_Out32((CF_BASEADDR + CF_REG_DATA_MONITOR), CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG); // write ones to clear bits delay_ms(100); if ((Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR) & (CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG)) != 0) { xil_printf(" ERROR: PN status(%04x).\n\r", Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR)); } return; } for (n = 0; n < 32; n++) { rdata = Xil_In32(DDR_BASEADDR+(n*4)); if ((mode == 0x1) && (format == 0)) edata = 0x80008000; if ((mode == 0x2) && (format == 0)) edata = 0xffffffff; if ((mode == 0x3) && (format == 0)) edata = 0x00000000; if ((mode == 0x1) && (format == 1)) edata = 0x00000000; if ((mode == 0x2) && (format == 1)) edata = 0x7fff7fff; if ((mode == 0x3) && (format == 1)) edata = 0x80008000; if (((mode == 0x4) || (mode == 0x7)) && (n == 0)) { edata = (rdata & 0xffff); } if ((mode == 0x4) && (n == 0)) edata = (edata == 0xaaaa) ? 0x5555aaaa : 0xaaaa5555; if ((mode == 0x7) && (n == 0)) edata = (edata == 0xffff) ? 0x0000ffff : 0xffff0000; if (rdata != edata) { xil_printf(" ERROR[%2d]: rcv(%08x), exp(%08x)\n\r", n, rdata, edata); } } }
/**************************************************************************** * * Configure the SMC interface for SRAM. * * @param None. * * @return None. * * @note None. * ****************************************************************************/ void XSmc_SramInit (void) { Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES, SRAM_SET_CYCLES); Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE, SRAM_SET_OPMODE); Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD, SRAM_DIRECT_CMD); }
void timer0_systick_init() { // SCUtimer configuration // Set timer load and counter register Xil_Out32(XSCUTIMER_0_LOAD_REG, XSCTIMER_LOAD_VALUE); Xil_Out32(XSCUTIMER_0_COUNTER_REG, XSCTIMER_LOAD_VALUE); // Clear interrupt flag. Xil_Out32(XSCUTIMER_0_INT_STATUS_REG, 0x00000001); }
/**************************************************************************** * * Configure the SMC interface for NOR flash. * * @param None. * * @return None. * * @note None. * ****************************************************************************/ void XSmc_NorInit(void) { Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES, NOR_SET_CYCLES); Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE, NOR_SET_OPMODE); Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD, NOR_DIRECT_CMD); }
void set_car_front(int speed) { //set the for motor direction to be 0 //Xil_Out32(AXI_GPIO_BASEADDR, 0x00); //set the four motor's speed Xil_Out32(AXI_PWM_BASEADDR, speed == 0 ? 0 : 0x80000000 | speed); Xil_Out32(AXI_PWM_BASEADDR + 4, 0); Xil_Out32(AXI_PWM_BASEADDR + 8, speed == 0 ? 0 : 0x80000000 | speed); Xil_Out32(AXI_PWM_BASEADDR + 12, 0); }
/****************************************************************************** * @brief Reads data from an ADC usign AXI_DMA core * * @param buf - Start address of the buffer where to store the read data * @param size - Size in bytes of the data to read * @return None ******************************************************************************/ void ReadAdcData(u32 buf, u32 size) { // program DMA engine Xil_Out32((DMA_BASEADDR + 0x030), 0); // Clear dma operations Xil_Out32((DMA_BASEADDR + 0x030), 1); // Enable Run bit Xil_Out32((DMA_BASEADDR + 0x048), buf); // Configure DMA with the destination address Xil_Out32((DMA_BASEADDR + 0x058), (size * 4 )); // Number of bites to be written // program the DMA module in the ADC core Xil_Out32((CF_BASEADDR + 0x040), 0x1); // Power up the core Xil_Out32((CF_BASEADDR + 0x088), 0x7); // Reset overflows Xil_Out32((CF_BASEADDR + 0x080), 0x0); // DMA stop Xil_Out32((CF_BASEADDR + 0x084), size * 4 ); // Program the number of bytes to be captured Xil_Out32((CF_BASEADDR + 0x080), 0x1); // Start capturing data // Wait for data transfer to finish do { delay_ms(1); } while ((Xil_In32(CF_BASEADDR + 0x088) & 0x1) == 1); if (Xil_In32(CF_BASEADDR + 0x088) != 0x00) { xil_printf("overflow occured, capture may be corrupted\n\r"); xil_printf ("%x\n", Xil_In32(CF_BASEADDR + 0x088) ); } Xil_DCacheFlush(); }
/**************************************************************************//** * @brief Reads data from an I2C slave. * * @param i2cAddr - The address of the I2C slave. * @param regAddr - Address of the I2C register to be read. * Must be set to -1 if it is not used. * @param rxSize - Number of bytes to read from the slave. * @param rxBuf - Buffer to store the read data. * * @return Returns the number of bytes read. ******************************************************************************/ uint32_t I2C_Read_axi(uint32_t i2cAddr, uint32_t regAddr, uint32_t rxSize, uint8_t* rxBuf) { uint32_t rxCnt = 0; uint32_t timeout = I2C_TIMEOUT; // Reset tx fifo Xil_Out32((axi_iic_baseaddr + CR), 0x002); // Enable iic Xil_Out32((axi_iic_baseaddr + CR), 0x001); delay_us(I2C_DELAY); if(regAddr != -1) { // Set the slave I2C address Xil_Out32((axi_iic_baseaddr + TX_FIFO), (0x100 | (i2cAddr << 1))); // Set the slave register address Xil_Out32((axi_iic_baseaddr + TX_FIFO), regAddr); } // Set the slave I2C address Xil_Out32((axi_iic_baseaddr + TX_FIFO), (0x101 | (i2cAddr << 1))); // Start a read transaction Xil_Out32((axi_iic_baseaddr + TX_FIFO), 0x200 + rxSize); // Read data from the I2C slave while(rxCnt < rxSize) { //wait for data to be available in the RxFifo while((Xil_In32(axi_iic_baseaddr + SR) & 0x00000040) && (timeout--)); if(timeout == -1) { //disable the I2C core Xil_Out32((axi_iic_baseaddr + CR), 0x00); //set the Rx FIFO depth to maximum Xil_Out32((axi_iic_baseaddr + RX_FIFO_PIRQ), 0x0F); //reset the I2C core and flush the Tx fifo Xil_Out32((axi_iic_baseaddr + CR), 0x02); //enable the I2C core Xil_Out32((axi_iic_baseaddr + CR), 0x01); return rxCnt; } timeout = I2C_TIMEOUT; //read the data rxBuf[rxCnt] = Xil_In32(axi_iic_baseaddr + RX_FIFO) & 0xFFFF; //increment the receive counter rxCnt++; } delay_us(I2C_DELAY); return rxCnt; }
//used to initialize the timer before operating it uint32_t intervalTimer_init(uint32_t timerNumber) { if(timerNumber == 0) { Xil_Out32(INTERVALTIMER_TIMER_0_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, 0x0000);// write a 0 to the TCSR0 register.. Xil_Out32(INTERVALTIMER_TIMER_0_BASEADDR + INTERVALTIMER_TCSR1_OFFSET, 0x0000);// write a 0 to the TCSR1 register. uint32_t read = Xil_In32(INTERVALTIMER_TIMER_0_BASEADDR + INTERVALTIMER_TCSR0_OFFSET); //get the number stored in TCSR0 uint32_t newread = read | INTERVALTIMER_ELEVENTH_ON;// make the eleventh bit a 1 uint32_t twonew = newread & INTERVALTIMER_SECOND_OFF; //make the second bit a 0 using masking Xil_Out32(INTERVALTIMER_TIMER_0_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, twonew);// SET THE CASC BIT AS 1 WHICH MAKES IT CASCADING; set the UDT0 bit as 0 which makes it an up counter } if(timerNumber == 1) { Xil_Out32(INTERVALTIMER_TIMER_1_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, 0x0000);// write a 0 to the TCSR0 register.. Xil_Out32(INTERVALTIMER_TIMER_1_BASEADDR + INTERVALTIMER_TCSR1_OFFSET, 0x0000);// write a 0 to the TCSR1 register. uint32_t read = Xil_In32(INTERVALTIMER_TIMER_1_BASEADDR + INTERVALTIMER_TCSR0_OFFSET); //get the number stored in TCSR0 uint32_t newread = read | INTERVALTIMER_ELEVENTH_ON;// make the eleventh bit a 1 uint32_t twonew = newread & INTERVALTIMER_SECOND_OFF; //make the second bit a 0 using masking Xil_Out32(INTERVALTIMER_TIMER_1_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, twonew);// SET THE CASC BIT AS 1 WHICH MAKES IT CASCADING; set the UDT0 bit as 0 which makes it an up counter } if(timerNumber == 2) { Xil_Out32(INTERVALTIMER_TIMER_2_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, 0x0000);// write a 0 to the TCSR0 register.. Xil_Out32(INTERVALTIMER_TIMER_2_BASEADDR + INTERVALTIMER_TCSR1_OFFSET, 0x0000);// write a 0 to the TCSR1 register. uint32_t read = Xil_In32(INTERVALTIMER_TIMER_2_BASEADDR + INTERVALTIMER_TCSR0_OFFSET); //get the number stored in TCSR0 uint32_t newread = read | INTERVALTIMER_ELEVENTH_ON;// make the eleventh bit a 1 uint32_t twonew = newread & INTERVALTIMER_SECOND_OFF; //make the second bit a 0 using masking Xil_Out32(INTERVALTIMER_TIMER_2_BASEADDR + INTERVALTIMER_TCSR0_OFFSET, twonew);// SET THE CASC BIT AS 1 WHICH MAKES IT CASCADING; set the UDT0 bit as 0 which makes it an up counter } }
/** * This function contains the implementation for disabling the level shifters * * @param N/A. * * @return N/A. * * @note None. * ******************************************************************************/ void XSlcr_DisableLevelShifters(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Disable the level shifters */ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); }
/** * This function contains the implementation for remapping the ocm memory region * * @param N/A. * * @return N/A. * * @note None. * ******************************************************************************/ void XOcm_Remap(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Map the ocm region to postbootrom state */ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); }
void my_dma_controller_load_registers(uint32_t source, uint32_t destination) { uint32_t status_register_values; Xil_Out32((XPAR_MY_DMA_0_BASEADDR) + (SOURCE_REGISTER), source); //writes to source register if (Xil_In32((XPAR_MY_DMA_0_BASEADDR) + (SOURCE_REGISTER)) != source) { //error checking xil_printf("Something went wrong writing to source register.\n\r"); } Xil_Out32((XPAR_MY_DMA_0_BASEADDR) + (DEST_REGISTER), destination); //writes to the dest register if (Xil_In32((XPAR_MY_DMA_0_BASEADDR) + (DEST_REGISTER)) != destination) { //error checking xil_printf("Something went wrong writing to destination register.\n\r"); } }
/** * * Perform a destructive 32-bit wide register IO test. Each location is tested * by sequentially writing a 32-bit wide regsiter, reading the register, and * comparing value. This function tests three kinds of register IO functions, * normal register IO, little-endian register IO, and big-endian register IO. * When testing little/big-endian IO, the function perform the following * sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, * Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value * before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. * @param Len is the length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. * @param Swap indicates whether to byte swap the read-in value. * * @return * * - -1 is returned for a failure * - 0 is returned for a pass * *****************************************************************************/ int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap) { u32 ValueIn; int Index; for (Index = 0; Index < Len; Index++) { switch (Kind) { case XIL_TESTIO_LE: Xil_Out32LE((u32)Addr, Value); break; case XIL_TESTIO_BE: Xil_Out32BE((u32)Addr, Value); break; default: Xil_Out32((u32)Addr, Value); break; } ValueIn = Xil_In32((u32)Addr); if (Kind && Swap) ValueIn = Swap32(ValueIn); if (Value != ValueIn) { return -1; } /* second round */ Xil_Out32((u32)Addr, Value); switch (Kind) { case XIL_TESTIO_LE: ValueIn = Xil_In32LE((u32)Addr); break; case XIL_TESTIO_BE: ValueIn = Xil_In32BE((u32)Addr); break; default: ValueIn = Xil_In32((u32)Addr); break; } if (Kind && Swap) ValueIn = Swap32(ValueIn); if (Value != ValueIn) { return -1; } Addr++; } return 0; }
/***************************************************************************//** * @brief Initializes the I2C communication peripheral. * * @param clockFreq - I2C clock frequency (Hz). * Example: 100000 - I2C clock frequency is 100 kHz. * @return status - Result of the initialization procedure. * Example: 0 - if initialization was successful; * -1 - if initialization was unsuccessful. *******************************************************************************/ unsigned char I2C_Init(unsigned long clockFreq) { /*!< Disable the I2C core */ Xil_Out32((I2C_BASEADDR + CR), 0x00); /*!< Set the Rx FIFO depth to maximum */ Xil_Out32((I2C_BASEADDR + RX_FIFO_PIRQ), 0x0F); /*!< Reset the I2C core and flush the Tx fifo */ Xil_Out32((I2C_BASEADDR + CR), 0x02); /*!< Enable the I2C core */ Xil_Out32((I2C_BASEADDR + CR), 0x01); return 0; }