void mainemuinit()
{
// initialize cpu memory
mem_init();
#ifndef __GP32__
graphics_init(NULL);
#else
graphics_init();
#endif
// initialize the TLCS-900H cpu
tlcs_init();
#ifdef DRZ80
Z80_Reset();
#else
z80Init();
#endif
// if neogeo pocket color rom, act if we are a neogeo pocket color
tlcsMemWriteB(0x6F91,tlcsMemReadB(0x00200023));
// pretend we're running in English mode
tlcsMemWriteB(0x00006F87,0x01);
// kludges & fixes
switch (tlcsMemReadW(0x00200020))
{
case 0x0059: // Sonic
case 0x0061: // Metal SLug 2nd
*get_address(0x0020001F) = 0xFF;
break;
}
ngpSoundOff();
//Flavor sound_start();
}
void ngpSoundStart()
{
ngpRunning = 1; // ?
#if defined(DRZ80) || defined(CZ80)
Z80_Reset();
#else
z80Init();
z80SetRunning(1);
#endif
}
// Initialize the NGPC sound engine (Z80)
void ngpSoundStart()
{
ngpRunning = 1; // ?
#ifdef DRZ80
Z80_Reset();
#else
z80Init();
z80SetRunning(1);
#endif
}
int
Z80_Init (void)
{
// Init Z80
z80_Init (&M_Z80);
z80_Add_Fetch (&M_Z80, 0x00, 0x1F, &Ram_Z80[0]);
z80_Add_Fetch (&M_Z80, 0x20, 0x3F, &Ram_Z80[0]);
z80_Add_ReadB (&M_Z80, 0x00, 0xFF, Z80_ReadB_Bad);
z80_Add_ReadB (&M_Z80, 0x00, 0x3F, Z80_ReadB_Ram);
z80_Add_ReadB (&M_Z80, 0x40, 0x5F, Z80_ReadB_YM2612);
z80_Add_ReadB (&M_Z80, 0x60, 0x6F, Z80_ReadB_Bank);
z80_Add_ReadB (&M_Z80, 0x70, 0x7F, Z80_ReadB_PSG);
z80_Add_ReadB (&M_Z80, 0x80, 0xFF, Z80_ReadB_68K_Ram);
z80_Add_ReadW (&M_Z80, 0x00, 0xFF, Z80_ReadW_Bad);
z80_Add_ReadW (&M_Z80, 0x00, 0x3F, Z80_ReadW_Ram);
z80_Add_ReadW (&M_Z80, 0x40, 0x5F, Z80_ReadW_YM2612);
z80_Add_ReadW (&M_Z80, 0x60, 0x6F, Z80_ReadW_Bank);
z80_Add_ReadW (&M_Z80, 0x70, 0x7F, Z80_ReadW_PSG);
z80_Add_ReadW (&M_Z80, 0x80, 0xFF, Z80_ReadW_68K_Ram);
z80_Add_WriteB (&M_Z80, 0x00, 0xFF, Z80_WriteB_Bad);
z80_Add_WriteB (&M_Z80, 0x00, 0x3F, Z80_WriteB_Ram);
z80_Add_WriteB (&M_Z80, 0x40, 0x5F, Z80_WriteB_YM2612);
z80_Add_WriteB (&M_Z80, 0x60, 0x6F, Z80_WriteB_Bank);
z80_Add_WriteB (&M_Z80, 0x70, 0x7F, Z80_WriteB_PSG);
z80_Add_WriteB (&M_Z80, 0x80, 0xFF, Z80_WriteB_68K_Ram);
z80_Add_WriteW (&M_Z80, 0x00, 0xFF, Z80_WriteW_Bad);
z80_Add_WriteW (&M_Z80, 0x00, 0x3F, Z80_WriteW_Ram);
z80_Add_WriteW (&M_Z80, 0x40, 0x5F, Z80_WriteW_YM2612);
z80_Add_WriteW (&M_Z80, 0x60, 0x6F, Z80_WriteW_Bank);
z80_Add_WriteW (&M_Z80, 0x70, 0x7F, Z80_WriteW_PSG);
z80_Add_WriteW (&M_Z80, 0x80, 0xFF, Z80_WriteW_68K_Ram);
Z80_Reset ();
return 1;
}
/**
* Reset_Genesis(): Resets the Genesis.
*/
void Reset_Genesis(void)
{
// Clear the sound buffer.
audio_clear_sound_buffer();
Controller_1_COM = Controller_2_COM = 0;
Settings.Paused = 0;
// If the ROM size is smaller than 2MB, enable SRAM.
// Otherwise, disable SRAM.
// TODO: Instead of hardcoding 2MB, use SRAM_Start.
if (Rom_Size <= (2 * 1024 * 1024))
{
SRAM_ON = 1;
SRAM_Write = 1;
}
else
{
SRAM_ON = 0;
SRAM_Write = 0;
}
// Reset all CPUs and other components.
M68K_Reset(0);
Z80_Reset();
VDP_Reset();
YM2612_Reset();
// Initialize the controller state.
Init_Controllers();
if (CPU_Mode)
VDP_Status |= 1;
else
VDP_Status &= ~1;
if (Auto_Fix_CS)
ROM::fixChecksum();
}
/**
* Init_Genesis_Bios(): Initialize the Genesis BIOS.
* TODO: Fix this. It doesn't seem to work properly.
*/
void Init_Genesis_Bios(void)
{
// TODO: Compressor support.
FILE *f;
// Clear the sound buffer.
audio_clear_sound_buffer();
// Clear the TMSS firmware buffer.
memset(&Genesis_Rom[0], 0x00, sizeof(Genesis_Rom));
ROM_ByteSwap_State &= ~ROM_BYTESWAPPED_MD_TMSS;
if ((f = fopen(BIOS_Filenames.MD_TMSS, "rb")))
{
size_t n = fread(&Genesis_Rom[0], 1, sizeof(Genesis_Rom), f);
fclose(f);
be16_to_cpu_array(&Genesis_Rom[0], n);
Rom_Size = n;
}
else
{
// No Genesis TMSS ROM.
Rom_Size = sizeof(Genesis_Rom);
}
ROM_ByteSwap_State |= ROM_BYTESWAPPED_MD_TMSS;
memcpy(Rom_Data, Genesis_Rom, Rom_Size);
Game_Mode = 0;
CPU_Mode = 0;
VDP_Num_Vis_Lines = 224;
// Set the clock frequencies.
Set_Clock_Freq(0);
// Reset the CPUs.
M68K_Reset(0);
Z80_Reset();
VDP_Reset();
}
void cpu_run(void)
{
int totalcpu,usres;
unsigned char *ROM0; /* opcode decryption is currently supported only for the first memory region */
ROM0 = ROM;
/* count how many CPUs we have to emulate */
totalcpu = 0;
while (totalcpu < MAX_CPU)
{
const struct MemoryReadAddress *mra;
const struct MemoryWriteAddress *mwa;
if (Machine->drv->cpu[totalcpu].cpu_type == 0) break;
/* if sound is disabled, don't emulate the audio CPU */
if (play_sound == 0 && (Machine->drv->cpu[totalcpu].cpu_type & CPU_AUDIO_CPU))
cpurunning[totalcpu] = 0;
else
cpurunning[totalcpu] = 1;
/* initialize the memory base pointers for memory hooks */
RAM = Machine->memory_region[Machine->drv->cpu[totalcpu].memory_region];
mra = Machine->drv->cpu[totalcpu].memory_read;
while (mra->start != -1)
{
if (mra->base) *mra->base = &RAM[mra->start];
mra++;
}
mwa = Machine->drv->cpu[totalcpu].memory_write;
while (mwa->start != -1)
{
if (mwa->base) *mwa->base = &RAM[mwa->start];
mwa++;
}
totalcpu++;
}
#ifdef BUGS
extern void g_exec(void);
g_exec();
#else // BUGS
reset:
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
int cycles;
cycles = Machine->drv->cpu[activecpu].cpu_clock /
(Machine->drv->frames_per_second * Machine->drv->cpu[activecpu].interrupts_per_frame);
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_Reset();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = Z80_IGNORE_INT;
}
break;
#if 0
case CPU_M6502:
{
M6502 *ctxt;
ctxt = (M6502 *)cpucontext[activecpu];
/* Reset6502() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
ctxt->IPeriod = cycles; /* must be done before Reset6502() */
Reset6502(ctxt);
}
break;
case CPU_I86:
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
I86_Reset(RAM,cycles);
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
/* m6809_reset() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
m6809_IPeriod = cycles;
m6809_reset();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = INT_NONE;
}
break;
#endif
/* ...DS */
}
}
do
{
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
if (cpurunning[activecpu])
{
int loops;
memoryread = Machine->drv->cpu[activecpu].memory_read;
memorywrite = Machine->drv->cpu[activecpu].memory_write;
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
/* opcode decryption is currently supported only for the first memory region */
if (activecpu == 0) ROM = ROM0;
else ROM = RAM;
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_SetRegs(&ctxt->regs);
Z80_ICount = ctxt->icount;
Z80_IPeriod = ctxt->iperiod;
Z80_IRQ = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Z80_Execute();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = Z80_ICount;
ctxt->iperiod = Z80_IPeriod;
ctxt->irq = Z80_IRQ;
}
break;
#if 0
case CPU_M6502:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Run6502((M6502 *)cpucontext[activecpu]);
break;
case CPU_I86:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
I86_Execute();
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
m6809_SetRegs(&ctxt->regs);
m6809_ICount = ctxt->icount;
m6809_IPeriod = ctxt->iperiod;
m6809_IRequest = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
m6809_execute();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = m6809_ICount;
ctxt->iperiod = m6809_IPeriod;
ctxt->irq = m6809_IRequest;
}
break;
#endif
/* ...DS */
}
}
}
usres = updatescreen();
if (usres == 2) /* user asked to reset the machine */
goto reset;
} while (usres == 0);
#endif // BUGS
}
/**
* Init_Genesis(): Initialize the Genesis with the specified ROM image.
* @param MD_ROM ROM image struct.
* @return 1 if successful.
*/
int Init_Genesis(ROM_t* MD_ROM)
{
// Clear the sound buffer.
audio_clear_sound_buffer();
Flag_Clr_Scr = 1;
Settings.Paused = Frame_Number = 0;
SRAM_Start = SRAM_End = SRAM_ON = SRAM_Write = 0;
Controller_1_COM = Controller_2_COM = 0;
#ifdef GENS_DEBUGGER
STOP_DEBUGGING();
#endif
#if 0 // TODO: Replace with MDP "exclusive mode" later.
if (!Kaillera_Client_Running)
#endif
Init_Genesis_SRAM(MD_ROM);
// Check what country code should be used.
// TODO: Get rid of magic numbers.
switch (Country)
{
default:
case -1: // Autodetection.
Detect_Country_Genesis(MD_ROM);
break;
case 0: // Japan (NTSC)
Game_Mode = 0;
CPU_Mode = 0;
break;
case 1: // US (NTSC)
Game_Mode = 1;
CPU_Mode = 0;
break;
case 2: // Europe (PAL)
Game_Mode = 1;
CPU_Mode = 1;
break;
case 3: // Japan (PAL)
Game_Mode = 0;
CPU_Mode = 1;
break;
}
VDP_Num_Vis_Lines = 224;
Gen_Version = 0x20 + 0x0; // Version de la megadrive (0x0 - 0xF)
// Byteswap the ROM data.
be16_to_cpu_array(Rom_Data, Rom_Size);
ROM_ByteSwap_State |= ROM_BYTESWAPPED_MD_ROM;
// Reset all CPUs and other components.
M68K_Reset(0);
Z80_Reset();
VDP_Reset();
// Initialize the controller state.
Init_Controllers();
// Set clock rates depending on the CPU mode (NTSC / PAL).
Set_Clock_Freq(0);
// If auto-fix checksum is enabled, fix the ROM checksum.
if (Auto_Fix_CS)
ROM::fixChecksum();
// Initialize sound.
if (audio_get_enabled())
{
audio_end();
if (audio_init(AUDIO_BACKEND_DEFAULT))
audio_set_enabled(false);
else
{
if (audio_play_sound)
audio_play_sound();
}
}
Reset_Update_Timers();
// Set the appropriate frame update function pointers.
Update_Frame = Do_Genesis_Frame;
Update_Frame_Fast = Do_Genesis_Frame_No_VDP;
return 1;
}
