/***************************************************************************//**
* @brief
* Generate 128 bit decryption key from 128 bit encryption key. The decryption
* key is used for some cipher modes when decrypting.
*
* @details
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place 128 bit decryption key. Must be at least 16 bytes long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding 128 bit encryption key. Must be at least 16 bytes long.
******************************************************************************/
void AES_DecryptKey128(uint8_t *out, const uint8_t *in)
{
int i;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
for (i = 3; i >= 0; i--)
{
AES->KEYLA = __REV(_in[i]);
}
/* Do dummy encryption to generate decrypt key */
AES->CTRL = 0;
AES_IntClear(AES_IF_DONE);
AES->CMD = AES_CMD_START;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save decryption key */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->KEYLA);
}
}
/**************************************************************************//**
* @brief Decrypt one AES block using the CBC mode.
*
* @param key
* The decryption key
*
* @param inputData
* The cipher text block to decrypt
*
* @param prevCipher
* The cipher text of the previous block
*
* @param outputData
* Buffer to store the decrypted block
*****************************************************************************/
RAMFUNC void decryptCBC256(const uint8_t *key, const uint8_t* inputData, const uint8_t *prevCipher, uint8_t *outputData)
{
int i;
uint32_t *_key = (uint32_t *)key;
uint32_t *_inputData = (uint32_t *)inputData;
uint32_t *_prevCipher = (uint32_t *)prevCipher;
uint32_t *_outputData = (uint32_t *)outputData;
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_AES256;
/* Load key and input block */
for (i=3; i>=0; i--)
{
AES->KEYHA = __REV(_key[i]);
AES->KEYLA = __REV(_key[i+4]);
AES->DATA = __REV(_inputData[i]);
}
/* Start and wait until decryption is complete */
AES->CMD = AES_CMD_START;
while ( AES->STATUS & AES_STATUS_RUNNING );
/* Retrieve decrypted block */
for (i=3; i>=0; i--)
{
_outputData[i] = __REV(AES->DATA) ^ _prevCipher[i];
}
}
/**
* @brief Write the InitVector/InitCounter in IVRx registers.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
{
uint32_t ivaddr = 0x0;
if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
{
hcryp->Instance->IVR3 = 0;
hcryp->Instance->IVR2 = 0;
hcryp->Instance->IVR1 = 0;
hcryp->Instance->IVR0 = 0;
}
else
{
if (hcryp->Init.pInitVect == NULL)
{
return HAL_ERROR;
}
ivaddr = (uint32_t)(hcryp->Init.pInitVect);
hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
}
return HAL_OK;
}
/***************************************************************************//**
* @brief
* Generate 256 bit decryption key from 256 bit encryption key. The decryption
* key is used for some cipher modes when decrypting.
*
* @details
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place 256 bit decryption key. Must be at least 32 bytes long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding 256 bit encryption key. Must be at least 32 bytes long.
******************************************************************************/
void AES_DecryptKey256(uint8_t *out, const uint8_t *in)
{
int i;
int j;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
AES->KEYLA = __REV(_in[j]);
AES->KEYHA = __REV(_in[i]);
}
/* Do dummy encryption to generate decrypt key */
AES->CTRL = AES_CTRL_AES256;
AES->CMD = AES_CMD_START;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save decryption key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
_out[j] = __REV(AES->KEYLA);
_out[i] = __REV(AES->KEYHA);
}
}
/**
* @brief Compute the HASH SHA1 digest.
* @param Input: pointer to the Input buffer to be treated.
* @param Ilen: length of the Input buffer.
* @param Output: the returned digest
* @retval An ErrorStatus enumeration value:
* - SUCCESS: digest computation done
* - ERROR: digest computation failed
*/
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) {
HASH_InitTypeDef SHA1_HASH_InitStructure;
HASH_MsgDigest SHA1_MessageDigest;
__IO uint16_t nbvalidbitsdata = 0;
uint32_t i = 0;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t inputaddr = (uint32_t) Input;
uint32_t outputaddr = (uint32_t) Output;
/* Number of valid bits in last word of the Input data */
nbvalidbitsdata = 8 * (Ilen % 4);
/* HASH peripheral initialization */
HASH_DeInit();
/* HASH Configuration */
SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
HASH_Init(&SHA1_HASH_InitStructure);
/* Configure the number of valid bits in last word of the data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* Write the Input block in the IN FIFO */
for (i = 0; i < Ilen; i += 4) {
HASH_DataIn(*(uint32_t*) inputaddr);
inputaddr += 4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
do {
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
} while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET) {
status = ERROR;
} else {
/* Read the message digest */
HASH_GetDigest(&SHA1_MessageDigest);
*(uint32_t*) (outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
outputaddr += 4;
*(uint32_t*) (outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
outputaddr += 4;
*(uint32_t*) (outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
outputaddr += 4;
*(uint32_t*) (outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
outputaddr += 4;
*(uint32_t*) (outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
}
return status;
}
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.
*
* @details
* Encryption:
* @verbatim
* InitVector +----------------+
* | | |
* V | V
* +--------------+ | +--------------+
* Key ->| Block cipher | | Key ->| Block cipher |
* | encryption | | | encryption |
* +--------------+ | +--------------+
* | | |
* |---------+ |
* V V
* Plaintext ->XOR Plaintext ->XOR
* | |
* V V
* Ciphertext Ciphertext
* @endverbatim
* Decryption:
* @verbatim
* InitVector +----------------+
* | | |
* V | V
* +--------------+ | +--------------+
* Key ->| Block cipher | | Key ->| Block cipher |
* | encryption | | | encryption |
* +--------------+ | +--------------+
* | | |
* |---------+ |
* V V
* Ciphertext ->XOR Ciphertext ->XOR
* | |
* V V
* Plaintext Plaintext
* @endverbatim
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* 128 bit encryption key.
*
* @param[in] iv
* 128 bit initalization vector to use.
******************************************************************************/
void AES_OFB128(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
const uint8_t *iv)
{
int i;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
const uint32_t *_key = (const uint32_t *)key;
const uint32_t *_iv = (const uint32_t *)iv;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
/* Select encryption mode, trigger explicitly by command */
#if defined( AES_CTRL_KEYBUFEN )
AES->CTRL = AES_CTRL_KEYBUFEN;
#else
AES->CTRL = 0;
#endif
/* Load key into high key for key buffer usage */
/* Load initialization vector */
for (i = 3; i >= 0; i--)
{
#if defined( AES_CTRL_KEYBUFEN )
AES->KEYHA = __REV(_key[i]);
#endif
AES->DATA = __REV(_iv[i]);
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
#if !defined( AES_CTRL_KEYBUFEN )
/* Load key */
for (i = 3; i >= 0; i--)
{
AES->KEYLA = __REV(_key[i]);
}
#endif
AES->CMD = AES_CMD_START;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
_in += 4;
}
}
// Get response from the SD card
// input:
// resp_type - response type (SD_Rxx values)
// pResp - pointer to the array for response (1..4 32-bit values)
// return:
// for R1 or R1b responses:
// SDR_Success if no error or SDR_XXX in case of some error bits set
// pResp contains a card status value
// for R2 response:
// result always is SDR_Success
// pResp contains a 128-bit CSD or CID register value
// for R3 response:
// SDR_Success if no error or SDR_BadResponse in case of bad OCR register header
// pResp contains a 32-bit OCR register value
// for R6 response:
// SDR_Success if no error or SDR_BadResponse in case of bad RCA response
// pResp contains a 32-bit RCA value
// for R7 response:
// SDR_Success if no error or SDR_BadResponse in case of bad R7 response header
// pResp contains a 32-bit value of R7 response
SDResult SD_Response(uint16_t resp_type, uint32_t *pResp) {
SDResult result = SDR_Success;
// Get first 32-bit value, it similar for all types of response except R2
*pResp = SDIO->RESP1;
switch (resp_type) {
case SD_R1:
case SD_R1b:
// RESP1 contains card status information
// Check for error bits in card status
result = SD_GetError(*pResp);
break;
case SD_R2:
// RESP1..4 registers contain the CID/CSD register value
#ifdef __GNUC__
// Use GCC built-in intrinsics (fastest, less code) (GCC v4.3 or later)
*pResp++ = __builtin_bswap32(SDIO->RESP1);
*pResp++ = __builtin_bswap32(SDIO->RESP2);
*pResp++ = __builtin_bswap32(SDIO->RESP3);
*pResp = __builtin_bswap32(SDIO->RESP4);
#else
// Use ARM 'REV' instruction (fast, a bit bigger code than GCC intrinsics)
*pResp++ = __REV(SDIO->RESP1);
*pResp++ = __REV(SDIO->RESP2);
*pResp++ = __REV(SDIO->RESP3);
*pResp = __REV(SDIO->RESP4);
// Use SHIFT, AND and OR (slower, biggest code)
// *pResp++ = SWAP_UINT32(SDIO->RESP1);
// *pResp++ = SWAP_UINT32(SDIO->RESP2);
// *pResp++ = SWAP_UINT32(SDIO->RESP3);
// *pResp = SWAP_UINT32(SDIO->RESP4);
#endif
break;
case SD_R3:
// RESP1 contains the OCR register value
// Check for correct OCR header
if (SDIO->RESPCMD != 0x3f) result = SDR_BadResponse;
break;
case SD_R6:
// RESP1 contains the RCA response value
// Only CMD3 generates R6 response, so RESPCMD must be 0x03
if (SDIO->RESPCMD != 0x03) result = SDR_BadResponse;
break;
case SD_R7:
// RESP1 contains 'Voltage accepted' and echo-back of check pattern
// Only CMD8 generates R7 response, so RESPCMD must be 0x08
if (SDIO->RESPCMD != 0x08) result = SDR_BadResponse;
break;
default:
// Unknown response
result = SDR_BadResponse;
break;
}
return result;
}
void
nbuf_alloc(int ch)
{
int i;
//uint32_t *temp;
next_txbd = 0;
next_rxbd = 0;
TxNBUF = (NBUF *)(((uint32_t)(unaligned_txbd)) & 0xFFFFFFF0);
RxNBUF = (NBUF *)(((uint32_t)(unaligned_rxbd)) & 0xFFFFFFF0);
RxBuffer = (uint8_t *)(((uint32_t)(unaligned_rxbuffer)) & 0xFFFFFFF0);
#ifdef USE_DEDICATED_TX_BUFFERS
TxBuffer = (uint8_t *)(((uint32_t)(unaligned_txbuffer)) & 0xFFFFFFF0);
#endif
// Initialize transmit descriptor ring
for (i = 0; i < NUM_TXBDS; i++)
{
TxNBUF[i].status = 0x0000;
TxNBUF[i].length = 0;
#ifdef USE_DEDICATED_TX_BUFFERS
#ifdef NBUF_LITTLE_ENDIAN
TxNBUF[i].data = (uint8_t *)__REV((uint32_t)&TxBuffer[i * TX_BUFFER_SIZE]);
#else
TxNBUF[i].data = (uint8_t *)(uint32_t)&TxBuffer[i * TX_BUFFER_SIZE];
#endif
#endif
#ifdef ENHANCED_BD
TxNBUF[i].ebd_status = TX_BD_IINS | TX_BD_PINS;
#endif
}
// Initialize receive descriptor ring
for (i = 0; i < NUM_RXBDS; i++)
{
RxNBUF[i].status = RX_BD_E;
RxNBUF[i].length = 0;
#ifdef NBUF_LITTLE_ENDIAN
RxNBUF[i].data = (uint8_t *)__REV((uint32_t)&RxBuffer[i * RX_BUFFER_SIZE]);
#else
RxNBUF[i].data = (uint8_t *)(uint32_t)&RxBuffer[i * RX_BUFFER_SIZE];
#endif
#ifdef ENHANCED_BD
RxNBUF[i].bdu = 0x00000000;
RxNBUF[i].ebd_status = RX_BD_INT;
#endif
}
// Set the Wrap bit on the last one in the ring
RxNBUF[NUM_RXBDS - 1].status |= RX_BD_W;
TxNBUF[NUM_TXBDS - 1].status |= TX_BD_W;
}
bool MassStorage_t::CmdReadCapacity10() {
// Uart.Printf("CmdReadCapacity10\r");
ReadCapacity10Response.LastBlockAddr = __REV(SDCD1.capacity - 1);
ReadCapacity10Response.BlockSize = __REV((uint32_t)MMCSD_BLOCK_SIZE);
// Transmit SenceData
Usb.PEpBulkIn->StartTransmitBuf((uint8_t*)&ReadCapacity10Response, sizeof(ReadCapacity10Response));
Usb.PEpBulkIn->WaitUntilReady();
// Succeed the command and update the bytes transferred counter
CmdBlock.DataTransferLen -= sizeof(ReadCapacity10Response);
return true;
}
/** Internal helper function. Initialize buffers and buffers descriptors for ENET module.
*/
static void init_enet_bufs(void) {
int i;
uint8_t *buf;
tx_bd = (enet_bd_t*)((uint32_t)tx_bd_unaligned + 0x0f & 0xfffffff0);
rx_bd = (enet_bd_t*)((uint32_t)rx_bd_unaligned + 0x0f & 0xfffffff0);
/* setup the buffers and initialize buffers descriptors */
buf = (uint8_t*)((uint32_t)tx_bufs + 0x0f & 0xfffffff0);
for (i = 0; i < NUM_ENET_TX_BUFS; i++) {
tx_bd[i].status = ENET_TX_BD_TC;
#ifdef ENET_LITTLE_ENDIAN
tx_bd[i].data = (uint8_t*)__REV((uint32_t)buf);
#else
tx_bd[i].data = buf;
#endif /* ENET_LITTLE_ENDIAN */
tx_bd[i].length = 0;
#ifdef ENHANCED_BD
tx_bd[i].ebd_status = TX_BD_INT
#if ENET_HARDWARE_CHECKSUM
| TX_BD_IINS
| TX_BD_PINS
#endif /* ENET_HARDWARE_CHECKSUM */
;
#endif /* ENHANCED_BD */
buf += ENET_TX_BUF_SIZE;
}
buf = (uint8_t*)((uint32_t)rx_bufs + 0x0f & 0xfffffff0);
for (i = 0; i < NUM_ENET_RX_BUFS; i++) {
rx_bd[i].status = ENET_RX_BD_E;
rx_bd[i].length = 0;
#ifdef ENET_LITTLE_ENDIAN
rx_bd[i].data = (uint8_t*)__REV((uint32_t)buf);
#else
rx_bd[i].data = buf;
#endif /* ENET_LITTLE_ENDIAN */
#ifdef ENHANCED_BD
rx_bd[i].bdu = 0x00000000;
rx_bd[i].ebd_status = RX_BD_INT;
#endif /* ENHANCED_BD */
buf += ENET_RX_BUF_SIZE;
}
/* set the wrap bit in the last descriptors to form a ring */
tx_bd[NUM_ENET_TX_BUFS - 1].status |= ENET_TX_BD_W;
rx_bd[NUM_ENET_RX_BUFS - 1].status |= ENET_RX_BD_W;
rx_next_buf = 0;
tx_next_buf = 0;
}
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 128 bit key.
*
* @details
* Encryption:
* @verbatim
* Plaintext Plaintext
* | |
* V V
* +--------------+ +--------------+
* Key ->| Block cipher | Key ->| Block cipher |
* | encryption | | encryption |
* +--------------+ +--------------+
* | |
* V V
* Ciphertext Ciphertext
* @endverbatim
* Decryption:
* @verbatim
* Ciphertext Ciphertext
* | |
* V V
* +--------------+ +--------------+
* Key ->| Block cipher | Key ->| Block cipher |
* | decryption | | decryption |
* +--------------+ +--------------+
* | |
* V V
* Plaintext Plaintext
* @endverbatim
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* When doing encryption, this is the 128 bit encryption key. When doing
* decryption, this is the 128 bit decryption key. The decryption key may
* be generated from the encryption key with AES_DecryptKey128().
*
* @param[in] encrypt
* Set to true to encrypt, false to decrypt.
******************************************************************************/
void AES_ECB128(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
bool encrypt)
{
int i;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
const uint32_t *_key = (const uint32_t *)key;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
AES->KEYHA = __REV(_key[i]);
}
if (encrypt)
{
/* Select encryption mode */
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
}
else
{
/* Select decryption mode */
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
/* Load block to be encrypted/decrypted */
for (i = 3; i >= 0; i--)
{
AES->DATA = __REV(_in[i]);
}
_in += 4;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 128 bit key.
*
* @details
* Encryption:
* @verbatim
* Counter Counter
* | |
* V V
* +--------------+ +--------------+
* Key ->| Block cipher | Key ->| Block cipher |
* | encryption | | encryption |
* +--------------+ +--------------+
* | |
* Plaintext ->XOR Plaintext ->XOR
* | |
* V V
* Ciphertext Ciphertext
* @endverbatim
* Decryption:
* @verbatim
* Counter Counter
* | |
* V V
* +--------------+ +--------------+
* Key ->| Block cipher | Key ->| Block cipher |
* | encryption | | encryption |
* +--------------+ +--------------+
* | |
* Ciphertext ->XOR Ciphertext ->XOR
* | |
* V V
* Plaintext Plaintext
* @endverbatim
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* 128 bit encryption key.
* If this argument is null, the key will not be loaded, as it is assumed
* the key has been loaded into KEYHA previously.
*
* @param[in,out] ctr
* 128 bit initial counter value. The counter is updated after each AES
* block encoding through use of @p ctrFunc.
*
* @param[in] ctrFunc
* Function used to update counter value.
******************************************************************************/
void AES_CTR128(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
uint8_t *ctr,
AES_CtrFuncPtr_TypeDef ctrFunc)
{
int i;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
uint32_t *_ctr = (uint32_t *)ctr;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
EFM_ASSERT(ctrFunc);
/* Select encryption mode, with auto trigger */
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
if (key)
{
const uint32_t *_key = (const uint32_t *)key;
/* Load key into high key for key buffer usage */
for (i = 3; i >= 0; i--)
{
AES->KEYHA = __REV(_key[i]);
}
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
/* Load ctr to be encrypted/decrypted */
for (i = 3; i >= 0; i--)
{
AES->DATA = __REV(_ctr[i]);
}
/* Increment ctr for next use */
ctrFunc(ctr);
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
_in += 4;
}
}
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 256 bit key.
*
* @details
* Please see AES_ECB128() for ECB figure.
*
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* When doing encryption, this is the 256 bit encryption key. When doing
* decryption, this is the 256 bit decryption key. The decryption key may
* be generated from the encryption key with AES_DecryptKey256().
*
* @param[in] encrypt
* Set to true to encrypt, false to decrypt.
******************************************************************************/
void AES_ECB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
bool encrypt)
{
int i;
int j;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
const uint32_t *_key = (const uint32_t *)key;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
if (encrypt)
{
/* Select encryption mode */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DATASTART;
}
else
{
/* Select decryption mode */
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_AES256 | AES_CTRL_DATASTART;
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
/* Load key and block to be encrypted/decrypted */
for (i = 3, j = 7; i >= 0; i--, j--)
{
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
AES->DATA = __REV(_in[i]);
}
_in += 4;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.
*
* @details
* Please see AES_OFB128() for OFB figure.
*
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* 256 bit encryption key.
*
* @param[in] iv
* 128 bit initalization vector to use.
******************************************************************************/
void AES_OFB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
const uint8_t *iv)
{
int i;
int j;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
const uint32_t *_key = (const uint32_t *)key;
const uint32_t *_iv = (const uint32_t *)iv;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
/* Select encryption mode, trigger explicitly by command */
AES->CTRL = AES_CTRL_AES256;
/* Load initialization vector */
for (i = 3; i >= 0; i--)
{
AES->DATA = __REV(_iv[i]);
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
/* Load key */
for (i = 3, j = 7; i >= 0; i--, j--)
{
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
}
AES->CMD = AES_CMD_START;
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
_in += 4;
}
}
/**
* @brief Write the Key in KeyRx registers.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
{
uint32_t keyaddr = 0x0;
if (hcryp->Init.pKey == NULL)
{
return HAL_ERROR;
}
keyaddr = (uint32_t)(hcryp->Init.pKey);
if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
{
hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
}
hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
return HAL_OK;
}
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 256 bit key.
*
* @details
* Please see AES_CTR128() for CTR figure.
*
* Please refer to general comments on layout and byte ordering of parameters.
*
* @param[out] out
* Buffer to place encrypted/decrypted data. Must be at least @p len long. It
* may be set equal to @p in, in which case the input buffer is overwritten.
*
* @param[in] in
* Buffer holding data to encrypt/decrypt. Must be at least @p len long.
*
* @param[in] len
* Number of bytes to encrypt/decrypt. Must be a multiple of 16.
*
* @param[in] key
* 256 bit encryption key.
*
* @param[in,out] ctr
* 128 bit initial counter value. The counter is updated after each AES
* block encoding through use of @p ctrFunc.
*
* @param[in] ctrFunc
* Function used to update counter value.
******************************************************************************/
void AES_CTR256(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
uint8_t *ctr,
AES_CtrFuncPtr_TypeDef ctrFunc)
{
int i;
int j;
uint32_t *_out = (uint32_t *)out;
const uint32_t *_in = (const uint32_t *)in;
const uint32_t *_key = (const uint32_t *)key;
uint32_t *_ctr = (uint32_t *)ctr;
EFM_ASSERT(!(len % AES_BLOCKSIZE));
EFM_ASSERT(ctrFunc);
/* Select encryption mode, with auto trigger */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DATASTART;
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
while (len--)
{
/* Load key and block to be encrypted/decrypted */
for (i = 3, j = 7; i >= 0; i--, j--)
{
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
AES->DATA = __REV(_ctr[i]);
}
/* Increment ctr for next use */
ctrFunc(ctr);
/* Wait for completion */
while (AES->STATUS & AES_STATUS_RUNNING)
;
/* Save encrypted/decrypted data */
for (i = 3; i >= 0; i--)
{
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
_in += 4;
}
}
/*
* LPLD_ENET_MacRecv
* 以太帧接收函数
*
* 参数:
* *ch--接收数据帧头地址。
* *len--数据帧长度地址。
*
* 输出:
* 无
*/
uint8 LPLD_ENET_MacRecv(uint8 *ch, uint16 *len)
{
uint8 *prvRxd;
*len = 0;
uxNextRxBuffer = 0;
//寻找为非空的接收缓冲区描述符
while( (xENETRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E)!=0 )
{
uxNextRxBuffer++;
if( uxNextRxBuffer >= CFG_NUM_ENET_RX_BUFFERS )
{
uxNextRxBuffer = 0;
return 1;
}
}
//读取接收缓冲区描述符
*len = __REVSH(xENETRxDescriptors[ uxNextRxBuffer ].length);
prvRxd = (uint8 *)__REV((uint32)xENETRxDescriptors[ uxNextRxBuffer ].data);
memcpy((void *)ch, (void *)prvRxd, *len);
//清除接收缓冲区描述符状态标志Empty
xENETRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E;
ENET_RDAR = ENET_RDAR_RDAR_MASK;
return 0;
}
/***************************************************************************//**
* @brief
* Issue a SCSI Read Capacity command.
*
* @param[out] data
* Read Capacity response data buffer.
*
* @return
* Returns true on success, false otherwise.
******************************************************************************/
bool MSDSCSI_ReadCapacity(MSDSCSI_ReadCapacityData_TypeDef *data)
{
if (MSDBOT_Xfer((void*) cbwReadCap, data) == SCSI_READCAPACITYDATA_LEN)
{
/* Big to Little endian conversion, keep local copy of lba count and size */
lbaCount = __REV(data->LogicalBlockAddress);
lbaSize = __REV(data->LogicalBlockLength);
data->LogicalBlockAddress = lbaCount;
data->LogicalBlockLength = lbaSize;
return true;
}
return false;
}
void
nbuf_flush(int ch)
{
int i;
next_txbd = 0;
next_rxbd = 0;
// Reset enet hardware bd pointers also ??
// Reset receive descriptor ring
for (i = 0; i < NUM_RXBDS; i++)
{
RxNBUF[i].status = RX_BD_E;
RxNBUF[i].length = 0;
#ifdef NBUF_LITTLE_ENDIAN
RxNBUF[i].data = (uint8_t *)__REV((uint32_t)&RxBuffer[i * RX_BUFFER_SIZE]);
#else
RxNBUF[i].data = (uint8_t *)(uint32_t)&RxBuffer[i * RX_BUFFER_SIZE];
#endif
}
// Reset transmit descriptor ring
for (i = 0; i < NUM_TXBDS; i++)
{
TxNBUF[i].status = 0x0000;
TxNBUF[i].length = 0;
}
// Set the Wrap bit on the last one in the ring
RxNBUF[NUM_RXBDS - 1].status |= RX_BD_W;
TxNBUF[NUM_TXBDS - 1].status |= TX_BD_W;
}
/**************************************************************************//**
* @brief AES IRQ Handler
*****************************************************************************/
void AES_IRQHandler(void)
{
int i;
/* Clear interrupt flag */
AES->IFC = AES_IFC_DONE;
if (blockIndex < numberOfBlocks)
{
/* Store en/decrypted data and increment to the next start input vector */
for (i = 3; i >= 0; i--)
{
outputDataG[i] = __REV(AES->DATA) ^ inputDataG[i];
}
outputDataG += 4;
inputDataG += 4;
/* Start en/decryption */
AES->CMD = AES_CMD_START;
}
/* Indicate last block */
else
{
aesFinished = true;
}
/* Increase block index */
blockIndex++;
}
// Check R2 response
// input:
// pBuf - pointer to the data buffer to store the R2 response
// return: SDResult value
static SDResult SD_GetR2Resp(uint32_t *pBuf) {
volatile uint32_t wait = SD_CMD_TIMEOUT;
// Wait for response, error or timeout
while (!(SDMMC1->STA & (SDMMC_STA_CCRCFAIL | SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT)) && --wait);
// Timeout?
if ((SDMMC1->STA & SDMMC_STA_CTIMEOUT) && (wait == 0)) {
SDMMC1->ICR = SDMMC_ICR_CTIMEOUTC;
return SDR_Timeout;
}
// CRC fail?
if (SDMMC1->STA & SDMMC_STA_CCRCFAIL) {
SDMMC1->ICR = SDMMC_ICR_CCRCFAILC;
return SDR_CRCError;
}
// Clear the static SDIO flags
SDMMC1->ICR = SDIO_ICR_STATIC;
// SDMMC_RESP[1..4] registers contains the R2 response
#ifdef __GNUC__
// Use GCC built-in intrinsics (fastest, less code) (GCC v4.3 or later)
*pBuf++ = __builtin_bswap32(SDMMC1->RESP1);
*pBuf++ = __builtin_bswap32(SDMMC1->RESP2);
*pBuf++ = __builtin_bswap32(SDMMC1->RESP3);
*pBuf = __builtin_bswap32(SDMMC1->RESP4);
#else
// Use ARM 'REV' instruction (fast, a bit bigger code than GCC intrinsics)
*pBuf++ = __REV(SDMMC1->RESP1);
*pBuf++ = __REV(SDMMC1->RESP2);
*pBuf++ = __REV(SDMMC1->RESP3);
*pBuf = __REV(SDMMC1->RESP4);
/*
// Use SHIFT, AND and OR (slower, biggest code)
*pBuf++ = SWAP_UINT32(SDMMC1->RESP1);
*pBuf++ = SWAP_UINT32(SDMMC1->RESP2);
*pBuf++ = SWAP_UINT32(SDMMC1->RESP3);
*pBuf = SWAP_UINT32(SDMMC1->RESP4);
*/
#endif
return SDR_Success;
}
void ad9951_init(void)
{
int ret;
uint64_t tmp64;
uint8_t i;
uint32_t carrier=107800;
// AD9951_SPI_Init();
/* RESET_H;
Si4432_Delay(1);
RESET_L;*/
cfr[0] = CFR1;
cfr[1] = 0;
cfr[2] = 0;
cfr[3] = SDIO_IPT;
cfr[4] = nSYNC_OPT;
for (i=0;i<5;i++)
{while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
SPI_I2S_SendData(PLL_SPI,cfr[i]);};
//Delayms(10);
while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
GPIO_SetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN); //Set PLL CS
//Delayms(10);
GPIO_ResetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN);
cfr[0] = CFR2;
cfr[1] = 0;
cfr[2] = 0;
cfr[3] = (PLL_MULT<<3)|7;
for (i=0;i<4;i++)
{while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
SPI_I2S_SendData(PLL_SPI,cfr[i]);};
//Delayms(10);
while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
GPIO_SetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN); //Set PLL CS
//Delayms(10);
GPIO_ResetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN);
#define MAX32 4294967296UL
//0x44ED9168 = 107700 khz @ Fs 400000
tmp64=((MAX32)*(uint64_t)carrier)/(XTAL_FREQ*PLL_MULT);
FTW=(uint32_t)tmp64&0xffffffff;
TIM2->CCR4=__REV(FTW);
cfr[0]=FTW0;
//*(uint32_t *)(&cfr[1])=*(uint32_t *)(&TIM2->CCR4);
cfr[1]=((FTW>>24)&0xFF);
cfr[2]=((FTW>>16)&0xFF);
cfr[3]=((FTW>>8)&0xFF);
cfr[4]=(FTW&0xFF);
for (i=0;i<5;i++)
{while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
SPI_I2S_SendData(PLL_SPI,cfr[i]);};
//Delayms(10);
while(SPI_I2S_GetFlagStatus(PLL_SPI, SPI_I2S_FLAG_BSY));
GPIO_SetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN); //Set PLL CS
//Delayms(10);
GPIO_ResetBits(PLL_SPI_CS_GPIO_PORT, PLL_SPI_CS_PIN);
}
/**************************************************************************//**
* @brief Encrypt/decrypt with 128-bit key in OFB mode. Function returns after
* initializing encryption/decryption. Use AesFinished() to check for
* completion. Output data only valid after completion.
*
* @param[in] key
* This is the 128-bit encryption key regardless of encryption or decryption
*
* @param[in] inputData
* Buffer holding data to encrypt/decrypt.
*
* @param[out] outputData
* Buffer to put output data, must be of size blockNumber*16 bytes. This can
* be the same location as inputData.
*
* @param[in] blockNumber
* Number of 128-bit blocks to decrypt/encrypt.
*
* @param[in] iv
* 128-bit initialization vector to use
*****************************************************************************/
void AesOfb128(const uint8_t* key,
const uint8_t* inputData,
uint8_t* outputData,
const uint32_t blockNumber,
const uint8_t* iv)
{
int i;
uint32_t* iv32 = (uint32_t*) iv;
uint32_t* key32 = (uint32_t*) key;
/* Copy to global variables */
inputDataG = (uint32_t*) inputData;
outputDataG = (uint32_t*) outputData;
numberOfBlocks = blockNumber;
/* Reset block index */
blockIndex = 0;
/* Initialize finished flag */
aesFinished = false;
/* Clear and enable AES interrupt */
AES->IFC = AES_IFC_DONE;
AES->IEN = AES_IEN_DONE;
NVIC_EnableIRQ(AES_IRQn);
/* Configure AES module */
AES->CTRL = AES_CTRL_KEYBUFEN; /* Set key buffer */
/* Write KEY and DATA to AES module - but this will NOT start the en/decryption. */
for (i = 3; i >= 0; i--)
{
/* Write the KEY to AES module beginning with the most significant 32-bit double word */
/* Writing only the KEYHA 4 times will transfer the key to all 4
* high key registers, used here, in 128 bit key mode, as buffers */
AES->KEYHA = __REV(key32[i]);
/* Load data using DATA register*/
AES->DATA = __REV(iv32[i]);
}
AES->CMD = AES_CMD_START; /* Only here start en/decryption */
}
/**
****************************************************************************************
* @brief Erase n sectors of flash
* @param[in] addr A23-A0 specified a valid 24bit address of a sector
* @param[in] n number of sector
* @description
* This function is used to erase serial flash sector.
*****************************************************************************************
*/
void sector_erase_flash(uint32_t addr, uint32_t n)
{
while (n--)
{
flash_write_enable(); //set the Write Enable Latch bit
sf_ctrl_SetCmdAddr(QN_SF_CTRL, __REV((addr & 0xffffff) | (g_flash_cmd[SE_CMD]<<24)));
addr += 4*1024; //all flash sector erase command erasing size is 4K
}
}
/**
****************************************************************************************
* @brief Erase n blocks of flash
* @param[in] addr A23-A0 specified a valid 24bit address of a block.
* @param[in] block_size flash a block content size
* @param[in] n requirement erasing number blocks
* @description
* This function is used to erase serial flash block.
*****************************************************************************************
*/
void block_erase_flash(uint32_t addr, uint32_t block_size, uint32_t n)
{
while (n--)
{
flash_write_enable(); //set the Write Enable Latch bit
sf_ctrl_SetCmdAddr(QN_SF_CTRL, __REV(addr | (g_flash_cmd[BE_CMD]<<24)));
addr += block_size;
}
}
u32 ReadUnit(u8 *buffer,u8 idx,u8 NbrOfBytes,Endianness BytesFormat)
{
u32 index=0;
u32 temp=0;
for(index=0;index<NbrOfBytes;index++)temp|=buffer[idx+index]<<(index*8);
if (BytesFormat == BigEndian)temp= __REV(temp);
return temp;
}
void vEMACWrite( void )
{
long x;
/* Wait until the second transmission of the last packet has completed. */
for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
{
if( ( xTxDescriptors[ 1 ].status & TX_BD_R ) != 0 )
{
/* Descriptor is still active. */
vTaskDelay( emacTX_WAIT_DELAY_ms );
}
else
{
break;
}
}
/* Is the descriptor free after waiting for it? */
if( ( xTxDescriptors[ 1 ].status & TX_BD_R ) != 0 )
{
/* Something has gone wrong. */
prvResetEverything();
}
/* Setup both descriptors to transmit the frame. */
xTxDescriptors[ 0 ].data = ( uint8_t * ) __REV( ( unsigned long ) uip_buf );
xTxDescriptors[ 0 ].length = __REVSH( uip_len );
xTxDescriptors[ 1 ].data = ( uint8_t * ) __REV( ( unsigned long ) uip_buf );
xTxDescriptors[ 1 ].length = __REVSH( uip_len );
/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
for use by the stack. */
uip_buf = prvGetNextBuffer();
/* Clear previous settings and go. */
xTxDescriptors[ 0 ].status |= ( TX_BD_R | TX_BD_L );
xTxDescriptors[ 1 ].status |= ( TX_BD_R | TX_BD_L );
/* Start the Tx. */
ENET_TDAR = ENET_TDAR_TDAR_MASK;
}
/*
* LPLD_ENET_BDInit
* 缓冲区描述符初始化
*
* 参数:
* 无
*
* 输出:
* 无
*/
static void LPLD_ENET_BDInit( void )
{
unsigned long ux;
uint8 *pcBufPointer;
//寻找<发送描述符数组空间>中的16字节对齐的地址，即低四位为0的起始地址
pcBufPointer = &( xENETTxDescriptors_unaligned[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
xENETTxDescriptors = ( NBUF * ) pcBufPointer;
//寻找<接收描述符数组空间>中的16字节对齐的地址
pcBufPointer = &( xENETRxDescriptors_unaligned[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
xENETRxDescriptors = ( NBUF * ) pcBufPointer;
//发送缓冲区描述符初始化
for( ux = 0; ux < CFG_NUM_ENET_TX_BUFFERS; ux++ )
{
xENETTxDescriptors[ ux ].status = 0;
xENETTxDescriptors[ ux ].data = 0;
xENETTxDescriptors[ ux ].length = 0;
}
//寻找<接收缓冲区空间>中的16字节对齐的地址
pcBufPointer = &( ucENETRxBuffers[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
//接收缓冲区描述符初始化
for( ux = 0; ux < CFG_NUM_ENET_RX_BUFFERS; ux++ )
{
xENETRxDescriptors[ ux ].status = RX_BD_E;
xENETRxDescriptors[ ux ].length = 0;
xENETRxDescriptors[ ux ].data = (uint8 *)__REV((uint32)pcBufPointer);
pcBufPointer += CFG_ENET_RX_BUFFER_SIZE;
}
//设置缓冲区描述符环形序列中的最后一个状态位为Wrap
xENETTxDescriptors[ CFG_NUM_ENET_TX_BUFFERS - 1 ].status |= TX_BD_W;
xENETRxDescriptors[ CFG_NUM_ENET_RX_BUFFERS - 1 ].status |= RX_BD_W;
uxNextRxBuffer = 0;
uxNextTxBuffer = 0;
}
__INLINE static size_t getAtomSize(void* atom)//
{
return __REV(*(uint32_t*)atom);
/*REV
Converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data.
This intrinsic inserts a REV instruction or an equivalent code sequence into the instruction stream generated by the compiler.
It enables you to convert a 32-bit big-endian data value into a little-endian data value, or a 32-bit little-endian data value
into a big-endian data value from within your C or C++ code.
*/
}
unsigned short usEMACRead( void )
{
unsigned short usBytesReceived;
usBytesReceived = prvCheckRxStatus();
usBytesReceived = __REVSH( usBytesReceived );
if( usBytesReceived > 0 )
{
/* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
the buffer that contains the received data. */
prvReturnBuffer( uip_buf );
/* Point uip_buf to the data about to be processed. */
uip_buf = ( void * ) pxCurrentRxDesc->data;
uip_buf = ( void * ) __REV( ( unsigned long ) uip_buf );
/* Allocate a new buffer to the descriptor, as uip_buf is now using it's
old descriptor. */
pxCurrentRxDesc->data = ( uint8_t * ) prvGetNextBuffer();
pxCurrentRxDesc->data = ( uint8_t* ) __REV( ( unsigned long ) pxCurrentRxDesc->data );
/* Prepare the descriptor to go again. */
pxCurrentRxDesc->status |= RX_BD_E;
/* Move onto the next buffer in the ring. */
ulRxDescriptorIndex++;
if( ulRxDescriptorIndex >= emacNUM_RX_DESCRIPTORS )
{
ulRxDescriptorIndex = 0UL;
}
pxCurrentRxDesc = &( xRxDescriptors[ ulRxDescriptorIndex ] );
/* Restart Ethernet if it has stopped */
ENET_RDAR = ENET_RDAR_RDAR_MASK;
}
return usBytesReceived;
}
