void send_signal() {
// 32.75khz is the target frequency
// must pulse at minimum twice
// too many pulses and the camera will
// interpert them as seperate signals
// 9 pulses is too many, 8 safe, 7 more safe
for (uint8_t repeat = 0; repeat <= 7; repeat++) {
for (uint8_t i = 0; i < 16; i++ ) {
#if F_CPU == 1000000
bset(PORTB, 0); // 2 cycles sbi
__builtin_avr_delay_cycles(12); // 12 cycles
bclr(PORTB, 0); // 2 cycles cbi
__builtin_avr_delay_cycles(12); // 12 cycles
// addi/subi // 1 cycle i++
// brne // 2 cycles loop check
// total = 31 cycles
// 1 clock, 1 microsecond at 1mhz
// 1 second / 31 microseconds = 32.25 khz
#else
#warning untested send_signal configuration
bset(PORTB,0);
_delay_us(15);
bclr(PORTB,0);
_delay_us(16);
// this is probably accurate enough
// no guarantees, though!
#endif
}
_delay_us(7300); // instant shot
// 5300 for 2sec delay before shot
}
}
void shiftReg_loadData(struct shiftOutReg *s, unsigned char data){
char temp;
for(unsigned char c = 1; c < 0b10000000; c <<= 1){
*s->port &= ~(1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
temp = (data&c) ? 1 : 0; //this would be amazing if it works!
if(temp == 1){
*s->port |= (1 << s->SER);
}else{
*s->port &= ~(1 << s->SER);
}
*s->port |= (1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
}
*s->port &= ~(1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
temp = (data&0x80) ? 1 : 0; //this would be amazing if it works!
if(temp == 1){
*s->port |= (1 << s->SER);
}else{
*s->port &= ~(1 << s->SER);
}
*s->port |= (1 << s->SRCLK);
*s->port |= (1 << s->RCLK);
//s->RCLK = 1;
__builtin_avr_delay_cycles(1);
*s->port &= ~((1 << s->SRCLK) | (1 << s->RCLK));
//s->RCLK = 0;
//s->SRCLK = 0;
}
void shiftReg_Clear_Output(struct shiftOutReg *s)
{
*s->port &= ~(1 << s->SRCLR);
//no op
__builtin_avr_delay_cycles(2);
*s->port |= (1 << s->SRCLR);
*s->port |= (1 << s->RCLK);
//s->RCLK = 1;
__builtin_avr_delay_cycles(1);
*s->port &= ~(1 << s->RCLK);
}
static void onPress() {
// Don't trigger any interrupts while strobing the keypad
KEYPAD_INT(PCMSK) = 0;
// Pull low each row one by one to find which buttons are pressed
uint8_t row = 0;
KEYPAD(PORT) = (~(1 << KEYPAD_ROW0) & KEYPAD_ROWS) | KEYPAD_COLS;
__builtin_avr_delay_cycles(2);
uint8_t input = ~KEYPAD(PIN) & KEYPAD_COLS;
if (!input) {
row = 1;
KEYPAD(PORT) = (~(1 << KEYPAD_ROW1) & KEYPAD_ROWS) | KEYPAD_COLS;
__builtin_avr_delay_cycles(2);
input = ~KEYPAD(PIN) & KEYPAD_COLS;
}
if (!input) {
row = 2;
KEYPAD(PORT) = (~(1 << KEYPAD_ROW2) & KEYPAD_ROWS) | KEYPAD_COLS;
__builtin_avr_delay_cycles(2);
input = ~KEYPAD(PIN) & KEYPAD_COLS;
}
if (!input) {
row = 3;
KEYPAD(PORT) = (~(1 << KEYPAD_ROW3) & KEYPAD_ROWS) | KEYPAD_COLS;
__builtin_avr_delay_cycles(2);
input = ~KEYPAD(PIN) & KEYPAD_COLS;
}
// Restore the keypad's state
KEYPAD(PORT) = KEYPAD_COLS;
KEYPAD_INT(PCMSK) = 0xff;
// Decode the column
uint8_t col = 0;
if (input & (1 << KEYPAD_COL0))
col = 0;
else if (input & (1 << KEYPAD_COL1))
col = 1;
else if (input & (1 << KEYPAD_COL2))
col = 2;
else if (input & (1 << KEYPAD_COL3))
col = 3;
// Call the callback
onKeypadPressCallback(pgm_read_byte(&keymap[row][col]));
}
unsigned char recv_isa_byte() {
unsigned char temp;
cli(); // disable interrupts
PORTB &= ~PIN_IDR; // lower IDR
__builtin_avr_delay_cycles(3); // wait for i/o to settle
temp = PINA; // capture what we find there
PORTB |= PIN_IDR; // raise IDR
sei(); // re-enable interrupts
return temp; // report back with the results
}
void send_isa_byte(Bit8u byte) {
cli(); // disable interrupts
DDRA = 0xff; // set porta to output
PORTA = byte; // output byte on porta
PORTB &= ~PIN_IDW; // lower IDW
__builtin_avr_delay_cycles(3); // wait for logic to stabilize
PORTB |= PIN_IDW; // raise IDW
DDRA = 0; // set the port back to input
sei(); // re-enable interrupts
}
/*---------------------------------------------------------------
Function for generating a TWI Stop Condition. Used to release
the TWI bus.
---------------------------------------------------------------*/
unsigned char USI_TWI_Master_Stop( void )
{
PORT_USI &= ~(1<<PIN_USI_SDA); // Pull SDA low.
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Wait for SCL to go high.
__builtin_avr_delay_cycles( T4_TWI );
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.
__builtin_avr_delay_cycles( T2_TWI );
#ifdef SIGNAL_VERIFY
if( !(USISR & (1<<USIPF)) )
{
USI_TWI_state.errorState = USI_TWI_MISSING_STOP_CON;
return (FALSE);
}
#endif
return (TRUE);
}
/*---------------------------------------------------------------
Core function for shifting data in and out from the USI.
Data to be sent has to be placed into the USIDR prior to calling
this function. Data read, will be return'ed from the function.
---------------------------------------------------------------*/
unsigned char USI_TWI_Master_Transfer( unsigned char temp )
{
USISR = temp; // Set USISR according to temp.
// Prepare clocking.
temp = (0<<USISIE)|(0<<USIOIE)| // Interrupts disabled
(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode.
(1<<USICS1)|(0<<USICS0)|(1<<USICLK)| // Software clock strobe as source.
(1<<USITC); // Toggle Clock Port.
do
{
__builtin_avr_delay_cycles( T2_TWI );
USICR = temp; // Generate positve SCL edge.
while( !(PIN_USI & (1<<PIN_USI_SCL)) );// Wait for SCL to go high.
__builtin_avr_delay_cycles( T4_TWI );
USICR = temp; // Generate negative SCL edge.
} while( !(USISR & (1<<USIOIF)) ); // Check for transfer complete.
__builtin_avr_delay_cycles( T2_TWI );
temp = USIDR; // Read out data.
USIDR = 0xFF; // Release SDA.
DDR_USI |= (1<<PIN_USI_SDA); // Enable SDA as output.
return temp; // Return the data from the USIDR
}
int main (void) {
// enable pull up resistors
bset(PORTB, 1);
bset(PORTB, 2);
bset(PORTB, 3);
// burn some time to let inputs settle
__builtin_avr_delay_cycles(20);
// this is a really inefficent way to do it, but i had the I/Os
// and a free 4 position switch, so why not. simpler than binary input.
// to read, all pull ups are enabled, and each pin of the switch
// is connected to a seperate IO. the IO that is low is switch pos
uint16_t delay = 60; // assume position 1 by default
// could use uint8_t and save some code space
// divide each delay by 4, then then delay for 4000ms in the loop
if (!bisset(PINB,3)) // position 2
delay = 120;
if (!bisset(PINB,1)) // position 3
delay = 180;
if (!bisset(PINB,2)) // position 4
delay = 300;
PORTB = 0; // disable pull ups
// enable output
bset(DDRB, 0);
while(true) {
send_signal(); // begin bulb exposure
// this is wasteful of power, but i tried using the wdt
// to let me sleep 1s in power down state, and it turns
// out that the wdt oscilator is way off. better to busy
// wait and be about correct than way out in left field
for(uint16_t i = 0; i <= delay; i++)
_delay_ms(1000);
send_signal(); // terminate bulb exposure
_delay_ms(10000); // wait for camera to recover its wits
}
}
int main (void)
{
const __memx void *p;
f1();
__builtin_avr_delay_cycles (1000);
p = &c0;
if (__builtin_avr_flash_segment (p) != 0)
abort();
p = &c1;
if (__builtin_avr_flash_segment (p) != 1)
abort();
if (__builtin_avr_flash_segment ("p") != -1)
abort();
exit (0);
return 0;
}
void shiftReg_loadStops(struct shiftOutReg *s, unsigned char data[]){
char temp;
//so fully load in the first 2 bytes
for(unsigned char byteCount = 0; byteCount<5; byteCount++){
for(unsigned char c = 1; c; c <<= 1){
*s->port &= ~(1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
temp = (data[byteCount]&c) ? 1 : 0; //this would be amazing if it works!
if(temp == 1){
*s->port |= (1 << s->SER);
}else{
*s->port &= ~(1 << s->SER);
}
*s->port |= (1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
}
}
for(unsigned char c = 1; c < 0b10000000; c <<= 1){
*s->port &= ~(1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
temp = (data[5]&c) ? 1 : 0; //this would be amazing if it works!
if(temp == 1){
*s->port |= (1 << s->SER);
}else{
*s->port &= ~(1 << s->SER);
}
*s->port |= (1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
}
*s->port &= ~(1 << s->SRCLK);
__builtin_avr_delay_cycles(1);
temp = (data[5]&0x80) ? 1 : 0; //this would be amazing if it works! It does!
if(temp == 1){
*s->port |= (1 << s->SER);
}else{
*s->port &= ~(1 << s->SER);
}
*s->port |= (1 << s->SRCLK);
*s->port |= (1 << s->RCLK);
//s->RCLK = 1;
__builtin_avr_delay_cycles(1);
*s->port &= ~((1 << s->SRCLK) | (1 << s->RCLK));
//s->RCLK = 0;
//s->SRCLK = 0;
}
void shiftReg_Clear_Registers(struct shiftOutReg *s){
*s->port &= ~(1 << s->SRCLR);
//no op
__builtin_avr_delay_cycles(2);
*s->port |= (1 << s->SRCLR);
}
/*---------------------------------------------------------------
USI Transmit and receive function. LSB of first byte in data
indicates if a read or write cycles is performed. If set a read
operation is performed.
Function generates (Repeated) Start Condition, sends address and
R/W, Reads/Writes Data, and verifies/sends ACK.
Success or error code is returned. Error codes are defined in
USI_TWI_Master.h
---------------------------------------------------------------*/
unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char *msg, unsigned char msgSize)
{
unsigned char tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges.
unsigned char tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges.
USI_TWI_state.errorState = 0;
USI_TWI_state.addressMode = TRUE;
#ifdef PARAM_VERIFICATION
if(msg > (unsigned char*)RAMEND) // Test if address is outside SRAM space
{
USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND;
return (FALSE);
}
if(msgSize <= 1) // Test if the transmission buffer is empty
{
USI_TWI_state.errorState = USI_TWI_NO_DATA;
return (FALSE);
}
#endif
#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution.
if( USISR & (1<<USISIF) )
{
USI_TWI_state.errorState = USI_TWI_UE_START_CON;
return (FALSE);
}
if( USISR & (1<<USIPF) )
{
USI_TWI_state.errorState = USI_TWI_UE_STOP_CON;
return (FALSE);
}
if( USISR & (1<<USIDC) )
{
USI_TWI_state.errorState = USI_TWI_UE_DATA_COL;
return (FALSE);
}
#endif
if ( !(*msg & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation.
{
USI_TWI_state.masterWriteDataMode = TRUE;
}
/* Release SCL to ensure that (repeated) Start can be performed */
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PORT_USI & (1<<PIN_USI_SCL)) ); // Verify that SCL becomes high.
#ifdef TWI_FAST_MODE
__builtin_avr_delay_cycles( T4_TWI ); // Delay for T4TWI if TWI_FAST_MODE
#else
__builtin_avr_delay_cycles( T2_TWI ); // Delay for T2TWI if TWI_STANDARD_MODE
#endif
/* Generate Start Condition */
PORT_USI &= ~(1<<PIN_USI_SDA); // Force SDA LOW.
__builtin_avr_delay_cycles( T4_TWI );
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.
#ifdef SIGNAL_VERIFY
if( !(USISR & (1<<USISIF)) )
{
USI_TWI_state.errorState = USI_TWI_MISSING_START_CON;
return (FALSE);
}
#endif
/*Write address and Read/Write data */
do
{
/* If masterWrite cycle (or inital address tranmission)*/
if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode)
{
/* Write a byte */
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
USIDR = *(msg++); // Setup data.
USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) )
{
if ( USI_TWI_state.addressMode )
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS;
else
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA;
return (FALSE);
}
USI_TWI_state.addressMode = FALSE; // Only perform address transmission once.
}
/* Else masterRead cycle*/
else
{
/* Read a data byte */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit );
/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if( msgSize == 1) // If transmission of last byte was performed.
{
USIDR = 0xFF; // Load NACK to confirm End Of Transmission.
}
else
{
USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low.
}
USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK.
}
} while( --msgSize) ; // Until all data sent/received.
USI_TWI_Master_Stop(); // Send a STOP condition on the TWI bus.
/* Transmission successfully completed*/
return (TRUE);
}
