void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count)
{
//set_dma_addr
REG_DMAC_DSAR(ch) = PHYSADDR(srcAddr);
REG_DMAC_DDAR(ch) = PHYSADDR(dstAddr);
//set_dma_count
REG_DMAC_DTCR(ch) = count / dma_unit_size[ch];
//enable_dma
REG_DMAC_DCCSR(ch) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
__dmac_enable_channel(ch);
if (dma_irq[ch])
__dmac_channel_enable_irq(ch);
}
static void enable_dma_irq(unsigned int irq)
{
unsigned int intc_irq;
if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) /* DMAC Group 0 irq */
intc_irq = IRQ_DMAC0;
else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) /* DMAC Group 1 irq */
intc_irq = IRQ_DMAC1;
else {
printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
return;
}
__intc_unmask_irq(intc_irq);
__dmac_channel_enable_irq(irq - IRQ_DMA_0);
}
void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count)
{
// printf("dma gao start1\n");
dma_stop(ch);
//set_dma_addr
REG_DMAC_DSAR(ch) = srcAddr;
REG_DMAC_DDAR(ch) = dstAddr;
//set_dma_count
REG_DMAC_DTCR(ch) = count / dma_unit_size[ch];
//enable_dma
REG_DMAC_DCMD(ch) = dma_mode[ch];
REG_DMAC_DCCSR(ch) &= ~(DMAC_DCCSR_HLT|DMAC_DCCSR_TC|DMAC_DCCSR_AR);
REG_DMAC_DCCSR(ch) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
__dmac_enable_channel(ch);
if (dma_irq[ch])
__dmac_channel_enable_irq(ch);
}
static void enable_dma_irq(unsigned int irq)
{
__intc_unmask_irq(IRQ_DMAC);
__dmac_channel_enable_irq(irq - IRQ_DMA_0);
}
