void __init mach_setup (char **cmdline)
{
/* Enable the instruction and data caches (if present) */
#if CONFIG_XILINX_MICROBLAZE0_USE_ICACHE==1
__flush_icache_all();
__enable_icache();
#endif
#if CONFIG_XILINX_MICROBLAZE0_USE_DCACHE==1
__flush_dcache_all();
__enable_dcache();
#endif
printk (KERN_INFO "CPU: MICROBLAZE\n");
/* Now called from tty_io.c:init_console(), where it should be (/
/* xmbrs_console_init(); */
/*
* Enable master control on interrupt controller. Note
* this does not enable interrupts in the processor, nor
* does it enable individual IRQs on the controller. Just
* initialises the intc in preparation for these things */
microblaze_intc_master_enable();
#ifdef CONFIG_XILINX_GPIO_0_INSTANCE
/* Configure the GPIO */
/* 8 inputs, 16 outputs */
/* microblaze_gpio_setdir(CONFIG_XILINX_GPIO_0_BASEADDR,MICROBLAZE_GPIO_DIR); */
#endif
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_leave_lowpower\n");
if (((cpu == 4) && (cpu_online(5) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 5) && (cpu_online(4) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 6) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(7) == 0)) ||
((cpu == 7) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(6) == 0)))
{
/* Enable CA15L snoop function */
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write_phy(virt_to_phys(MP1_AXI_CONFIG), REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#else //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write(MP1_AXI_CONFIG, REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#endif //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
/* Enable snoop requests and DVM message requests */
REG_WRITE(CCI400_SI3_SNOOP_CONTROL, REG_READ(CCI400_SI3_SNOOP_CONTROL) | (SNOOP_REQ | DVM_MSG_REQ));
while (REG_READ(CCI400_STATUS) & CHANGE_PENDING);
}
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
void __invalidate_dcache_range(unsigned long start, unsigned long end)
{
unsigned int i;
unsigned flags;
unsigned int align;
if (cpuinfo.use_dcache) {
/*
* No need to cover entire cache range,
* just cover cache footprint
*/
end = min(start + cpuinfo.dcache_size, end);
align = ~(cpuinfo.dcache_line - 1);
start &= align; /* Make sure we are aligned */
/* Push end up to the next cache line */
end = ((end & align) + cpuinfo.dcache_line);
local_irq_save(flags);
__disable_dcache();
for (i = start; i < end; i += cpuinfo.dcache_line)
__invalidate_dcache(i);
__enable_dcache();
local_irq_restore(flags);
}
}
void __init mach_setup (char **cmdline)
{
/* Enable the instruction and data caches (if present) */
#if CONFIG_XILINX_MICROBLAZE0_USE_ICACHE==1
__enable_icache();
#endif
#if CONFIG_XILINX_MICROBLAZE0_USE_DCACHE==1
__enable_dcache();
#endif
printk (KERN_INFO "CPU: MICROBLAZE\n");
/* memcons_setup (); */
/* This is defined as an initcall, but doesn't seem to work...*/
xmbrs_console_init();
/*
* Enable master control on interrupt controller. Note
* this does not enable interrupts in the processor, nor
* does it enable individual IRQs on the controller. Just
* initialises the intc in preparation for these things */
microblaze_intc_master_enable();
/* Configure the GPIO */
/* 8 inputs, 16 outputs */
/* microblaze_gpio_setdir(CONFIG_XILINX_GPIO_0_BASEADDR,MICROBLAZE_GPIO_DIR); */
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_leave_lowpower\n");
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
/* HOTPLUG_INFO("cpu_leave_lowpower\n"); */
if ((cpu == 3 && cpu_online(2) == 0) || (cpu == 2 && cpu_online(3) == 0)) {
spm_write(CA15_MISC_DBG, spm_read(CA15_MISC_DBG) & ~0x11);
spm_write(CA15_CCI400_DVM_EN, spm_read(CA15_CCI400_DVM_EN) | 0x3);
/* wait cci change pending */
while (spm_read(CCI400_STATUS) & 0x1)
;
}
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
void __invalidate_dcache_all(void)
{
unsigned int i;
unsigned flags;
if (cpuinfo.use_dcache) {
local_irq_save(flags);
__disable_dcache();
/*
* Just loop through cache size and invalidate,
* no need to add CACHE_BASE address
*/
for (i = 0; i < cpuinfo.dcache_size;
i += cpuinfo.dcache_line)
__invalidate_dcache(i);
__enable_dcache();
local_irq_restore(flags);
}
}
void __init setup_arch(char **cmdline_p)
{
#ifdef CONFIG_CMDLINE_FORCE
strlcpy(cmd_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
strlcpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
#endif
*cmdline_p = cmd_line;
console_verbose();
unflatten_device_tree();
/* NOTE I think that this function is not necessary to call */
/* irq_early_init(); */
setup_cpuinfo();
__invalidate_icache_all();
__enable_icache();
__invalidate_dcache_all();
__enable_dcache();
panic_timeout = 120;
setup_memory();
#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
printk(KERN_NOTICE "Self modified code enable\n");
#endif
#ifdef CONFIG_VT
#if defined(CONFIG_XILINX_CONSOLE)
conswitchp = &xil_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
}